libz.so.1 inflate _init inflateInit_ inflateReset _fini inflateEnd _Jv_RegisterClasses __gmon_start__ libc.so.6 putchar strcpy getgid __strtod_internal stdout strerror fdopen memmove getopt_long ftello64 getenv __rawmemchr __strtol_internal getpid qsort memcpy getuid malloc optarg ldexp vsnprintf __strtoul_internal fflush strncasecmp abort chmod __lxstat strrchr calloc ctime strcat dcgettext fseek optind fnmatch umask ferror strstr strncmp strncpy unlink strcasecmp realloc __strdup sscanf strncat fread sbrk gettimeofday memset ftell __assert_fail strcmp asprintf fclose strcspn stderr mkstemp fputc mkdtemp fwrite access __xstat __errno_location __fxstat bindtextdomain fopen _IO_putc fileno _IO_stdin_used _exit strspn __libc_start_main strchr fputs realpath warn fcntl fseeko64 frexp vfprintf strpbrk free fopen64 __environ _edata __bss_start _end GLIBC_2.2.3 GLIBC_2.2 GLIBC_2.3 GLIBC_2.1 GLIBC_2.0
all-headers private-headers architecture archive-headers debugging debugging-tags demangle disassemble disassemble-all disassembler-options disassemble-zeroes dynamic-reloc dynamic-syms file-headers file-offsets file-start-context full-contents help line-numbers no-show-raw-insn prefix-addresses section-headers source special-syms include dwarf wide .eh_frame Report bugs to %s. %3d %-13s %08lx %08lx 2**%u ALLOC CONSTRUCTOR READONLY ROM DEBUGGING NEVER_LOAD EXCLUDE SORT_ENTRIES BLOCK CLINK SMALL_DATA SHARED THREAD_LOCAL LINK_ONCE_SAME_SIZE LINK_ONCE_SAME_CONTENTS LINK_ONCE_DISCARD LINK_ONCE_ONE_ONLY (COMDAT %s %ld) gnu_compiled gcc2_compiled <%s -0x +0x (File Offset: 0x%lx) .gnu.linkonce.wi. .debug_info No %s section present Contents of %s section: %-6d %-6s HdrSym %-6d %-6d %-6d %-6lu * DYNAMIC SYMBOL TABLE: no symbols OFFSET %*s TYPE %*s VALUE %s(): ??? %s:%u *unknown* %-16s %-16d *unknown* RELOCATION RECORDS FOR [%s]: (none) %s: file format %s architecture: %s, flags 0x%08x: HAS_RELOC EXEC_P HAS_LINENO HAS_DEBUG HAS_SYMS HAS_LOCALS WP_TEXT D_PAGED BFD_IS_RELAXABLE HAS_LOAD_PAGE start address 0x Sections: Flags Pg %s: not a dynamic object .stab .stab.exclstr .stab.excl .stab.indexstr .stab.index LC_SYMTAB.stabstr LC_SYMTAB.stabs $GDB_STRINGS$ $GDB_SYMBOLS$ DYNAMIC RELOCATION RECORDS Can't use supplied machine %s In archive %s: binutils , unknown demangling style `%s' --adjust-vma --start-address --stop-address unrecognized -E option objdump a.out Disassembly of section %s: ... %s: : *unknown* : %s : %d Contents of section %s: LC_SEGMENT.__DWARFA.__zdebug_abbrev LC_SEGMENT.__DWARFA.__zdebug_aranges LC_SEGMENT.__DWARFA.__zdebug_frame LC_SEGMENT.__DWARFA.__zdebug_info LC_SEGMENT.__DWARFA.__zdebug_line LC_SEGMENT.__DWARFA.__zdebug_pubnames LC_SEGMENT.__DWARFA.__zdebug_macinfo LC_SEGMENT.__DWARFA.__zdebug_str LC_SEGMENT.__DWARFA.__zdebug_loc LC_SEGMENT.__DWARFA.__zdebug_pubtypes LC_SEGMENT.__DWARFA.__zdebug_ranges LC_SEGMENT.__DWARFA.__zdebug_static_func LC_SEGMENT.__DWARFA.__zdebug_static_vars LC_SEGMENT.__DWARFA.__zdebug_types LC_SEGMENT.__DWARFA.__zdebug_weaknames LC_SEGMENT.__DWARFA.__debug_abbrev LC_SEGMENT.__DWARFA.__debug_aranges LC_SEGMENT.__DWARFA.__debug_frame LC_SEGMENT.__DWARFA.__debug_info LC_SEGMENT.__DWARFA.__debug_line LC_SEGMENT.__DWARFA.__debug_pubnames LC_SEGMENT.__DWARFA.__debug_macinfo LC_SEGMENT.__DWARFA.__debug_str LC_SEGMENT.__DWARFA.__debug_loc LC_SEGMENT.__DWARFA.__debug_pubtypes LC_SEGMENT.__DWARFA.__debug_ranges LC_SEGMENT.__DWARFA.__debug_static_func LC_SEGMENT.__DWARFA.__debug_static_vars LC_SEGMENT.__DWARFA.__debug_types LC_SEGMENT.__DWARFA.__debug_weaknames Usage: %s Display information from object . At least one of the following switches must be given: -a, --archive-headers Display archive header information -f, --file-headers Display the contents of the overall file header -p, --private-headers Display object format specific file header contents -h, --[section-]headers Display the contents of the section headers -x, --all-headers Display the contents of all headers -d, --disassemble Display assembler contents of executable sections -D, --disassemble-all Display assembler contents of all sections -S, --source Intermix source code with disassembly -s, --full-contents Display the full contents of all sections requested -g, --debugging Display debug information in object file -e, --debugging-tags Display debug information using ctags style -G, --stabs Display (in raw form) any STABS info in the file -W, --dwarf Display DWARF info in the file -t, --syms Display the contents of the symbol table(s) -T, --dynamic-syms Display the contents of the dynamic symbol table -r, --reloc Display the relocation entries in the file -R, --dynamic-reloc Display the dynamic relocation entries in the file @ Read options from -v, --version Display this program's version number -i, --info List object formats and architectures supported -H, --help Display this information The following switches are optional: -b, --target=BFDNAME Specify the target object format as BFDNAME -m, --architecture=MACHINE Specify the target architecture as MACHINE -j, --section=NAME Only display information for section NAME -M, --disassembler-options=OPT Pass text OPT on to the disassembler -EB --endian=big Assume big endian format when disassembling -EL --endian=little Assume little endian format when disassembling --file-start-context Include context from start of file (with -S) -I, --include=DIR Add DIR to search list for source files -l, --line-numbers Include line numbers and filenames in output -F, --file-offsets Include file offsets when displaying information -C, --demangle[=STYLE] Decode mangled/processed symbol names The STYLE, if specified, can be `auto', `gnu', `lucid', `arm', `hp', `edg', `gnu-v3', `java' or `gnat' -w, --wide Format output for more than 80 columns -z, --disassemble-zeroes Do not skip blocks of zeroes when disassembling --start-address=ADDR Only process data whose address is >= ADDR --stop-address=ADDR Only process data whose address is <= ADDR --prefix-addresses Print complete address alongside disassembly --[no-]show-raw-insn Display hex alongside symbolic disassembly --adjust-vma=OFFSET Add OFFSET to all displayed section addresses --special-syms Include special symbols in symbol dumps Unrecognized form: %lu (not inlined) (inlined) (ANSI C) (non-ANSI C) (Ada) (C++) (Cobol 74) (Cobol 85) (FORTRAN 77) (Fortran 90) (ANSI Pascal) (Modula 2) (Java) (ANSI C99) (ADA 95) (Fortran 95) (PLI) (Objective C) (Objective C++) (Unified Parallel C) (D) (MIPS assembler) (implementation defined: %lx) (Unknown: %lx) (void) (machine address) (boolean) (complex float) (float) (signed) (signed char) (unsigned) (unsigned char) (imaginary float) (decimal float) (packed_decimal) (numeric_string) (edited) (signed_fixed) (unsigned_fixed) (HP_float80) (HP_complex_float80) (HP_float128) (HP_complex_float128) (HP_floathpintel) (HP_imaginary_float80) (HP_imaginary_float128) (user defined type) (unknown type) (public) (protected) (private) (unknown accessibility) (local) (exported) (qualified) (unknown visibility) (none) (virtual) (pure_virtual) (unknown virtuality) (case_sensitive) (up_case) (down_case) (case_insensitive) (unknown case) (normal) (program) (nocall) (user defined) (unknown convention) (undefined) (row major) (column major) (location list) [without DW_AT_frame_base] [Abbrev Number: %ld No comp units in %s section ? The section %s contains: Unable to locate %s section! 64-bit 32-bit Length: 0x%lx (%s) Version: %d Abbrev Offset: %ld Pointer Size: %d <%2lx> %-18s: Offset Name %-6ld %s Unhandled data length: %d Address Length The section %s contains: %08lx ZERO terminator eh %08lx %08lx %08lx CIE Version: %d Code alignment factor: %u Data alignment factor: %d Return address column: %d Augmentation data: %02x DW_CFA_restore: %s DW_CFA_set_loc: %08lx DW_CFA_undefined: %s DW_CFA_same_value: %s DW_CFA_register: %s in DW_CFA_remember_state DW_CFA_restore_state DW_CFA_def_cfa: %s ofs %d DW_CFA_def_cfa_offset: %d DW_CFA_nop DW_CFA_def_cfa_expression ( DW_CFA_expression: %s ( DW_CFA_val_expression: %s ( DW_CFA_GNU_window_save DW_CFA_GNU_args_size: %ld CU: %s: CU: %s/%s: UNKNOWN: length %d ./%s:[++] %s/%s: Set ISA to %lu 0x%lx%s %-35s %11d %#18lx %s %11d %#18lx Opcodes: Opcode %d has %d args The Directory Table: %s The File Name Table: Entry Dir Time Size Name %lu Line Number Statements: and Line by %d to %d Extended opcode %d: End of Sequence set Address to 0x%lx %d %s DW_LNE_HP_negate_is_UV_update DW_LNE_HP_push_context DW_LNE_HP_pop_context DW_LNE_HP_set_routine_name DW_LNE_HP_set_sequence DW_LNE_HP_define_proc user defined: length %d Copy Advance PC by %lu to 0x%lx Advance Line by %d to %d Set column to %lu Set is_stmt to %d Set basic block Set prologue_end to true Set epilogue_begin to true The %s section is empty. 0x%8.8lx %2.2x %8.8lx (base address) (start == end) (start > end) Offset Begin End (base address) II MI QI UI YI ]I aI eI u y } iI mI rI wI |I I I I I I I I I I I I I I I I I aT I I I nI sI xI }I I I I I I ( K I / I I I I I J J J J J J J J $J (J ,J 0J I I I I aT I I I mI rI wI |I I I I I nI sI xI }I I I I I J J I ( K I / I I N U \ c j q x A O w 4 ~ $ 5 F q . ? P t 1 E i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i \ $ P | & 7 H Y j { l l l l l l l l : : E _ : l G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G c a 3 a a a a % j % T % T ] % F G % % % % T T T T _ p . ? P a , = N = ? ? > ? @ ? `> ? J? = = ? = = ? @ V@ ? ? @ V@ @ = = = = = = @ = = = = = = = = = = = = = = = = = > = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = > = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = q> L 5L K K J HK J kJ 2J I PI {H H I G G M OM L P XO O O @ @ @ @ @ @ L @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ N N %N @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ M @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ = @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ N Y X Z >Z eZ Z Z [ [ B[ X X m[ Sf f f %g `g g g /h bh h h i Di Ej j j k Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej xl l l l l l l m m Ej Ej Ej Ej Ej Ej ,m DW_OP_GNU_push_tls_address or DW_OP_HP_unknown DW_OP_GNU_encoded_addr: fmt:%02x addr: DW_AT_MIPS_software_pipeline_depth DW_AT_HP_all_variables_modifiable DW_AT_MIPS_fde or DW_AT_HP_unmodifiable DW_MACINFO_start_file - lineno: %d filenum: %d DW_MACINFO_define - lineno : %d macro : %s DW_MACINFO_undef - lineno : %d macro : %s DW_MACINFO_vendor_ext - constant : %d string : %s Displaying the debug contents of section %s is not yet supported. Internal error: DWARF version is not 2 or 3. DW_FORM_data8 is unsupported when sizeof (unsigned long) != 8 DW_FORM_strp offset too big: %lx (indirect string, offset: 0x%lx): %s (declared as inline but ignored) (declared as inline and inlined) (Unknown inline attribute value: %lx) Offset %lx used as value for DW_AT_import attribute of DIE at offset %lx is too big. Reserved length value (%lx) found in section %s Corrupt unit length (%lx) found in section %s Not enough memory for a debug info array of %u entries Compilation Unit @ offset 0x%lx: Debug info is corrupted, length of CU at %lx extends beyond end of section (length = %lx) CU at offset %lx contains corrupt or unsupported version number: %d. Debug info is corrupted, abbrev offset (%lx) is larger than abbrev section size (%lx) Bogus end-of-siblings marker detected at offset %lx in .debug_info section Further warnings about bogus end-of-sibling markers suppressed <%d><%lx>: Abbrev Number: %lu DIE at offset %lx refers to abbreviation number %lu which does not exist .debug_info offset of 0x%lx in %s section does not point to a CU header. Only DWARF 2 and 3 pubnames are currently supported Length: %ld Version: %d Offset into .debug_info section: 0x%lx Size of area in .debug_info section: %ld Only DWARF 2 and 3 aranges are currently supported. Length: %ld Version: %d Offset into .debug_info: 0x%lx Pointer Size: %d Segment Size: %d Pointer size + Segment size is not a power of two. Address Length Invalid length %#08lx in FDE at %#08lx %08lx %08lx %08lx CIE "%s" cf=%d df=%d ra=%d Augmentation: "%s" Invalid CIE pointer %#08lx in FDE at %#08lx %08lx %08lx %08lx FDE cie=%08lx pc=%08lx..%08lx DW_CFA_advance_loc: %d to %08lx DW_CFA_offset: %s at cfa%+ld DW_CFA_advance_loc1: %ld to %08lx DW_CFA_advance_loc2: %ld to %08lx DW_CFA_advance_loc4: %ld to %08lx DW_CFA_offset_extended: %s at cfa%+ld DW_CFA_val_offset: %s at cfa%+ld DW_CFA_restore_extended: %s Mismatched DW_CFA_restore_state DW_CFA_def_cfa_register: %s DW_CFA_offset_extended_sf: %s at cfa%+ld DW_CFA_val_offset_sf: %s at cfa%+ld DW_CFA_def_cfa_sf: %s ofs %d DW_CFA_def_cfa_offset_sf: %d DW_CFA_MIPS_advance_loc8: %ld to %08lx DW_CFA_GNU_negative_offset_extended: %s at cfa%+ld DW_CFA_??? (User defined call frame op: %#x) unsupported or unknown Dwarf Call Frame Instruction number: %#x Decoded dump of debug contents of section %s: The line info appears to be corrupt - the section is too small Only DWARF version 2 and 3 line info is currently supported. File name Line number Starting address badly formed extended line op encountered! Unknown opcode %d with operands: Unable to load/parse the .debug_info section, so cannot interpret the %s section. Raw dump of debug contents of section %s: Offset: 0x%lx Length: %ld DWARF Version: %d Prologue Length: %d Minimum Instruction Length: %d Initial value of 'is_stmt': %d Line Base: %d Line Range: %d Opcode Base: %d The Directory Table is empty. The File Name Table is empty. Special opcode %d: advance Address by %lu to 0x%lx define new File Table entry DW_LNE_HP_set_file_line_column DW_LNE_HP_negate_post_semantics DW_LNE_HP_negate_function_exit DW_LNE_HP_negate_front_end_logical Set File Name to entry %d in the File Name Table Advance PC by constant %lu to 0x%lx Advance PC by fixed size amount %lu to 0x%lx Location lists in .debug_info section aren't in ascending order! No location lists in .debug_info section! Location lists in %s section start at 0x%lx Offset Begin End Expression There is a hole [0x%lx - 0x%lx] in .debug_loc section. There is an overlap [0x%lx - 0x%lx] in .debug_loc section. Offset 0x%lx is bigger than .debug_loc section size. Location list starting at offset 0x%lx is not terminated. There are %ld unused bytes at the end of section %s Range lists in .debug_info section aren't in ascending order! No range lists in .debug_info section! Range lists in %s section start at 0x%lx There is a hole [0x%lx - 0x%lx] in %s section. There is an overlap [0x%lx - 0x%lx] in %s section. K ` . z M 1 a L ] n ] % < E T ] 4 . [ ` < z M 1 a L ] $ c / K A ? % E Q . S i [ prepend_type append_type append_parent substitute_type pop_type pr_start_compilation_unit pr_start_source pr_pointer_type pr_function_type pr_reference_type pr_range_type pr_fix_visibility pr_end_struct_type pr_class_baseclass pr_class_start_method pr_class_method_variant pr_class_static_method_variant w tg_fix_visibility tg_end_struct_type tg_class_baseclass tg_class_method_variant tg_class_static_method_variant o !_TAG_FILE_FORMAT 2 /extended format/ !_TAG_FILE_SORTED 0 /0=unsorted, 1=sorted/ !_TAG_PROGRAM_AUTHOR Ian Lance Taylor, Salvador E. Tropea and others // !_TAG_PROGRAM_NAME objdump /From GNU binutils/ ../../../toolchain/android-toolchain/binutils-2.19/binutils/prdbg.c s[0] == ' ' && s[1] == ' ' && s[2] == '\0' info->stack != ((void *)0) && info->stack->next != ((void *)0) info->stack->next != ((void *)0) info->stack->next->method != ((void *)0) /* file %s line %lu addr %s */ %s %s 0;" kind:g enum:%s value:%s info->stack->visibility != DEBUG_VISIBILITY_IGNORE %s %s 0;" kind:m type:%s %s:%s access:%s %s %s 0;" kind:x type:%s class:%s access:%s %s %s 0;" kind:p type:%s class:%s %s %s 0;" kind:p type:%s class:%s access:%s %s %s 0;" kind:v type:const int value:%s %s %s 0;" kind:v type:const double value:%g %s %s 0;" kind:v type:const %s value:%s info->stack != ((void *)0) info->indent == 0 void %sint%d float float%d complex bool%d enum /* undefined */ = } (*|) *| &| range ( ): |[%s] |[%s:%s] /* string */ set { /* bitstring */ ::| union class const | volatile | struct union %%anon%u { /* size %u id %u public private /* ignore */ t[len - 1] == ' ' ; /* bitsize info->indent >= 2 size vtable self static virtual private /* unknown visibility */ public protected /* bitpos const context voffset /* id %u */ typedef %s; const int %s = %s; const double %s = %g; const %s %s = %s; register %s /* %s */; %s /* %s */ { /* %s */ } /* %s */ %s %s 0;" kind:e type:%s struct union %s %s 0;" kind:%c union class %s::%s %s %s 0;" kind:c type:%s inherits:%s %s %s 0;" kind:t type:%s :: %s %s 0;" kind:v type:%s file: register: class:%s %s %s ;" kind:%c type:%s Last stabs entries before error: n_type n_desc n_value string %s: %s: stab entry %ld is corrupt, strx = 0x%x, type = %d %s: no recognized debugging information %s: %s: %s .debug info->units == ((void *)0) debug_add_to_current_namespace: no current file ../../../toolchain/android-toolchain/binutils-2.19/binutils/debug.c debug_start_source: no debug_set_filename call debug_record_function: no debug_set_filename call debug_record_parameter: no current function debug_end_function: no current function debug_end_function: some blocks were not closed debug_start_block: no current block debug_end_block: no current block debug_end_block: attempt to close top level block debug_record_line: no current unit debug_start_common_block: not implemented debug_end_common_block: not implemented debug_record_label: not implemented debug_record_variable: no current file debug_tag_type: no current file debug_tag_type: extra tag attempted debug_make_undefined_type: unsupported kind debug_name_type: no current file Warning: changing type size from %d to %d debug_find_named_type: no current compilation unit debug_get_real_type: circular debug information for %s type->kind == DEBUG_KIND_STRUCT || type->kind == DEBUG_KIND_UNION || type->kind == DEBUG_KIND_CLASS || type->kind == DEBUG_KIND_UNION_CLASS name->kind == DEBUG_OBJECT_TAG debug_write_type: illegal type encountered type->u.kclass->id > info->base_id debug_set_filename 3 D } debug_set_class_id debug_write_class_type debug_write_type < J f P o ; " H Warning: %s: %s numeric overflow Bad stab: %s Unrecognized XCOFF type %d unsigned char unsigned short unsigned long integer boolean short real character logical*1 logical*2 logical*4 logical double complex integer*1 integer*2 integer*4 wchar unsigned long long logical*8 integer*8 stringptr bad mangled name `%s' bool __float128 unsigned __int128 Unexpected demangled varargs long long unsigned int long long int short unsigned int __wchar_t NoSuchStrinG__ ::NoSuchStrinG 01000000000000000000000; 0777777777777777777777; 01777777777777777777777; missing index type _vptr$ unnamed $vb type FOO _vb$ unrecognized C++ abbreviation INVALID_CPLUSPLUS_ABBREV member function type missing __ct __dt __%s%s __%s%s%d No mangling for "%s" N_LBRAC not within function Too many N_RBRACs Undefined N_EXCL this eh_throw unknown C++ encoded name gcc2_compiled. gcc_compiled. Type file number %d out of range Type index number %d out of range Unrecognized demangle component %d Failed to print demangled template Couldn't get demangled builtin type Unrecognized demangled builtin type Unexpected type in v3 arglist demangling unrecognized cross reference type unknown visibility character for field unknown virtual character for baseclass unknown visibility character for baseclass const/volatile indicator missing Demangled name is not a function no argument types in mangled string B a ' I [ u % G a { ' I k R * d d d d d 6 > } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } A A A A A A A A A A } } } } } } } } } } } } } * } } } } } } } } } } } } } } } } } } } } } } } } } } U } } } } } } } } } 2 } D * * * * W W * % * * 5 F h h W h % Z ! /! + e @ 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 < < = < #> #> #> #> #> #> #> #> #> #> = = = = = = = = = r; = = = = = = = = = = = = = A> = r; = = = = = = = = = = = 2 = = = = = = = = = = = = = = = = = = = = = K J J SO dL J J J J J J J J %L J J M =M J 4N J WJ J J J J J J J J nN J N J J SO J J J J J WJ J J J O J P WJ hK J K I pQ pQ pQ pQ pQ pQ I pQ pQ pQ pQ pQ Q pQ pQ pQ pQ pQ pQ pQ pQ pQ pQ pQ pQ pQ pQ Q pQ I [ d n H q S F G U p f K H p j h } P h ieee_builtin_type Z ] ] ] c] >] ] \ \ \ \ p\ S\ 6\ [ [ [ p[ K[ &[ [ Z Z Z filename != ((void *)0) GNU objcopy bfd_make_section bfd_set_section_contents bfd_set_section_size __anon%u localp == nt->type.localp vclass != ((void *)0) _vb$%s _b$%s h != ((void *)0) info->block_depth == 1 unexpected end of debugging information unsupported IEEE expression operator ../../../toolchain/android-toolchain/binutils-2.19/binutils/ieee.c C++ default values not in a function reference parameter is not a pointer unrecognized C++ reference type C++ reference in class with no fields C++ base class not found in container C++ data member not found in container bad type for C++ method function no type information for C++ method function unrecognized C++ object overhead spec Pascal file name not supported IEEE string length overflow: %u ! ((&info->vars)->head == ((void *)0)) IEEE unsupported integer type size %u IEEE unsupported float type size %u IEEE unsupported complex type size %u info->type_stack != ((void *)0) && info->type_stack->next != ((void *)0) && ! ((&info->type_stack->next->type.strdef)->head == ((void *)0)) info->type_stack != ((void *)0) && ! ((&info->type_stack->type.strdef)->head == ((void *)0)) info->type_stack != ((void *)0) && info->type_stack->type.classdef != ((void *)0) info->type_stack != ((void *)0) && info->type_stack->type.name != ((void *)0) && info->type_stack->next != ((void *)0) && info->type_stack->next->type.classdef != ((void *)0) && ! ((&info->type_stack->next->type.strdef)->head == ((void *)0)) info->type_stack != ((void *)0) && info->type_stack->type.classdef != ((void *)0) && info->type_stack->type.classdef->method == ((void *)0) info->type_stack != ((void *)0) && info->type_stack->type.classdef != ((void *)0) && info->type_stack->type.classdef->method != ((void *)0) info->pending_ranges != ((void *)0) *globals* .bf .ef %ld: unexpected .ef .bb .eb bfd_coff_get_syment failed: %s parse_coff_type: Bad type code 0x%x bfd_coff_get_auxent failed: %s %ld: .bf without preceding function ; ; b ' b ~ B g :%s[%s] %s: arm-unknown-eabi %s: Matching formats: Supported targets: %s: supported targets: Supported architectures: %s: supported architectures: little endian endianness unknown big endian %.12s %.4s %s %ld/%ld %6ld %s %s: bad number: %s '%s': No such file abfd != ((void *)0) %s(%s) BFD header file version %s (GNU Binutils) 2.19 %s (header %s, data %s) COLUMNS %*s UNKNOWN! %*s can't set BFD default target to `%s': %s Warning: could not locate '%s'. reason: %s Warning: '%s' is not an ordinary file ../../../toolchain/android-toolchain/binutils-2.19/binutils/bucomm.c bfd_get_archive_filename GNU %s %s Copyright 2007 Free Software Foundation, Inc. This program is free software; you may redistribute it under the terms of the GNU General Public License version 3 or (at your option) any later version. This program has absolutely no warranty. raw Select raw register names gcc lr std apcs a3 v1 v6 v7 v8 special-atpcs WR SL FP vs vc hi pli%c %a dbg%c #%0-3d dmb%c %U dsb%c %U isb%c %U sdiv%c %8-11r, %16-19r, %0-3r udiv%c %8-11r, %16-19r, %0-3r nop%c.w yield%c.w wfe%c.w wfi%c.w sev%c.w nop%c.w {%0-7d} clrex%c cpsie.w %7'a%6'i%5'f%X cpsid.w %7'a%6'i%5'f%X bxj%c %16-19r%x rfedb%c %16-19r%21'! rfeia%c %16-19r%21'! mrs%c %8-11r, %D cps #%0-4d%X tbb%c [%16-19r, %0-3r]%x cpsie %7'a%6'i%5'f, #%0-4d%X cpsid %7'a%6'i%5'f, #%0-4d%X subs%c pc, lr, #%0-7d msr%c %C, %16-19r ldrex%c %12-15r, [%16-19r] srsdb%c %16-19r%21'!, #%0-4d srsia%c %16-19r%21'!, #%0-4d sxth%c.w %8-11r, %0-3r%R uxth%c.w %8-11r, %0-3r%R sxtb16%c %8-11r, %0-3r%R uxtb16%c %8-11r, %0-3r%R sxtb%c.w %8-11r, %0-3r%R uxtb%c.w %8-11r, %0-3r%R qadd%c %8-11r, %0-3r, %16-19r qsub%c %8-11r, %0-3r, %16-19r rev%c.w %8-11r, %16-19r rev16%c.w %8-11r, %16-19r rbit%c %8-11r, %16-19r revsh%c.w %8-11r, %16-19r sel%c %8-11r, %16-19r, %0-3r clz%c %8-11r, %16-19r bfc%c %8-11r, %E tst%c.w %16-19r, %S teq%c %16-19r, %S cmn%c.w %16-19r, %S cmp%c.w %16-19r, %S tst%c.w %16-19r, %M teq%c %16-19r, %M cmn%c.w %16-19r, %M cmp%c.w %16-19r, %M mov%20's%c.w %8-11r, %S mvn%20's%c.w %8-11r, %S smc%c %K mov%20's%c.w %8-11r, %M mvn%20's%c.w %8-11r, %M pld%c %a pkhbt%c %8-11r, %16-19r, %S pkhtb%c %8-11r, %16-19r, %S sbfx%c %8-11r, %16-19r, %F ubfx%c %8-11r, %16-19r, %F str%wt%c %12-15r, %a bfi%c %8-11r, %16-19r, %E ldr%wt%c %12-15r, %a addw%c %8-11r, %16-19r, %I movw%c %8-11r, %J subw%c %8-11r, %16-19r, %I movt%c %8-11r, %J stmia%c.w %16-19r%21'!, %m ldmia%c.w %16-19r%21'!, %m stmdb%c %16-19r%21'!, %m ldmdb%c %16-19r%21'!, %m str%w%c.w %12-15r, %a ldr%w%c.w %12-15r, %a undefined (bcc, cond=0xF) undefined (bcc, cond=0xE) b%22-25c.w %b%X b%c.w %B%x blx%c %B%x bl%c %B%x undefined wcid wcon wcssf wcasf reserved wcgr0 wcgr1 wcgr2 wcgr3 wr0 wr1 wr2 wr3 wr4 wr5 wr6 wr7 wr8 wr9 wr10 wr11 wr12 wr13 wr14 wr15 bus bc hus hc hss wus wc wss dus dc dss 1.0 2.0 3.0 4.0 5.0 0.5 10.0 mia%c acc0, %0-3r, %12-15r miaph%c acc0, %0-3r, %12-15r mar%c acc0, %12-15r, %16-19r mra%c %12-15r, %16-19r, acc0 tandc%22-23w%c %12-15r tbcst%6-7w%c %16-19g, %12-15r tmcr%c %16-19G, %12-15r tmia%c %5-8g, %0-3r, %12-15r tmrc%c %12-15r, %16-19G torc%22-23w%c %12-15r torvsc%22-23w%c %12-15r wldrd %12-15g, %r wldrw %12-15G, %A wldr%L%c %12-15g, %l wor%c %12-15g, %16-19g, %0-3g wstrd %12-15g, %r wstrw %12-15G, %A wstr%L%c %12-15g, %l mvf%c%P%R %12-14f, %0-3f mnf%c%P%R %12-14f, %0-3f abs%c%P%R %12-14f, %0-3f rnd%c%P%R %12-14f, %0-3f sqt%c%P%R %12-14f, %0-3f log%c%P%R %12-14f, %0-3f lgn%c%P%R %12-14f, %0-3f exp%c%P%R %12-14f, %0-3f sin%c%P%R %12-14f, %0-3f cos%c%P%R %12-14f, %0-3f tan%c%P%R %12-14f, %0-3f asn%c%P%R %12-14f, %0-3f acs%c%P%R %12-14f, %0-3f atn%c%P%R %12-14f, %0-3f urd%c%P%R %12-14f, %0-3f nrm%c%P%R %12-14f, %0-3f flt%c%P%R %16-18f, %12-15r fix%c%R %12-15r, %0-2f wfs%c %12-15r rfs%c %12-15r wfc%c %12-15r rfc%c %12-15r cmf%c %16-18f, %0-3f cnf%c %16-18f, %0-3f cmfe%c %16-18f, %0-3f cnfe%c %16-18f, %0-3f stf%c%Q %12-14f, %A ldf%c%Q %12-14f, %A sfm%c %12-14f, %F, %A lfm%c %12-14f, %F, %A vstmdb%c %16-19r%21'!, %B vldmdb%c %16-19r%21'!, %B vstmia%c %16-19r%21'!, %B vldmia%c %16-19r%21'!, %B vstr%c %12-15,22D, %C vldr%c %12-15,22D, %C vdup%c.32 %16-19,7D, %12-15r vdup%c.16 %16-19,7D, %12-15r vdup%c.32 %16-19,7Q, %12-15r vdup%c.16 %16-19,7Q, %12-15r vdup%c.8 %16-19,7D, %12-15r vdup%c.8 %16-19,7Q, %12-15r fmstat%c fmxr%c fpsid, %12-15r fmxr%c fpscr, %12-15r fmxr%c mvfr1, %12-15r fmxr%c mvfr0, %12-15r fmxr%c fpexc, %12-15r fmrx%c %12-15r, fpsid fmrx%c %12-15r, fpscr fmrx%c %12-15r, mvfr1 fmrx%c %12-15r, mvfr0 fmrx%c %12-15r, fpexc fmdlr%c %z2, %12-15r fmrdl%c %12-15r, %z2 fmdhr%c %z2, %12-15r fmrdh%c %12-15r, %z2 fmsr%c %y2, %12-15r fmrs%c %12-15r, %y2 fcmp%7'ezs%c %y1 fcmp%7'ezd%c %z1 fcpys%c %y1, %y0 fabss%c %y1, %y0 fcpyd%c %z1, %z0 fabsd%c %z1, %z0 fnegs%c %y1, %y0 fsqrts%c %y1, %y0 fnegd%c %z1, %z0 fsqrtd%c %z1, %z0 fcvtds%c %z1, %y0 fcvtsd%c %y1, %z0 fuitos%c %y1, %y0 fsitos%c %y1, %y0 fuitod%c %z1, %y0 fsitod%c %z1, %y0 fcmp%7'es%c %y1, %y0 fcmp%7'ed%c %z1, %z0 fto%16?sui%7'zs%c %y1, %y0 fto%16?sui%7'zd%c %y1, %z0 fmrrd%c %12-15r, %16-19r, %z0 fconsts%c %y1, #%0-3,16-19d fconstd%c %z1, #%0-3,16-19d fmsrr%c %y4, %12-15r, %16-19r fmdrr%c %z0, %12-15r, %16-19r fmrrs%c %12-15r, %16-19r, %y4 fmacs%c %y1, %y2, %y0 fnmacs%c %y1, %y2, %y0 fmacd%c %z1, %z2, %z0 fnmacd%c %z1, %z2, %z0 fmscs%c %y1, %y2, %y0 fnmscs%c %y1, %y2, %y0 fmscd%c %z1, %z2, %z0 fnmscd%c %z1, %z2, %z0 fmuls%c %y1, %y2, %y0 fnmuls%c %y1, %y2, %y0 fmuld%c %z1, %z2, %z0 fnmuld%c %z1, %z2, %z0 fadds%c %y1, %y2, %y0 fsubs%c %y1, %y2, %y0 faddd%c %z1, %z2, %z0 fsubd%c %z1, %z2, %z0 fdivs%c %y1, %y2, %y0 fdivd%c %z1, %z2, %z0 fstmdbs%c %16-19r!, %y3 fstmdb%0?xd%c %16-19r!, %z3 fldmdbs%c %16-19r!, %y3 fldmdb%0?xd%c %16-19r!, %z3 fsts%c %y1, %A fstd%c %z1, %A flds%c %y1, %A fldd%c %z1, %A fstmias%c %16-19r%21'!, %y3 fldmias%c %16-19r%21'!, %y3 cfldrs%c mvf%12-15d, %A cfldrd%c mvd%12-15d, %A cfldr32%c mvfx%12-15d, %A cfldr64%c mvdx%12-15d, %A cfstrs%c mvf%12-15d, %A cfstrd%c mvd%12-15d, %A cfstr32%c mvfx%12-15d, %A cfstr64%c mvdx%12-15d, %A cfmvsr%c mvf%16-19d, %12-15r cfmvrs%c %12-15r, mvf%16-19d cfmvdlr%c mvd%16-19d, %12-15r cfmvrdl%c %12-15r, mvd%16-19d cfmvdhr%c mvd%16-19d, %12-15r cfmvrdh%c %12-15r, mvd%16-19d cfmvsc32%c dspsc, mvdx%12-15d cfmv32sc%c mvdx%12-15d, dspsc vcnt%c.8 %12-15,22R, %0-3,5R vmvn%c %12-15,22R, %0-3,5R vswp%c %12-15,22R, %0-3,5R vmov%c.i8 %12-15,22R, %E vmov%c.i64 %12-15,22R, %E vmov%c.f32 %12-15,22R, %E vmov%c.i16 %12-15,22R, %E vmvn%c.i16 %12-15,22R, %E vorr%c.i16 %12-15,22R, %E vbic%c.i16 %12-15,22R, %E vmov%c.i32 %12-15,22R, %E vmvn%c.i32 %12-15,22R, %E vorr%c.i32 %12-15,22R, %E vbic%c.i32 %12-15,22R, %E vld4%c.32 %C vld1%c.%6-7S2 %C vld2%c.%6-7S2 %C vld3%c.%6-7S2 %C vld4%c.%6-7S2 %C v%21?ls%21?dt1%c.%6-7S3 %A v%21?ls%21?dt2%c.%6-7S2 %A v%21?ls%21?dt3%c.%6-7S2 %A v%21?ls%21?dt4%c.%6-7S2 %A v%21?ls%21?dt1%c.%10-11S2 %B v%21?ls%21?dt2%c.%10-11S2 %B v%21?ls%21?dt3%c.%10-11S2 %B v%21?ls%21?dt4%c.%10-11S2 %B nop%c yield%c wfe%c wfi%c sev%c nop%c {%4-7d} cbnz %0-2r, %b%X cbz %0-2r, %b%X it%I%X cpsie %2'a%1'i%0'f%X cpsid %2'a%1'i%0'f%X mov%c %0-2r, %3-5r rev%c %0-2r, %3-5r rev16%c %0-2r, %3-5r revsh%c %0-2r, %3-5r setend %3?ble%X sxth%c %0-2r, %3-5r sxtb%c %0-2r, %3-5r uxth%c %0-2r, %3-5r uxtb%c %0-2r, %3-5r bkpt %0-7x blx%c %3-6r%x nop%c (mov r8, r8) and%C %0-2r, %3-5r eor%C %0-2r, %3-5r lsl%C %0-2r, %3-5r lsr%C %0-2r, %3-5r asr%C %0-2r, %3-5r adc%C %0-2r, %3-5r sbc%C %0-2r, %3-5r ror%C %0-2r, %3-5r tst%c %0-2r, %3-5r neg%C %0-2r, %3-5r cmp%c %0-2r, %3-5r cmn%c %0-2r, %3-5r orr%C %0-2r, %3-5r mul%C %0-2r, %3-5r bic%C %0-2r, %3-5r mvn%C %0-2r, %3-5r add%c sp, #%0-6W sub%c sp, #%0-6W bx%c %S%x add%c %D, %S cmp%c %D, %S mov%c %D, %S push%c %N pop%c %O add%C %0-2r, %3-5r, %6-8r sub%C %0-2r, %3-5r, %6-8r add%C %0-2r, %3-5r, #%6-8d sub%C %0-2r, %3-5r, #%6-8d strh%c %0-2r, [%3-5r, %6-8r] ldrh%c %0-2r, [%3-5r, %6-8r] lsl%C %0-2r, %3-5r, #%6-10d lsr%C %0-2r, %3-5r, %s asr%C %0-2r, %3-5r, %s mov%C %8-10r, #%0-7d cmp%c %8-10r, #%0-7d add%C %8-10r, #%0-7d sub%C %8-10r, #%0-7d str%c %0-2r, [%3-5r, #%6-10W] ldr%c %0-2r, [%3-5r, #%6-10W] str%c %8-10r, [sp, #%0-7W] ldr%c %8-10r, [sp, #%0-7W] add%c %8-10r, sp, #%0-7W stmia%c %8-10r!, %M ldmia%c %8-10r!, %M svc%c %0-7d b%8-11c.n %0-7B%X b%c.n %0-10B%x nop (mov r0,r0) bx%c %0-3r pli %P dmb %U dsb %U isb %U bfc%c %12-15r, %E bfi%c %12-15r, %0-3r, %E strht%c %12-15r, %s ldr%6's%5?hbt%c %12-15r, %s movw%c %12-15r, %V movt%c %12-15r, %V rbit%c %12-15r, %0-3r smc%c %e clrex ldrexb%c %12-15r, [%16-19r] ldrexd%c %12-15r, [%16-19r] ldrexh%c %12-15r, [%16-19r] nop%c {%0-7d} cpsie %8'a%7'i%6'f cpsie %8'a%7'i%6'f,#%0-4d cpsid %8'a%7'i%6'f cpsid %8'a%7'i%6'f,#%0-4d cps #%0-4d ldrex%c r%12-15d, [%16-19r] rev%c %12-15r, %0-3r rev16%c %12-15r, %0-3r revsh%c %12-15r, %0-3r rfe%23?id%24?ba %16-19r%21'! sxth%c %12-15r, %0-3r sxth%c %12-15r, %0-3r, ror #8 sxtb16%c %12-15r, %0-3r sxtb%c %12-15r, %0-3r sxtb%c %12-15r, %0-3r, ror #8 uxth%c %12-15r, %0-3r uxth%c %12-15r, %0-3r, ror #8 uxtb16%c %12-15r, %0-3r uxtb%c %12-15r, %0-3r uxtb%c %12-15r, %0-3r, ror #8 sel%c %12-15r, %16-19r, %0-3r setend %9?ble bxj%c %0-3r blx %B blx%c %0-3r clz%c %12-15r, %0-3r ldrd%c %12-15r, %s strd%c %12-15r, %s pld %a str%6's%5?hb%c %12-15r, %s ldr%6's%5?hb%c %12-15r, %s msr%c %22?SCPSR%C, %o mrs%c %12-15r, %22?SCPSR tst%p%c %16-19r, %o teq%p%c %16-19r, %o cmp%p%c %16-19r, %o cmn%p%c %16-19r, %o mov%20's%c %12-15r, %o mov%20's%c %12-15r, %0-3r lsl%20's%c %12-15r, %q lsr%20's%c %12-15r, %q asr%20's%c %12-15r, %q rrx%20's%c %12-15r, %0-3r ror%20's%c %12-15r, %q mvn%20's%c %12-15r, %o str%22'b%t%c %12-15r, %a ldr%22'b%t%c %12-15r, %a push%c %m stm%c %16-19r%21'!, %m%22'^ pop%c %m ldm%c %16-19r%21'!, %m%22'^ b%24'l%c %b svc%c %0-23x undefined instruction %0-31x lsl lsr asr , rrx , %s #%d , %s %s %% , #%s%d]%s , {%d} {d%d} {d%d-} {d%d-d%d} opcodes d%ld q%ld #%s f%ld -%c%d , %c%d} ], #%s%d [%s], %c%s , lsl #%d [%s, %c%s INVALID [pc , #%d] ], #%d ], %s %sd%d d%d-d%d }, [%s , :%d %sd%d[%d] %sd%d[] d%d[]-d%d[] , : #%ld ; 0x%.4lx #%ld ; 0x%.2lx #%.7g ; 0x%.8lx #%ld ; 0x%.8lx {d%d- #0x%.8lx%.8lx [pc, #%d] ; ], %s%s #%d ; 0x%x sy un unst ; IMB ; IMBRange %01lx #%lu, #%lu (invalid: %lu:%lu) #%lu ; 0x%lx %s ; unpredictable #%ld CONTROL IAPSR EAPSR IPSR IEPSR MSP PSP PRIMASK BASEPRI BASEPRI_MASK FAULTMASK #%u ; 0x%x , lsl #%u , lsr #%u , asr #%u , ror #%u , ] ]! , #%c%u ], {%u} sb #%u, #%u %cPSR_ %cPSR .byte 0x%02lx .short 0x%04lx .word 0x%08lx reg-names- no-force-thumb reg-names-%s %*c%s Select register names used by GCC Select register names used in ARM's ISA documentation Select register names used in the APCS Select register names used in the ATPCS Select special register names used in the ATPCS tbh%c [%16-19r, %0-3r, lsl #1]%x ldrex%4?hb%c %12-15r, [%16-19r] strex%c %8-11r, %12-15r, [%16-19r] ldrexd%c %12-15r, %8-11r, [%16-19r] sadd8%c %8-11r, %16-19r, %0-3r qadd8%c %8-11r, %16-19r, %0-3r shadd8%c %8-11r, %16-19r, %0-3r uadd8%c %8-11r, %16-19r, %0-3r uqadd8%c %8-11r, %16-19r, %0-3r uhadd8%c %8-11r, %16-19r, %0-3r qdadd%c %8-11r, %0-3r, %16-19r qdsub%c %8-11r, %0-3r, %16-19r sadd16%c %8-11r, %16-19r, %0-3r qadd16%c %8-11r, %16-19r, %0-3r shadd16%c %8-11r, %16-19r, %0-3r uadd16%c %8-11r, %16-19r, %0-3r uqadd16%c %8-11r, %16-19r, %0-3r uhadd16%c %8-11r, %16-19r, %0-3r saddsubx%c %8-11r, %16-19r, %0-3r qaddsubx%c %8-11r, %16-19r, %0-3r shaddsubx%c %8-11r, %16-19r, %0-3r uaddsubx%c %8-11r, %16-19r, %0-3r uqaddsubx%c %8-11r, %16-19r, %0-3r uhaddsubx%c %8-11r, %16-19r, %0-3r ssub8%c %8-11r, %16-19r, %0-3r qsub8%c %8-11r, %16-19r, %0-3r shsub8%c %8-11r, %16-19r, %0-3r usub8%c %8-11r, %16-19r, %0-3r uqsub8%c %8-11r, %16-19r, %0-3r uhsub8%c %8-11r, %16-19r, %0-3r ssub16%c %8-11r, %16-19r, %0-3r qsub16%c %8-11r, %16-19r, %0-3r shsub16%c %8-11r, %16-19r, %0-3r usub16%c %8-11r, %16-19r, %0-3r uqsub16%c %8-11r, %16-19r, %0-3r uhsub16%c %8-11r, %16-19r, %0-3r ssubaddx%c %8-11r, %16-19r, %0-3r qsubaddx%c %8-11r, %16-19r, %0-3r shsubaddx%c %8-11r, %16-19r, %0-3r usubaddx%c %8-11r, %16-19r, %0-3r uqsubaddx%c %8-11r, %16-19r, %0-3r uhsubaddx%c %8-11r, %16-19r, %0-3r mul%c.w %8-11r, %16-19r, %0-3r usad8%c %8-11r, %16-19r, %0-3r lsl%20's%c.w %8-11r, %16-19r, %0-3r lsr%20's%c.w %8-11r, %16-19r, %0-3r asr%20's%c.w %8-11r, %16-19r, %0-3r ror%20's%c.w %8-11r, %16-19r, %0-3r strex%4?hb%c %0-3r, %12-15r, [%16-19r] ssat16%c %8-11r, #%0-4d, %16-19r usat16%c %8-11r, #%0-4d, %16-19r smuad%4'x%c %8-11r, %16-19r, %0-3r smulw%4?tb%c %8-11r, %16-19r, %0-3r smusd%4'x%c %8-11r, %16-19r, %0-3r smmul%4'r%c %8-11r, %16-19r, %0-3r sxtah%c %8-11r, %16-19r, %0-3r%R uxtah%c %8-11r, %16-19r, %0-3r%R sxtab16%c %8-11r, %16-19r, %0-3r%R uxtab16%c %8-11r, %16-19r, %0-3r%R sxtab%c %8-11r, %16-19r, %0-3r%R uxtab%c %8-11r, %16-19r, %0-3r%R smul%5?tb%4?tb%c %8-11r, %16-19r, %0-3r strexd%c %0-3r, %12-15r, %8-11r, [%16-19r] mla%c %8-11r, %16-19r, %0-3r, %12-15r mls%c %8-11r, %16-19r, %0-3r, %12-15r usada8%c %8-11r, %16-19r, %0-3r, %12-15r smull%c %12-15r, %8-11r, %16-19r, %0-3r umull%c %12-15r, %8-11r, %16-19r, %0-3r smlal%c %12-15r, %8-11r, %16-19r, %0-3r umlal%c %12-15r, %8-11r, %16-19r, %0-3r umaal%c %12-15r, %8-11r, %16-19r, %0-3r ldrex%c %12-15r, [%16-19r, #%0-7W] smlad%4'x%c %8-11r, %16-19r, %0-3r, %12-15r smlaw%4?tb%c %8-11r, %16-19r, %0-3r, %12-15r smlsd%4'x%c %8-11r, %16-19r, %0-3r, %12-15r smmla%4'r%c %8-11r, %16-19r, %0-3r, %12-15r smmls%4'r%c %8-11r, %16-19r, %0-3r, %12-15r smlald%4'x%c %12-15r, %8-11r, %16-19r, %0-3r smlsld%4'x%c %12-15r, %8-11r, %16-19r, %0-3r smla%5?tb%4?tb%c %8-11r, %16-19r, %0-3r, %12-15r smlal%5?tb%4?tb%c %12-15r, %8-11r, %16-19r, %0-3r ssat%c %8-11r, #%0-4d, %16-19r%s usat%c %8-11r, #%0-4d, %16-19r%s and%20's%c.w %8-11r, %16-19r, %S bic%20's%c.w %8-11r, %16-19r, %S orr%20's%c.w %8-11r, %16-19r, %S orn%20's%c %8-11r, %16-19r, %S eor%20's%c.w %8-11r, %16-19r, %S add%20's%c.w %8-11r, %16-19r, %S adc%20's%c.w %8-11r, %16-19r, %S sbc%20's%c.w %8-11r, %16-19r, %S sub%20's%c.w %8-11r, %16-19r, %S rsb%20's%c %8-11r, %16-19r, %S strex%c %8-11r, %12-15r, [%16-19r, #%0-7W] and%20's%c.w %8-11r, %16-19r, %M bic%20's%c.w %8-11r, %16-19r, %M orr%20's%c.w %8-11r, %16-19r, %M orn%20's%c %8-11r, %16-19r, %M eor%20's%c.w %8-11r, %16-19r, %M add%20's%c.w %8-11r, %16-19r, %M adc%20's%c.w %8-11r, %16-19r, %M sbc%20's%c.w %8-11r, %16-19r, %M sub%20's%c.w %8-11r, %16-19r, %M rsb%20's%c %8-11r, %16-19r, %M strd%c %12-15r, %8-11r, [%16-19r] ldrd%c %12-15r, %8-11r, [%16-19r] strd%c %12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'! ldrd%c %12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'! strd%c %12-15r, %8-11r, [%16-19r], #%23`-%0-7W ldrd%c %12-15r, %8-11r, [%16-19r], #%23`-%0-7W mia%17'T%17`B%16'T%16`B%c acc0, %0-3r, %12-15r textrc%22-23w%c %12-15r, #%0-2d textrm%3?su%22-23w%c %12-15r, %16-19g, #%0-2d tinsr%6-7w%c %16-19g, %12-15r, #%0-2d tmcrr%c %0-3g, %12-15r, %16-19r tmia%17?tb%16?tb%c %5-8g, %0-3r, %12-15r tmiaph%c %5-8g, %0-3r, %12-15r tmovmsk%22-23w%c %12-15r, %16-19g tmrrc%c %12-15r, %16-19r, %0-3g wabs%22-23w%c %12-15g, %16-19g wacc%22-23w%c %12-15g, %16-19g wadd%20-23w%c %12-15g, %16-19g, %0-3g waddbhus%22?ml%c %12-15g, %16-19g, %0-3g waddsubhx%c %12-15g, %16-19g, %0-3g waligni%c %12-15g, %16-19g, %0-3g, #%20-22d walignr%20-21d%c %12-15g, %16-19g, %0-3g wand%20'n%c %12-15g, %16-19g, %0-3g wavg2%22?hb%20'r%c %12-15g, %16-19g, %0-3g wavg4%20'r%c %12-15g, %16-19g, %0-3g wcmpeq%22-23w%c %12-15g, %16-19g, %0-3g wcmpgt%21?su%22-23w%c %12-15g, %16-19g, %0-3g wmac%21?su%20'z%c %12-15g, %16-19g, %0-3g wmadd%21?su%20'x%c %12-15g, %16-19g, %0-3g wmadd%21?sun%c %12-15g, %16-19g, %0-3g wmax%21?su%22-23w%c %12-15g, %16-19g, %0-3g wmerge%c %12-15g, %16-19g, %0-3g, #%21-23d wmia%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g wmiaw%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g wmin%21?su%22-23w%c %12-15g, %16-19g, %0-3g wmul%21?su%20?ml%23'r%c %12-15g, %16-19g, %0-3g wmul%21?sumr%c %12-15g, %16-19g, %0-3g wmulwsm%20`r%c %12-15g, %16-19g, %0-3g wmulwum%20`r%c %12-15g, %16-19g, %0-3g wmulwl%c %12-15g, %16-19g, %0-3g wqmia%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g wqmulm%21'r%c %12-15g, %16-19g, %0-3g wqmulwm%21'r%c %12-15g, %16-19g, %0-3g wpack%20-23w%c %12-15g, %16-19g, %0-3g wror%22-23w %12-15g, %16-19g, #%i wror%22-23w%c %12-15g, %16-19g, %0-3g wror%22-23wg%c %12-15g, %16-19g, %0-3G wsad%22?hb%20'z%c %12-15g, %16-19g, %0-3g wshufh%c %12-15g, %16-19g, #%Z wsll%22-23w %12-15g, %16-19g, #%i wsll%22-23w%8'g%c %12-15g, %16-19g, %0-3g wsll%22-23w%8'g%c %12-15g, %16-19g, %0-3G wsra%22-23w %12-15g, %16-19g, #%i wsra%22-23w%8'g%c %12-15g, %16-19g, %0-3g wsra%22-23w%8'g%c %12-15g, %16-19g, %0-3G wsrl%22-23w %12-15g, %16-19g, #%i wsrl%22-23w%8'g%c %12-15g, %16-19g, %0-3g wsrl%22-23w%8'g%c %12-15g, %16-19g, %0-3G wsub%20-23w%c %12-15g, %16-19g, %0-3g wsubaddhx%c %12-15g, %16-19g, %0-3g wabsdiff%22-23w%c %12-15g, %16-19g, %0-3g wunpckeh%21?sub%c %12-15g, %16-19g wunpckeh%21?suh%c %12-15g, %16-19g wunpckeh%21?suw%c %12-15g, %16-19g wunpckel%21?su%22-23w%c %12-15g, %16-19g wunpckih%22-23w%c %12-15g, %16-19g, %0-3g wunpckil%22-23w%c %12-15g, %16-19g, %0-3g wxor%c %12-15g, %16-19g, %0-3g adf%c%P%R %12-14f, %16-18f, %0-3f muf%c%P%R %12-14f, %16-18f, %0-3f suf%c%P%R %12-14f, %16-18f, %0-3f rsf%c%P%R %12-14f, %16-18f, %0-3f dvf%c%P%R %12-14f, %16-18f, %0-3f rdf%c%P%R %12-14f, %16-18f, %0-3f pow%c%P%R %12-14f, %16-18f, %0-3f rpw%c%P%R %12-14f, %16-18f, %0-3f rmf%c%P%R %12-14f, %16-18f, %0-3f fml%c%P%R %12-14f, %16-18f, %0-3f fdv%c%P%R %12-14f, %16-18f, %0-3f frd%c%P%R %12-14f, %16-18f, %0-3f pol%c%P%R %12-14f, %16-18f, %0-3f vmov%c %0-3,5D, %12-15r, %16-19r vmov%c %12-15r, %16-19r, %0-3,5D vmov%c.32 %16-19,7D[%21d], %12-15r vmov%c.32 %12-15r, %16-19,7D[%21d] vmov%c.16 %16-19,7D[%6,21d], %12-15r vmov%c.%23?us16 %12-15r, %16-19,7D[%6,21d] vmov%c.8 %16-19,7D[%5,6,21d], %12-15r vmov%c.%23?us8 %12-15r, %16-19,7D[%5,6,21d] fmxr%c fpinst, %12-15r @ Impl def fmxr%c fpinst2, %12-15r @ Impl def fmrx%c %12-15r, fpinst @ Impl def fmrx%c %12-15r, fpinst2 @ Impl def fmxr%c , %12-15r fmrx%c %12-15r, f%16?us%7?lhtos%c %y1, #%5,0-3k f%16?us%7?lhtod%c %z1, #%5,0-3k fto%16?us%7?lhs%c %y1, #%5,0-3k fto%16?us%7?lhd%c %z1, #%5,0-3k fstmia%0?xd%c %16-19r%21'!, %z3 fldmia%0?xd%c %16-19r%21'!, %z3 cfmv64lr%c mvdx%16-19d, %12-15r cfmvr64l%c %12-15r, mvdx%16-19d cfmv64hr%c mvdx%16-19d, %12-15r cfmvr64h%c %12-15r, mvdx%16-19d cfmval32%c mvax%12-15d, mvfx%16-19d cfmv32al%c mvfx%12-15d, mvax%16-19d cfmvam32%c mvax%12-15d, mvfx%16-19d cfmv32am%c mvfx%12-15d, mvax%16-19d cfmvah32%c mvax%12-15d, mvfx%16-19d cfmv32ah%c mvfx%12-15d, mvax%16-19d cfmva32%c mvax%12-15d, mvfx%16-19d cfmv32a%c mvfx%12-15d, mvax%16-19d cfmva64%c mvax%12-15d, mvdx%16-19d cfmv64a%c mvdx%12-15d, mvax%16-19d cfcpys%c mvf%12-15d, mvf%16-19d cfcpyd%c mvd%12-15d, mvd%16-19d cfcvtsd%c mvd%12-15d, mvf%16-19d cfcvtds%c mvf%12-15d, mvd%16-19d cfcvt32s%c mvf%12-15d, mvfx%16-19d cfcvt32d%c mvd%12-15d, mvfx%16-19d cfcvt64s%c mvf%12-15d, mvdx%16-19d cfcvt64d%c mvd%12-15d, mvdx%16-19d cfcvts32%c mvfx%12-15d, mvf%16-19d cfcvtd32%c mvfx%12-15d, mvd%16-19d cftruncs32%c mvfx%12-15d, mvf%16-19d cftruncd32%c mvfx%12-15d, mvd%16-19d cfrshl32%c mvfx%16-19d, mvfx%0-3d, %12-15r cfrshl64%c mvdx%16-19d, mvdx%0-3d, %12-15r cfsh32%c mvfx%12-15d, mvfx%16-19d, #%I cfsh64%c mvdx%12-15d, mvdx%16-19d, #%I cfcmps%c %12-15r, mvf%16-19d, mvf%0-3d cfcmpd%c %12-15r, mvd%16-19d, mvd%0-3d cfcmp32%c %12-15r, mvfx%16-19d, mvfx%0-3d cfcmp64%c %12-15r, mvdx%16-19d, mvdx%0-3d cfabss%c mvf%12-15d, mvf%16-19d cfabsd%c mvd%12-15d, mvd%16-19d cfnegs%c mvf%12-15d, mvf%16-19d cfnegd%c mvd%12-15d, mvd%16-19d cfadds%c mvf%12-15d, mvf%16-19d, mvf%0-3d cfaddd%c mvd%12-15d, mvd%16-19d, mvd%0-3d cfsubs%c mvf%12-15d, mvf%16-19d, mvf%0-3d cfsubd%c mvd%12-15d, mvd%16-19d, mvd%0-3d cfmuls%c mvf%12-15d, mvf%16-19d, mvf%0-3d cfmuld%c mvd%12-15d, mvd%16-19d, mvd%0-3d cfabs32%c mvfx%12-15d, mvfx%16-19d cfabs64%c mvdx%12-15d, mvdx%16-19d cfneg32%c mvfx%12-15d, mvfx%16-19d cfneg64%c mvdx%12-15d, mvdx%16-19d cfadd32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d cfadd64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d cfsub32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d cfsub64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d cfmul32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d cfmul64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d cfmac32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d cfmsc32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d cfmadd32%c mvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d cfmsub32%c mvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d cfmadda32%c mvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d cfmsuba32%c mvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d mcrr%c %8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d mrrc%c %8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d} mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d} mcr%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d} stc%22'l%c %8-11d, cr%12-15d, %A ldc%22'l%c %8-11d, cr%12-15d, %A mrrc2%c %8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d mcrr2%c %8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d ldc2%22'l%c %8-11d, cr%12-15d, %A stc2%22'l%c %8-11d, cr%12-15d, %A cdp2%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d} mcr2%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d} mrc2%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d} vext%c.8 %12-15,22R, %16-19,7R, %0-3,5R, #%8-11d vdup%c.32 %12-15,22R, %0-3,5D[%19d] vdup%c.16 %12-15,22R, %0-3,5D[%18-19d] vdup%c.8 %12-15,22R, %0-3,5D[%17-19d] vtbl%c.8 %12-15,22D, %F, %0-3,5D vtbx%c.8 %12-15,22D, %F, %0-3,5D vmovl%c.%24?us8 %12-15,22Q, %0-3,5D vmovl%c.%24?us16 %12-15,22Q, %0-3,5D vmovl%c.%24?us32 %12-15,22Q, %0-3,5D vmovn%c.i%18-19T2 %12-15,22D, %0-3,5Q vqmovun%c.s%18-19T2 %12-15,22D, %0-3,5Q vqmovn%c.s%18-19T2 %12-15,22D, %0-3,5Q vqmovn%c.u%18-19T2 %12-15,22D, %0-3,5Q vshll%c.i%18-19S2 %12-15,22Q, %0-3,5D, #%18-19S2 vrecpe%c.%8?fu%18-19S2 %12-15,22R, %0-3,5R vrsqrte%c.%8?fu%18-19S2 %12-15,22R, %0-3,5R vrev64%c.%18-19S2 %12-15,22R, %0-3,5R vrev32%c.%18-19S2 %12-15,22R, %0-3,5R vrev16%c.%18-19S2 %12-15,22R, %0-3,5R vcls%c.s%18-19S2 %12-15,22R, %0-3,5R vclz%c.i%18-19S2 %12-15,22R, %0-3,5R vqabs%c.s%18-19S2 %12-15,22R, %0-3,5R vqneg%c.s%18-19S2 %12-15,22R, %0-3,5R vtrn%c.%18-19S2 %12-15,22R, %0-3,5R vuzp%c.%18-19S2 %12-15,22R, %0-3,5R vzip%c.%18-19S2 %12-15,22R, %0-3,5R vcgt%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0 vcge%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0 vceq%c.%10?fi%18-19S2 %12-15,22R, %0-3,5R, #0 vcle%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0 vclt%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0 vabs%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R vneg%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R vpaddl%c.%7?us%18-19S2 %12-15,22R, %0-3,5R vpadal%c.%7?us%18-19S2 %12-15,22R, %0-3,5R vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa %12-15,22R, %0-3,5R vand%c %12-15,22R, %16-19,7R, %0-3,5R vbic%c %12-15,22R, %16-19,7R, %0-3,5R vorr%c %12-15,22R, %16-19,7R, %0-3,5R vorn%c %12-15,22R, %16-19,7R, %0-3,5R veor%c %12-15,22R, %16-19,7R, %0-3,5R vbsl%c %12-15,22R, %16-19,7R, %0-3,5R vbit%c %12-15,22R, %16-19,7R, %0-3,5R vbif%c %12-15,22R, %16-19,7R, %0-3,5R vadd%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vmla%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vceq%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vmax%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vrecps%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vsub%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vmls%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vmin%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vrsqrts%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vpadd%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vmul%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vcge%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vacge%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vpmax%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vabd%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vcgt%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vacgt%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vpmin%c.f%20U0 %12-15,22R, %16-19,7R, %0-3,5R vadd%c.i%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R vtst%c.%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vmla%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vqdmulh%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R vpadd%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vsub%c.i%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R vceq%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vmls%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vqrdmulh%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R vhadd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vqadd%c.%24?us%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R vrhadd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vhsub%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vqsub%c.%24?us%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R vcgt%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vcge%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R vqshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R vrshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R vqrshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R vmax%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vmin%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vabd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vaba%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vmul%c.%24?pi%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vpmax%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vpmin%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R vshrn%c.i16 %12-15,22D, %0-3,5Q, #%16-18e vrshrn%c.i16 %12-15,22D, %0-3,5Q, #%16-18e vqshrun%c.s16 %12-15,22D, %0-3,5Q, #%16-18e vqrshrun%c.s16 %12-15,22D, %0-3,5Q, #%16-18e vqshrn%c.%24?us16 %12-15,22D, %0-3,5Q, #%16-18e vqrshrn%c.%24?us16 %12-15,22D, %0-3,5Q, #%16-18e vshll%c.%24?us8 %12-15,22D, %0-3,5Q, #%16-18d vshrn%c.i32 %12-15,22D, %0-3,5Q, #%16-19e vrshrn%c.i32 %12-15,22D, %0-3,5Q, #%16-19e vshl%c.%24?us8 %12-15,22R, %0-3,5R, #%16-18d vsri%c.8 %12-15,22R, %0-3,5R, #%16-18e vsli%c.8 %12-15,22R, %0-3,5R, #%16-18d vqshlu%c.s8 %12-15,22R, %0-3,5R, #%16-18d vqshrun%c.s32 %12-15,22D, %0-3,5Q, #%16-19e vqrshrun%c.s32 %12-15,22D, %0-3,5Q, #%16-19e vqshrn%c.%24?us32 %12-15,22D, %0-3,5Q, #%16-19e vqrshrn%c.%24?us32 %12-15,22D, %0-3,5Q, #%16-19e vshll%c.%24?us16 %12-15,22D, %0-3,5Q, #%16-19d vshr%c.%24?us8 %12-15,22R, %0-3,5R, #%16-18e vsra%c.%24?us8 %12-15,22R, %0-3,5R, #%16-18e vrshr%c.%24?us8 %12-15,22R, %0-3,5R, #%16-18e vrsra%c.%24?us8 %12-15,22R, %0-3,5R, #%16-18e vqshl%c.%24?us8 %12-15,22R, %0-3,5R, #%16-18d vshrn%c.i64 %12-15,22D, %0-3,5Q, #%16-20e vrshrn%c.i64 %12-15,22D, %0-3,5Q, #%16-20e vshl%c.%24?us16 %12-15,22R, %0-3,5R, #%16-19d vsri%c.16 %12-15,22R, %0-3,5R, #%16-19e vsli%c.16 %12-15,22R, %0-3,5R, #%16-19d vqshlu%c.s16 %12-15,22R, %0-3,5R, #%16-19d vshll%c.%24?us32 %12-15,22D, %0-3,5Q, #%16-20d vshr%c.%24?us16 %12-15,22R, %0-3,5R, #%16-19e vsra%c.%24?us16 %12-15,22R, %0-3,5R, #%16-19e vrshr%c.%24?us16 %12-15,22R, %0-3,5R, #%16-19e vrsra%c.%24?us16 %12-15,22R, %0-3,5R, #%16-19e vqshl%c.%24?us16 %12-15,22R, %0-3,5R, #%16-19d vqshrun%c.s64 %12-15,22D, %0-3,5Q, #%16-20e vqrshrun%c.s64 %12-15,22D, %0-3,5Q, #%16-20e vqshrn%c.%24?us64 %12-15,22D, %0-3,5Q, #%16-20e vqrshrn%c.%24?us64 %12-15,22D, %0-3,5Q, #%16-20e vshl%c.%24?us32 %12-15,22R, %0-3,5R, #%16-20d vsri%c.32 %12-15,22R, %0-3,5R, #%16-20e vsli%c.32 %12-15,22R, %0-3,5R, #%16-20d vqshlu%c.s32 %12-15,22R, %0-3,5R, #%16-20d vshr%c.%24?us32 %12-15,22R, %0-3,5R, #%16-20e vsra%c.%24?us32 %12-15,22R, %0-3,5R, #%16-20e vrshr%c.%24?us32 %12-15,22R, %0-3,5R, #%16-20e vrsra%c.%24?us32 %12-15,22R, %0-3,5R, #%16-20e vqshl%c.%24?us32 %12-15,22R, %0-3,5R, #%16-20d vshl%c.%24?us64 %12-15,22R, %0-3,5R, #%16-21d vsri%c.64 %12-15,22R, %0-3,5R, #%16-21e vsli%c.64 %12-15,22R, %0-3,5R, #%16-21d vqshlu%c.s64 %12-15,22R, %0-3,5R, #%16-21d vshr%c.%24?us64 %12-15,22R, %0-3,5R, #%16-21e vsra%c.%24?us64 %12-15,22R, %0-3,5R, #%16-21e vrshr%c.%24?us64 %12-15,22R, %0-3,5R, #%16-21e vrsra%c.%24?us64 %12-15,22R, %0-3,5R, #%16-21e vqshl%c.%24?us64 %12-15,22R, %0-3,5R, #%16-21d vcvt%c.%24,8?usff32.%24,8?ffus32 %12-15,22R, %0-3,5R, #%16-20e vmull%c.p%20S0 %12-15,22Q, %16-19,7D, %0-3,5D vaddhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q vsubhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q vqdmlal%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D vqdmlsl%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D vqdmull%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D vraddhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q vrsubhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q vaddl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D vaddw%c.%24?us%20-21S2 %12-15,22Q, %16-19,7Q, %0-3,5D vsubl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D vsubw%c.%24?us%20-21S2 %12-15,22Q, %16-19,7Q, %0-3,5D vabal%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D vabdl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D vmlal%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D vmlsl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D vmull%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D vmla%c.i%20-21S6 %12-15,22D, %16-19,7D, %D vmla%c.f%20-21Sa %12-15,22D, %16-19,7D, %D vqdmlal%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D vmls%c.i%20-21S6 %12-15,22D, %16-19,7D, %D vmls%c.f%20-21S6 %12-15,22D, %16-19,7D, %D vqdmlsl%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D vmul%c.i%20-21S6 %12-15,22D, %16-19,7D, %D vmul%c.f%20-21Sa %12-15,22D, %16-19,7D, %D vqdmull%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D vqdmulh%c.s%20-21S6 %12-15,22D, %16-19,7D, %D vqrdmulh%c.s%20-21S6 %12-15,22D, %16-19,7D, %D vmla%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D vmla%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D vmls%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D vmls%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D vmul%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D vmul%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D vqdmulh%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D vqrdmulh%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D vmlal%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D vmlsl%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D vmull%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D ldrs%11?hb%c %0-2r, [%3-5r, %6-8r] str%10'b%c %0-2r, [%3-5r, %6-8r] ldr%10'b%c %0-2r, [%3-5r, %6-8r] ldr%c %8-10r, [pc, #%0-7W] (%0-7a) strb%c %0-2r, [%3-5r, #%6-10d] ldrb%c %0-2r, [%3-5r, #%6-10d] strh%c %0-2r, [%3-5r, #%6-10H] ldrh%c %0-2r, [%3-5r, #%6-10H] add%c %8-10r, pc, #%0-7W (adr %8-10r, %0-7a) mul%20's%c %16-19r, %0-3r, %8-11r mla%20's%c %16-19r, %0-3r, %8-11r, %12-15r swp%22'b%c %12-15r, %0-3r, [%16-19r] %22?sumull%20's%c %12-15r, %16-19r, %0-3r, %8-11r %22?sumlal%20's%c %12-15r, %16-19r, %0-3r, %8-11r mls%c %16-19r, %0-3r, %8-11r, %12-15r %22?usbfx%c %12-15r, %0-3r, #%7-11d, #%16-20W strexb%c %12-15r, %0-3r, [%16-19r] strexd%c %12-15r, %0-3r, [%16-19r] strexh%c %12-15r, %0-3r, [%16-19r] pkhbt%c %12-15r, %16-19r, %0-3r pkhbt%c %12-15r, %16-19r, %0-3r, lsl #%7-11d pkhtb%c %12-15r, %16-19r, %0-3r, asr #32 pkhtb%c %12-15r, %16-19r, %0-3r, asr #%7-11d qadd16%c %12-15r, %16-19r, %0-3r qadd8%c %12-15r, %16-19r, %0-3r qaddsubx%c %12-15r, %16-19r, %0-3r qsub16%c %12-15r, %16-19r, %0-3r qsub8%c %12-15r, %16-19r, %0-3r qsubaddx%c %12-15r, %16-19r, %0-3r sadd16%c %12-15r, %16-19r, %0-3r sadd8%c %12-15r, %16-19r, %0-3r saddaddx%c %12-15r, %16-19r, %0-3r shadd16%c %12-15r, %16-19r, %0-3r shadd8%c %12-15r, %16-19r, %0-3r shaddsubx%c %12-15r, %16-19r, %0-3r shsub16%c %12-15r, %16-19r, %0-3r shsub8%c %12-15r, %16-19r, %0-3r shsubaddx%c %12-15r, %16-19r, %0-3r ssub16%c %12-15r, %16-19r, %0-3r ssub8%c %12-15r, %16-19r, %0-3r ssubaddx%c %12-15r, %16-19r, %0-3r uadd16%c %12-15r, %16-19r, %0-3r uadd8%c %12-15r, %16-19r, %0-3r uaddsubx%c %12-15r, %16-19r, %0-3r uhadd16%c %12-15r, %16-19r, %0-3r uhadd8%c %12-15r, %16-19r, %0-3r uhaddsubx%c %12-15r, %16-19r, %0-3r uhsub16%c %12-15r, %16-19r, %0-3r uhsub8%c %12-15r, %16-19r, %0-3r uhsubaddx%c %12-15r, %16-19r, %0-3r uqadd16%c %12-15r, %16-19r, %0-3r uqadd8%c %12-15r, %16-19r, %0-3r uqaddsubx%c %12-15r, %16-19r, %0-3r uqsub16%c %12-15r, %16-19r, %0-3r uqsub8%c %12-15r, %16-19r, %0-3r uqsubaddx%c %12-15r, %16-19r, %0-3r usub16%c %12-15r, %16-19r, %0-3r usub8%c %12-15r, %16-19r, %0-3r usubaddx%c %12-15r, %16-19r, %0-3r sxth%c %12-15r, %0-3r, ror #16 sxth%c %12-15r, %0-3r, ror #24 sxtb16%c %12-15r, %0-3r, ror #8 sxtb16%c %12-15r, %0-3r, ror #16 sxtb16%c %12-15r, %0-3r, ror #24 sxtb%c %12-15r, %0-3r, ror #16 sxtb%c %12-15r, %0-3r, ror #24 uxth%c %12-15r, %0-3r, ror #16 uxth%c %12-15r, %0-3r, ror #24 uxtb16%c %12-15r, %0-3r, ror #8 uxtb16%c %12-15r, %0-3r, ror #16 uxtb16%c %12-15r, %0-3r, ror #24 uxtb%c %12-15r, %0-3r, ror #16 uxtb%c %12-15r, %0-3r, ror #24 sxtah%c %12-15r, %16-19r, %0-3r sxtah%c %12-15r, %16-19r, %0-3r, ror #8 sxtah%c %12-15r, %16-19r, %0-3r, ror #16 sxtah%c %12-15r, %16-19r, %0-3r, ror #24 sxtab16%c %12-15r, %16-19r, %0-3r sxtab16%c %12-15r, %16-19r, %0-3r, ror #8 sxtab16%c %12-15r, %16-19r, %0-3r, ror #16 sxtab16%c %12-15r, %16-19r, %0-3r, ror #24 sxtab%c %12-15r, %16-19r, %0-3r sxtab%c %12-15r, %16-19r, %0-3r, ror #8 sxtab%c %12-15r, %16-19r, %0-3r, ror #16 sxtab%c %12-15r, %16-19r, %0-3r, ror #24 uxtah%c %12-15r, %16-19r, %0-3r uxtah%c %12-15r, %16-19r, %0-3r, ror #8 uxtah%c %12-15r, %16-19r, %0-3r, ror #16 uxtah%c %12-15r, %16-19r, %0-3r, ror #24 uxtab16%c %12-15r, %16-19r, %0-3r uxtab16%c %12-15r, %16-19r, %0-3r, ror #8 uxtab16%c %12-15r, %16-19r, %0-3r, ror #16 uxtab16%c %12-15r, %16-19r, %0-3r, ROR #24 uxtab%c %12-15r, %16-19r, %0-3r uxtab%c %12-15r, %16-19r, %0-3r, ror #8 uxtab%c %12-15r, %16-19r, %0-3r, ror #16 uxtab%c %12-15r, %16-19r, %0-3r, ror #24 smuad%5'x%c %16-19r, %0-3r, %8-11r smusd%5'x%c %16-19r, %0-3r, %8-11r smlad%5'x%c %16-19r, %0-3r, %8-11r, %12-15r smlald%5'x%c %12-15r, %16-19r, %0-3r, %8-11r smlsd%5'x%c %16-19r, %0-3r, %8-11r, %12-15r smlsld%5'x%c %12-15r, %16-19r, %0-3r, %8-11r smmul%5'r%c %16-19r, %0-3r, %8-11r smmla%5'r%c %16-19r, %0-3r, %8-11r, %12-15r smmls%5'r%c %16-19r, %0-3r, %8-11r, %12-15r srs%23?id%24?ba %16-19r%21'!, #%0-4d ssat%c %12-15r, #%16-20W, %0-3r ssat%c %12-15r, #%16-20W, %0-3r, lsl #%7-11d ssat%c %12-15r, #%16-20W, %0-3r, asr #%7-11d ssat16%c %12-15r, #%16-19W, %0-3r strex%c %12-15r, %0-3r, [%16-19r] umaal%c %12-15r, %16-19r, %0-3r, %8-11r usad8%c %16-19r, %0-3r, %8-11r usada8%c %16-19r, %0-3r, %8-11r, %12-15r usat%c %12-15r, #%16-20d, %0-3r usat%c %12-15r, #%16-20d, %0-3r, lsl #%7-11d usat%c %12-15r, #%16-20d, %0-3r, asr #%7-11d usat16%c %12-15r, #%16-19d, %0-3r bkpt 0x%16-19X%12-15X%8-11X%0-3X smlabb%c %16-19r, %0-3r, %8-11r, %12-15r smlatb%c %16-19r, %0-3r, %8-11r, %12-15r smlabt%c %16-19r, %0-3r, %8-11r, %12-15r smlatt%c %16-19r, %0-3r, %8-11r, %12-15r smlawb%c %16-19r, %0-3r, %8-11r, %12-15r smlawt%c %16-19r, %0-3r, %8-11r, %12-15r smlalbb%c %12-15r, %16-19r, %0-3r, %8-11r smlaltb%c %12-15r, %16-19r, %0-3r, %8-11r smlalbt%c %12-15r, %16-19r, %0-3r, %8-11r smlaltt%c %12-15r, %16-19r, %0-3r, %8-11r smulbb%c %16-19r, %0-3r, %8-11r smultb%c %16-19r, %0-3r, %8-11r smulbt%c %16-19r, %0-3r, %8-11r smultt%c %16-19r, %0-3r, %8-11r smulwb%c %16-19r, %0-3r, %8-11r smulwt%c %16-19r, %0-3r, %8-11r qadd%c %12-15r, %0-3r, %16-19r qdadd%c %12-15r, %0-3r, %16-19r qsub%c %12-15r, %0-3r, %16-19r qdsub%c %12-15r, %0-3r, %16-19r and%20's%c %12-15r, %16-19r, %o eor%20's%c %12-15r, %16-19r, %o sub%20's%c %12-15r, %16-19r, %o rsb%20's%c %12-15r, %16-19r, %o add%20's%c %12-15r, %16-19r, %o adc%20's%c %12-15r, %16-19r, %o sbc%20's%c %12-15r, %16-19r, %o rsc%20's%c %12-15r, %16-19r, %o orr%20's%c %12-15r, %16-19r, %o bic%20's%c %12-15r, %16-19r, %o push%c {%12-15r} ; (str%c %12-15r, %a) pop%c {%12-15r} ; (ldr%c %12-15r, %a) stm%23?id%24?ba%c %16-19r%21'!, %m%22'^ ldm%23?id%24?ba%c %16-19r%21'!, %m%22'^ ; unpredictable branch in IT block Unrecognised register name set: %s Unrecognised disassembler option: %s The following ARM specific disassembler options are supported for use with the -M switch: force-thumb Assume all insns are Thumb insns no-force-thumb Examine preceeding label to determine an insn's type $ A + K Q e i m q u y } > < A + K Q e i m q u y -J J B E ` A + K Q e i m q u y } J B I A O N O Q @ 9@ F@ T -J J B e A O N O Q @ 9@ F@ T W Z yQ V =d ] A O N O Q @ k F@ R n q yQ V =d R R K ? 9 2 t w z R R R R ' } 0 p P @ ` / * 2 I ` p ! P 3 O < N k / ? O _ @ \ @ P $ ` D d < @ P ( ` L Z r p @ P ` $ H h @ P ` ( H @ l P ` @ @ P d ` p @ 4 ` X @ | 0 @ 4 P X | 0 @ P 0 T o ' ; O c u O o p | p $ L t ` P O o p 0 < @ l P ` 0 0 + @ G b } P ` @ $ @ H ` l @ ` @ @ ` @ ` < @ ` ` 6 Q j @ P 4 P P h ` p p p @ @ " ' - 3 3 3 3 < B H N 3 3 3 3 T X \ ` d h l p t x | ! ! ( , @ P 4 0 ? Q @ ? h p ? , p 0 L ` 8 | @ , ( 0 0 P 4 P ? ? 0 T 0 t 0 8 d @ ` 0 ` P P P % @ 4 ` ` < ` p D h : @ 0 0 @ 0 0 8 @ 0 0 ` @ 0 @ 0 H 0 $ @ 0 P @ 0 t H 0 @ 0 @ 0 H 0 @ P X P j | H p 0 @ , 0 X 0 @ @ @ @ 0 < @ @ ` @ P @ ` @ p @ @ @ 8 @ \ @ @ @ @ @ 0 @ @ @ P @ ` ' @ p @ @ Y @ r @ @ @ @ @ @ @ ! @ < @ S @ 0 a @ @ o @ P } @ @ @ @ @ @ 5 0 O i 0 0 p 0 p p 0 p p = p Y @ P p p P 0 0 4 0 0 P \ @ P P u ~ . D $ H Z o 0 l @ p @ p @ @ + @ < M @ _ p @ @ @ P @ P @ P @ P @ P @ P 3 @ P @ P P N l @ @ P P @ P P + @ P A P X @ P n P @ P P @ P P @ P 0 P @ 0 P " 0 P 8 @ 0 P N P d P z 0 0 0 0 0 0 % 4 4 P T P l P l P P P P P P P P P P P P @ P @ P P P @ P @ P P 4 P Q n 0 0 t 0 0 @ @ ` < ` ` 8 \ | ` @ , P t P p 8 d 0 0 \ 0 | @ 0 ` 0 0 0 0 4 0 ` 0 0 @ 0 , ` 0 P 0 t 0 0 0 4 d @ ` 0 l 0 @ P D P D @ x 4 t @ P 4 P \ @ P " ? Z @ @ h D l 4 \ ( X < h 0 H p 0 H x 8 h (! X! ! ! ! " H" x" " " # @# p# # # $ <$ t$ $ $ % T% % % % 4& l& & & ' L' ' ' u 0 0 0 * 0 D ^ 0 x * 0 D ' P ( L( P x( ( P ( ) <) P h) ) ) ) * @* P l* * P * + 0+ `+ + + + , P L, x, , , , $- T- - - - . D. P p. . P . / 4/ \/ / / / 0 @0 p0 0 0 0 1 L1 |1 1 1 2 <2 P |2 P 2 P 2 P 3 P H3 P |3 P 3 P 3 P 4 P P4 P 4 P 4 P 4 P 05 P h5 P 5 P 5 @ P 6 @ P <6 @ P h6 @ P 6 @ P 6 @ P 6 @ P 7 @ P L7 @ P x7 @ P 7 @ P 7 @ P 8 @ P 48 @ P `8 @ P 8 @ P 8 @ P 8 @ P 9 @ P @9 @ P p9 @ P 9 @ P 9 4 O l 0 @ ` p . F C V @ i ~ P @ G @ F @ @ ! @ @@ 4 @ @ G @ @ Z @ A m @ @A @ A @ A @ B @ @B @ B @ B @ C @ @C @ C + @ C > @ Q @ b @ G s @ D } @ E @ F @ @ @ @ @ @ @ R ! @ Z > @ V : @ P 0: @ X T: @ [ @ w @ @ @ ( @ 0 @ 8 @ H x: @ ` @ h @ p : @ x : @ : @ : @ 5 @ P @ ; @ k @ @ @ @ @ @ / L; p; ; ; ; P p P @ ` p $ ` ,< ` p = 0 0 Q m @ 0 P p T< @ p ` < < < ? - ? G Z t < p = P @= P p l= = = 0 = p > (> P H> l> > 0 > 0 > 0 > 0 0 ? p 0 @? 0 d? P 0 ? p ? ? P ? P @ P 8@ 0 P X@ p |@ p @ 0 p @ p p @ p A P p 0A ` TA ` xA 0 ` A p ` A ` A P ` B p P ,B P PB P P pB 0 P p p p B p B p / p B p B p C p G p ] p 6 >6 >6 >6 >6 >6 >6 >6 >6 >6 / / / / / / / 4 1 60 / 4 3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / C/ / / / / / / / / / / / / / / / / / / / / / / / 7 / / / / 6 / / / / / / / / / / / / 6 6 K7 K7 K7 / / / / / / / / / / 7 / / / 7 6 / / / / / / / / / / / / 7 N= I= I= I= I= I= I= I= I= I= I= r= r= r= r= r= r= r= r= r= r= I= I= I= I= I= I= I= = *> j> I= > I= I= I= I= I= I= I= I= I= I= +? I= I= I= I= vA @ I= I= I= I= I= I= I= I= I= I= "A 5A GA I= B? I= I= I= I= I= I= I= m? I= T@ @ ? I= ? @ cD I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= D I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= I= E ?E I= I= I= I= I= I= I= _E I= E I= E I= I= I= I= I= I= I= I= I= I= I= I= I= E I= I= I= I= I= E H F F F F F F F F F F H H H H H H H H H H F F F F F F F F F H G F F F F oG F F F F I |I F F F L F F F F F OL L L L L xL L L L L L xL xL xL xL xL xL L L L L L JN N N N N N N N N N N ]N ]N ]N ]N ]N ]N ]N ]N ]N ]N N N N N N N N N xO mP O 2P P N N Q /Q ZQ N FT N N N N T T N TU N N Q N N N N N N N N Q R R N N N N N N N N N !S N N N N N S N N N S "T Y X Y Y Y Z Y Unknown error %d 0x%s Address 0x%s is out of bounds. ! ! ! __.SYMDEF __.SYMDEF/ / /SYM64/ ARFILENAMES/ // %-ld: %-ld ARFILENAMES/ // __.SYMDEF %-10ld bfd %-7lo %-12ld %-8lo ` bfd_dont_truncate_arname ../../../toolchain/android-toolchain/binutils-2.19/bfd/archive.c Reading archive file mod timestamp Writing updated armap timestamp Warning: writing archive was slow: rewriting timestamp binary e e `A No error System call error Invalid bfd target File in wrong format Invalid operation Memory exhausted No symbols No more archived files Malformed archive File format not recognized File format is ambiguous Section has no contents Bad value File truncated File too big Error reading %s: %s # Please report this bug. BFD: BFD %s assertion fail %s:%d coff-go32 pe-i386 pei-i386 pe-x86-64 pei-x86-64 pe-arm-wince-little pei-arm-wince-little Archive object file in wrong format Archive has no index; run ranlib to add one Nonrepresentable section on output Symbol needs debug section which does not exist BFD %s internal error, aborting at %s line %d in %s BFD %s internal error, aborting at %s line %d ../../../toolchain/android-toolchain/binutils-2.19/bfd/bfd.c x D h - F ^ h w bfd_set_error _bfd_default_error_handler _bfd_set_gp_value bfd_emul_get_maxpagesize bfd_emul_get_commonpagesize bfd_stat ../../../toolchain/android-toolchain/binutils-2.19/bfd/bfdio.c ../../../toolchain/android-toolchain/binutils-2.19/bfd/coffgen.c (sec %2d)(fl 0x%02x)(ty %3x)(scl %3d) (nx %d) 0x AUX scnlen 0x%lx nreloc %d nlnno %d checksum 0x%lx assoc %d comdat %d AUX tagndx %ld ttlsiz 0x%lx lnnos %ld next %ld AUX lnno %d size 0x%x tagndx %ld coff_fix_symbol_name strange .file %B: bad string table size %lu coff %s %s [%3ld] File endndx %ld %s : %4d : %-5s %s %s %s invalid core bfd_put_bits bfd_get_bits _bfd_generic_get_section_contents_in_window ../../../toolchain/android-toolchain/binutils-2.19/bfd/libbfd.c %B: compiled for a big endian system and target is little endian %B: compiled for a little endian system and target is big endian Deprecated %s called at %s line %d in %s Deprecated %s called / @ bfd_fdopenr 0 w,a Q m jp5 c d 2 y +L | ~ - d jHq A } mQ V l kdz b e O\ l cc= n;^ iL A` rqg jm Zjz ' }D h i]Wb ge q6l knv + Zz J go C ` ~ 8R O g gW ?K6 H + L J 6`z A ` U g n1y iF a f o%6 hR w G "/& U ; ( Z + j \ 1 , [ d & c ju m ?6 g r W J z + {8 |! B hn [& w owG Z pj ; f\ e i b kaE l x T N 9a&g ` MGiI wn>Jj Z f @ ; 7S G 0 0 S $ 6 )W T g #.zf Ja h] +o*7 Z -r+ .gnu_debuglink ../../../toolchain/android-toolchain/binutils-2.19/bfd/opncls.c *IND* *COM* *UND* *ABS* .%d Z ` ` f T bfd_get_unique_section_name bfd_map_over_sections ../../../toolchain/android-toolchain/binutils-2.19/bfd/section.c .data *DEBUG* .drectve .edata .fini .idata .init .pdata .rdata .rodata .sbss .scommon .sdata .text zerovars %c%c%c%c%c%c%c Unsupported .stab relocation b t U d [ N p N c i l e s t y i t p r r s c g t H d b < > @ @ ` * 9 G W k x armeb-*-netbsdelf* arm-*-netbsdelf* arm-*-nto* nto*arm* arm-*-rtems* armeb-*-elf arm*b-*-linux-* strongarm-*-kaos* arm-*-freebsd* arm*-*-linux-* arm*-*-conix* arm*-*-uclinux* arm-*-kfreebsd*-gnu arm*-*-eabi* arm9e-*-elf thumb-*-elf strongarm-*-elf xscale-*-elf GNUTARGET default ? ? bfd_hash_replace ! ;A ../../../toolchain/android-toolchain/binutils-2.19/bfd/hash.c symbolsrec \%03o .sec%d $$ $$ %-5s %s w } 1 ] } 1 ] E 6 E E + g B W 7 l / S B B $ C C d % ; ; B E R . " 1 ; n u # w } 1 ] } 1 ] E 5 E E + g B W 7 l / S B B $ C C d % ; ; B E R . " 1 ; n u # 0123456789ABCDEF 3 u1 T3 3 - 3 - 3 5 5 _? _? i? > = = = > i? _? %B:%d: Unexpected character `%s' in S-record file %B:%d: Bad checksum in S-record file ../../../toolchain/android-toolchain/binutils-2.19/bfd/srec.c _binary_%s_%s start { } 1 ] } 1 ] E C E E C W D l / S BE E $ F d % G H E R . " 1 ; n u # Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx. tekhex %0781010 ' w } 1 ] } 1 ] E L E E L g pR W ?O l / S rL 4L U \U GU d % O O U E R . " 1 ; n u # 0123456789ABCDEF K J K K K J K K K out tekhex_write_object_contents T T T T S S S S S S S S S S T S S S S S T S S S S S S S S S S S T T S T S S S S S S S S S S T S S S S T ../../../toolchain/android-toolchain/binutils-2.19/bfd/tekhex.c ihex L } 1 ] } 1 ] E _ E E U g \ W V l / S $ ^ Y _ E R . " 1 ; n u # 0123456789ABCDEF lc 3d Zd e d e %B:%d: unexpected character `%s' in Intel Hex file ../../../toolchain/android-toolchain/binutils-2.19/bfd/ihex.c %B: internal error in ihex_read_section %B: bad section length in ihex_read_section %s: address 0x%s out of range for Intel Hex file %B:%u: bad checksum in Intel Hex file (expected %u, found %u) %B:%u: bad extended address record length in Intel Hex file %B:%u: bad extended start address length in Intel Hex file %B:%u: bad extended linear address record length in Intel Hex file %B:%u: bad extended linear start address length in Intel Hex file %B:%u: unrecognized ihex type %u in Intel Hex file WARNING GSYM FNAME FUN STSYM LCSYM MAIN ROSYM BNSYM NSYMS NOMAP OBJ OPT M2C DSLINE BSLINE DEFD FLINE ENSYM EHDECL CATCH SSYM ENDM OSO ALIAS LSYM BINCL SOL PSYM EINCL LBRAC SCOPE PATCH RBRAC BCOMM ECOMM ECOML WITH NBTEXT NBDATA NBBSS NBSTS NBLCS LENG SETA SETT SETD SETB SETV INDR ;h 7h 7h 7h 7h 7h 7h 7h 7h 7h Bh 7h Ih 7h Ph 7h Wh 7h ^h 7h eh 7h lh 7h sh 7h zh 7h h 7h h 7h h 7h h 7h h 7h h 7h h 7h h 7h 7h 7h h 7h 7h 7h h 7h 7h 7h h 7h h 7h h 7h h 7h h 7h h 7h h 7h h 7h h 7h 7h 7h i 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h i 7h i 7h i 7h "i 7h 7h 7h 7h 7h )i 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 0i 7h 7i 7h >i 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h Ei 7h Li 7h Si 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h Zi 7h ai 7h hi 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h oi 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h 7h vi 7h }i 7h i 7h 7h 7h i 7h i 7h 7h 7h 7h 7h i 7h i 7h i 7h i 7h i 7h 7h 7h 7h 7h i Dwarf Error: Can't find %s section. Dwarf Error: unable to decompress %s section. Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu). ../../../toolchain/android-toolchain/binutils-2.19/bfd/dwarf2.c Dwarf Error: Invalid or unhandled FORM value: %u. Dwarf Error: mangled line number section (bad file number). Dwarf Error: Could not find abbrev number %u. Dwarf Error: mangled line number section. /disk2/dougkwan/android-3/arm-eabi-4.3.1/lib/debug Dwarf Error: found dwarf version '%u', this reader only handles version 2 and 3 information. Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'. Dwarf Error: found address size '%u', this reader can only handle address sizes '2', '4' and '8'. Dwarf Error: Bad abbrev number: %u. %s/%s/%s read_address n o n o o $o @o \o @p [p q q q r p to Vq q $o @o \o to p find_abstract_instance_name scan_unit_for_symbols find_line ZLIB 1.2.3 elf32-littlearm-symbian aeabi .ARM.attributes .dynamic .dynstr .dynsym .init_array .fini_array .preinit_array elf32-bigarm-symbian elf32-littlearm-vxworks elf32-bigarm-vxworks elf32-littlearm elf32-bigarm R_ARM_RREL32 R_ARM_RABS32 R_ARM_RPC24 R_ARM_RBASE R_ARM_NONE R_ARM_PC24 R_ARM_ABS32 R_ARM_REL32 R_ARM_LDR_PC_G0 R_ARM_ABS16 R_ARM_ABS12 R_ARM_THM_ABS5 R_ARM_ABS8 R_ARM_SBREL32 R_ARM_THM_CALL R_ARM_THM_PC8 R_ARM_BREL_ADJ R_ARM_SWI24 R_ARM_SWI8 R_ARM_XPC25 R_ARM_THM_XPC22 R_ARM_TLS_DTPMOD32 R_ARM_TLS_DTPOFF32 R_ARM_TLS_TPOFF32 R_ARM_COPY R_ARM_GLOB_DAT R_ARM_JUMP_SLOT R_ARM_RELATIVE R_ARM_GOTOFF32 R_ARM_GOTPC R_ARM_GOT32 R_ARM_PLT32 R_ARM_CALL R_ARM_JUMP24 R_ARM_THM_JUMP24 R_ARM_BASE_ABS R_ARM_ALU_PCREL_7_0 R_ARM_ALU_PCREL_15_8 R_ARM_ALU_PCREL_23_15 R_ARM_LDR_SBREL_11_0 R_ARM_ALU_SBREL_19_12 R_ARM_ALU_SBREL_27_20 R_ARM_TARGET1 R_ARM_ROSEGREL32 R_ARM_V4BX R_ARM_TARGET2 R_ARM_PREL31 R_ARM_MOVW_ABS_NC R_ARM_MOVT_ABS R_ARM_MOVW_PREL_NC R_ARM_MOVT_PREL R_ARM_THM_MOVW_ABS_NC R_ARM_THM_MOVT_ABS R_ARM_THM_MOVW_PREL_NC R_ARM_THM_MOVT_PREL R_ARM_THM_JUMP19 R_ARM_THM_JUMP6 R_ARM_THM_ALU_PREL_11_0 R_ARM_THM_PC12 R_ARM_ABS32_NOI R_ARM_REL32_NOI R_ARM_ALU_PC_G0_NC R_ARM_ALU_PC_G0 R_ARM_ALU_PC_G1_NC R_ARM_ALU_PC_G1 R_ARM_ALU_PC_G2 R_ARM_LDR_PC_G1 R_ARM_LDR_PC_G2 R_ARM_LDRS_PC_G0 R_ARM_LDRS_PC_G1 R_ARM_LDRS_PC_G2 R_ARM_LDC_PC_G0 R_ARM_LDC_PC_G1 R_ARM_LDC_PC_G2 R_ARM_ALU_SB_G0_NC R_ARM_ALU_SB_G0 R_ARM_ALU_SB_G1_NC R_ARM_ALU_SB_G1 R_ARM_ALU_SB_G2 R_ARM_LDR_SB_G0 R_ARM_LDR_SB_G1 R_ARM_LDR_SB_G2 R_ARM_LDRS_SB_G0 R_ARM_LDRS_SB_G1 R_ARM_LDRS_SB_G2 R_ARM_LDC_SB_G0 R_ARM_LDC_SB_G1 R_ARM_LDC_SB_G2 R_ARM_MOVW_BREL_NC R_ARM_MOVT_BREL R_ARM_MOVW_BREL R_ARM_THM_MOVW_BREL_NC R_ARM_THM_MOVT_BREL R_ARM_THM_MOVW_BREL R_ARM_PLT32_ABS R_ARM_GOT_ABS R_ARM_GOT_PREL R_ARM_GOT_BREL12 R_ARM_GOTOFF12 R_ARM_GNU_VTENTRY R_ARM_GNU_VTINHERIT R_ARM_THM_JUMP11 R_ARM_THM_JUMP8 R_ARM_TLS_GD32 R_ARM_TLS_LDM32 R_ARM_TLS_LDO32 R_ARM_TLS_IE32 R_ARM_TLS_LE32 R_ARM_TLS_LDO12 R_ARM_TLS_LE12 R_ARM_TLS_IE12GP .reg .rel .rela .got.plt .rel.got .rela.got .rel.plt .rela.plt .dynbss .rel.bss .rela.bss %08x_%s+%x %08x_%x:%x+%x unnamed __%s_from_thumb __%s_from_arm __%s_veneer .stub .glue_7 .glue_7t .vfp11_veneer .v4_bx linker stubs __bx_r%d __%s_change_to_arm __vfp11_veneer_%x __vfp11_veneer_%x_r $a got-rel .tls_vars out of range unsupported relocation unknown error .note.gnu.arm.ident variable-size private flags = %lx: [interworking enabled] [APCS-26] [APCS-32] [VFP float format] [Maverick float format] [FPA float format] [position independent] [new ABI] [old ABI] [software FP] [Version1 EABI] [sorted symbol table] [unsorted symbol table] [Version2 EABI] [Version3 EABI] [Version4 EABI] [Version5 EABI] [BE8] [LE8] [relocatable executable] [has entry point] %B: bad symbol index: %d __real_%s .interp /usr/lib/ld.so.1 .gnu.version .gnu.version_d .gnu.version_r .ARM.exidx .gnu.linkonce.armexidx. $t $d ? / 1 W k q 1 W k q E l - g & ( x $y t l t' ( " X & 7 L ` t Wp ,w @ 8 $l k S ( ) G? [ s? ? F ? G B LI d % [) m) D n ? C (C E { ; m> " ] 2 u a ( * tq S* * v ? / } 1 ] } 1 ] E l - g & ( x $y t l t' ( " X & 7 L ` t Wp ,w @ 8 $l k S ( ) G? [ s? ? F ? G B LI d % [) m) D n ? C (C E { ; m> " ] 2 u a ( * tq S* * @ ? / 1 W k q 1 W k q E l - g & ( x $y t l t' ( " X & 7 L ` t Wp ,w @ 8 $l k S ( ) G? [ s? ? F ? G B LI d % [) m) D n ? C (C E P{ ; m> " ] 2 u a ( * tq S* * ( ? / } 1 ] } 1 ] E l - g & ( x $y t l t' ( " X & 7 L ` t Wp ,w @ 8 $l k S ( ) G? [ s? ? F ? G B LI d % [) m) D n ? C (C E P{ ; m> " ] 2 u a ( * tq S* * @ = ? / 1 W k q 1 W k q E l - g & ( x $y t l t' ( " X & 7 L ` t Wp ,w @ 8 $l k S ( ) G? [ s? ? F ? G B LI d % [) m) D n ? C (C E ; m> " ] 2 u a ( * tq S* * M ? / } 1 ] } 1 ] E l - g & ( x $y t l t' ( " X & 7 L ` t Wp ,w @ 8 $l k S ( ) G? [ s? ? F ? G B LI d % [) m) D n ? C (C E ; m> " ] 2 u a ( * tq S* * 4 ( ty y 6 ? s 6 q - - xG F 7 Z 7 g 7 t 7 7 7 7 7 7 7 7 7 7 7 7 7 7 ' 7 6 7 B 7 M 7 Y 7 i 7 | 7 7 7 7 7 7 7 7 7 7 7 7 % / / 7 6 7 E ! 7 Y " 7 n # 7 $ 7 % 7 & 7 ' 7 ( 7 ) 7 * 7 + 7 , 7 - 7 + . 7 > / 7 N p p 0 7 d p p 1 7 w p p 2 7 p p 3 7 /? /? 4 7 5 7 6 7 7 7 8 7 9 7 : 7 ; 7 - < 7 @ = 7 P > 7 ` ? 7 p @ 7 A 7 B 7 C 7 D 7 E 7 F 7 G 7 H 7 I 7 J 7 ) K 7 9 L 7 I M 7 Y N 7 i O 7 z P 7 Q 7 R 7 S 7 T 7 U 7 V 7 W 7 p p X 7 p p Y 7 * p p Z [ \ ] ^ 7 > _ 7 N ` 7 \ a 7 k b 7 | c d E e f 7 g 7 h i 7 j 7 k l 7 m 7 n 7 / o 7 > FxG 7 f 3 g 4 & ' * ) h j i k l ~ e d + , - . / 0 1 2 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S ( xG F @ N F0G@@ / @ N F0G@ / create_got_section elf32_arm_create_dynamic_sections v c P = < k bfd_elf32_arm_process_before_allocation bfd_arm_vfp11_insn_decode - - - - m t D D D D D D D D D D D D D T T T record_vfp11_erratum_veneer bfd_elf32_arm_vfp11_erratum_scan bfd_elf32_arm_vfp11_fix_veneer_locations elf32_arm_final_link_relocate 0 ; % % U % _ K K K K m - j j j j j j K K K - - U U W W W v W W e e @ 8 8 8 8 8 8 8 8 W W e e @ 3 ? p T T T T T T T T T T T 3 ? p < ' K < ' K O p elf32_arm_merge_eabi_attributes + + ". + ". ". :, ". ". Z, , , - k- - ". ". ". ". ". B- ". + ". + W. + + ? 1? 1? 1? ? ? ? ? ? ? 1? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1? 1? 1? 1? ? ? ? ? ? ? ? ? ? ? ? 1? 1? 1? 1? 1? 1? 1? 1? 1? 1? ? ? ? 1? 1? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ~B A mC mC ~B ~B A ~B ~B ~B A ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B B B B A A A A ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B A mC mC mC mC mC mC mC mC A ~B ~B ~B mC mC ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B ~B B ~B ~B ~B uC C ~B ~B B B ~B B allocate_dynrelocs ap p p p q fq p elf32_arm_write_section ../../../toolchain/android-toolchain/binutils-2.19/bfd/elf32-arm.c %B(%s): warning: interworking not enabled. first occurrence: %B: Thumb call to ARM %s: cannot create stub entry %s %B: BE8 images only valid in big-endian mode. %B: warning: selected VFP11 erratum workaround is not necessary for target architecture %B: unable to find VFP11 veneer `%s' Invalid TARGET2 relocation type '%s'. unable to find ARM glue '%s' for '%s' %B(%s): warning: interworking not enabled. first occurrence: %B: arm call to thumb %B(%A+0x%lx): %s relocation against SEC_MERGE section %B(%A+0x%lx): %s used with TLS symbol %s %B(%A+0x%lx): %s used with non-TLS symbol %s %B: Warning: Arm BLX instruction targets Arm function '%s'. %B: Warning: Thumb BLX instruction targets thumb function '%s'. unable to find THUMB glue '%s' for '%s' %B(%s): warning: interworking not enabled. first occurrence: %B: thumb call to arm %B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object %B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s %B(%A+0x%lx): unresolvable %s relocation against symbol `%s' %B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations Warning: Not setting interworking flag of %B since it has already been specified as non-interworking Warning: Clearing the interworking flag of %B due to outside request Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it ERROR: %B uses VFP register arguments, %B does not ERROR: %B: Conflicting architecture profiles %c/%c Warning: %B: Conflicting platform configuration ERROR: %B: Conflicting use of R9 ERROR: %B: SB relative addressing conflicts with use of R9 warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail ERROR: %B uses iWMMXt register arguments, %B does not Warning: %B: Unknown EABI object attribute %d ERROR: %B is already in final BE8 format ERROR: Source object %B has EABI version %d, but target %B has EABI version %d ERROR: %B is compiled for APCS-%d, whereas target %B uses APCS-%d ERROR: %B passes floats in float registers, whereas %B passes them in integer registers ERROR: %B passes floats in integer registers, whereas %B passes them in float registers ERROR: %B uses VFP instructions, whereas %B does not ERROR: %B uses FPA instructions, whereas %B does not ERROR: %B uses Maverick instructions, whereas %B does not ERROR: %B does not use Maverick instructions, whereas %B does ERROR: %B uses software FP, whereas %B uses hardware FP ERROR: %B uses hardware FP, whereas %B uses software FP Warning: %B supports interworking, whereas %B does not Warning: %B does not support interworking, whereas %B does [floats passed in float registers] [dynamic symbols use segment index] [mapping symbols precede others] dynamic variable `%s' is zero size Errors encountered processing file %s %B: error: VFP11 veneer out of range 4 ( | w} 6 ? s 6 q bfd_elf32_swap_symbol_out bfd_elf32_write_relocs > > 7 ../../../toolchain/android-toolchain/binutils-2.19/bfd/elfcode.h %s: version count (%ld) does not match symbol count (%ld) %s(%s): relocation %d has invalid symbol index %ld Warning: %B is truncated: expected core file size >= %lu, found: %lu. warning: %s has a corrupt string table index - ignoring __GOTT_BASE__ __GOTT_INDEX__ .rela.plt.unloaded .rel.plt.unloaded .tls_data LARGE_COMMON SHT_NULL SHT_PROGBITS SHT_SYMTAB SHT_STRTAB SHT_RELA SHT_HASH SHT_DYNAMIC SHT_NOTE SHT_NOBITS SHT_REL SHT_SHLIB SHT_DYNSYM .tbss .tdata .shstrtab .strtab .symtab .rodata1 .note.GNU-stack .note .line .gnu.linkonce.b .gnu.liblist .gnu.conflict .gnu.hash .data1 .comment (null) RELRO INTERP PHDR EH_FRAME STACK (*none*) Base %-11s .internal .hidden .protected 0x%02x %s%d%s .symtab_shndx .gnu.libstr LOPROC+%7.7x LOOS+%7.7x %8.8x Program Header: %8s off 0x vaddr 0x paddr 0x align 2**%u filesz 0x memsz 0x flags %c%c%c Dynamic Section: FILTER GNU_HASH NEEDED PLTRELSZ PLTGOT RELASZ RELAENT STRSZ SYMENT INIT FINI SONAME RPATH SYMBOLIC RELENT TEXTREL JMPREL BIND_NOW FINI_ARRAY FINI_ARRAYSZ RUNPATH FLAGS PREINIT_ARRAY PREINIT_ARRAYSZ CHECKSUM PLTPADSZ MOVEENT MOVESZ FEATURE POSFLAG_1 SYMINSZ SYMINENT CONFIG DEPAUDIT PLTPAD MOVETAB SYMINFO RELACOUNT RELCOUNT FLAGS_1 VERSYM VERDEF VERDEFNUM VERNEED VERNEEDNUM AUXILIARY USED %-20s Version definitions: %d 0x%2.2x 0x%8.8lx %s Version References: required from %s: %s/%d %s/%ld NetBSD-CORE .note.netbsdcore.procinfo .reg2 QNX .qnx_core_info .qnx_core_status/%ld .qnx_core_status SPU/ win32 .reg/%ld .module/%08lx LINUX .reg-xfp .reg-ppc-vmx .reg-ppc-vsx .auxv GNU null load shlib phdr eh_frame_hdr relro zdebug %B: invalid SHT_GROUP entry .gnu.linkonce + 6 A J S _ h s { H G G G {/ Y T v o o o o o s U p G ?- G G bfd_elf_get_elf_syms bfd_elf_set_group_contents get_program_header_size rewrite_elf_program_header assign_file_positions_for_non_load_sections _bfd_elf_get_lineno _bfd_elf_no_info_to_howto D D D D D D E D E D D D D D D D D D vE D D D D D lE D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D bE YE D D D RE D D D IE D D D D D D D BE D D D D D D D :E D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D E q .- 9/ 4 ../../../toolchain/android-toolchain/binutils-2.19/bfd/elf.c %B: invalid string offset %u >= %lu for section `%s' %B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section %B: warning: sh_link not set for section `%A' %B: sh_link [%d] in section `%A' is incorrect %B: unknown [%d] section `%s' in group [%s] warning: section `%A' type changed to PROGBITS %B: symbol `%s' required but not present %B: warning: Empty loadable segment detected, is this intentional ? Unable to find equivalent output section for symbol '%s' from section '%s' %B: sh_link of section `%A' points to discarded section `%A' of `%B' %B: sh_link of section `%A' points to removed section `%A' of `%B' %B: The first section in the PT_DYNAMIC segment is not the .dynamic section %B: Not enough room for program headers, try linking with -N %B: section %A vma 0x%lx overlaps previous sections %B: section `%A' can't be allocated in segment %d %B: warning: allocated section `%s' not in segment 0x%8.8lx 0x%2.2x %2.2d %s %B: unsupported relocation type %s %B: Corrupt size field in group section header: 0x%lx %B: no group info for section %A %B: invalid link %lu for reloc section %s (index %u) %B: don't know how to handle allocated, application specific section `%s' [0x%8x] %B: don't know how to handle processor specific section `%s' [0x%8x] %B: don't know how to handle OS specific section `%s' [0x%8x] %B: don't know how to handle section `%s' [0x%8x] % C a @ bfd_elf_record_link_assignment } #} #} { { { B} } s s _ _ _bfd_elf_link_output_relocs elf_link_add_object_symbols bfd_elf_size_dynsym_hash_dynstr put_value get_value elf_link_adjust_relocs elf_link_check_versioned_symbol t0 2 2 2 2 2 elf_link_output_extsym ;4 5 5 5 5 6 a4 elf_reloc_link_order _bfd_elf_section_already_linked _GLOBAL_OFFSET_TABLE_ _PROCEDURE_LINKAGE_TABLE_ .gnu.warning. .tcommon %s: undefined version: %s .end symbol 0- << >> == != && || ~ local .gcc_except_table .gnu.attributes .rela.dyn .rel.dyn .gnu.linkonce. ../../../toolchain/android-toolchain/binutils-2.19/bfd/elflink.c %s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A %s: TLS reference in %B mismatches non-TLS reference in %B %s: TLS definition in %B section %A mismatches non-TLS reference in %B %s: TLS reference in %B mismatches non-TLS definition in %B section %A %B: unexpected redefinition of indirect versioned symbol `%s' %B: version node not found for symbol %s %B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A' %B: relocation size mismatch in %B section %A warning: type and size of dynamic symbol `%s' are not defined %B: %s: invalid version %u (max %d) %B: %s: invalid needed version %d Warning: alignment %u of common symbol `%s' in %B is greater than the alignment (%u) of its section %A Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B Warning: size of symbol `%s' changed from %lu in %B to %lu in %B Warning: type of symbol `%s' changed from %d to %d in %B %s: invalid DSO for symbol `%s' definition %B: .preinit_array section is not allowed in DSO undefined %s reference in complex symbol: %s unknown operator '%c' in complex symbol %B: Too many sections: %d (>= %d) %B: %s symbol `%s' in %B is referenced by DSO %B: could not find output section %A for input section %A %B: %s symbol `%s' isn't defined %A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections %A has both ordered and unordered sections error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol %X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B %B: Unable to sort relocs - they are in more than one size %B: Unable to sort relocs - they are of an unknown size Not enough memory to sort relocations %B: could not find output section %s warning: %s section has zero size %P: warning: creating a DT_TEXTREL in a shared object. %P%X: can not read symbols: %E Warning: gc-sections option ignored Removing unused section '%s' in file '%B' %B: %A+%lu: No symbol found for INHERIT %B: ignoring duplicate section `%A' %B: duplicate section `%A' has different size %B: warning: could not read contents of section `%A' %B: warning: duplicate section `%A' has different contents %F%P: already_linked_table: %E bfd_elf_set_obj_attr_contents _bfd_elf_copy_obj_attributes _bfd_elf_obj_attrs_arg_type _bfd_elf_parse_attributes ../../../toolchain/android-toolchain/binutils-2.19/bfd/elf-attrs.c ERROR: %B: Must be processed by '%s' toolchain ERROR: %B: Incompatible object tag '%s':%d ../../../toolchain/android-toolchain/binutils-2.19/bfd/elf-strtab.c ../../../toolchain/android-toolchain/binutils-2.19/bfd/elf-eh-frame.c %P: error in %B(%A); no .eh_frame_hdr table will be created. %P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created. v v v y 5 v v v v 5 [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ v [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ _bfd_elf_write_section_eh_frame ! 9 R h ~ elf32-little elf32-big UNKNOWN D< ? / 1 W k q 1 W k q E l g & ( E ! l r " X ,3 L ` t Wp ,w @ 8 $l k S ( ) G? [ s? ? ? +A B B d % [) m) u ? C (C E R ] " ] 2 u a ( * tq S* * > Q< ? / } 1 ] } 1 ] E l g & ( E ! l r " X ,3 L ` t Wp ,w @ 8 $l k S ( ) G? [ s? ? ? +A B B d % [) m) u ? C (C E R ] " ] 2 u a ( * tq S* * < [< %B: Relocations in generic ELF (EM: %d) armv2 armv2a armv3 armv3m armv4 armv4t armv5 armv5t armv5te xscale ep9312 iwmmxt iwmmxt2 arm2 arm250 arm3 arm6 arm60 arm600 arm610 arm7 arm710 arm7500 arm7d arm7di arm7dm arm7dmi arm7tdmi arm8 arm810 arm9 arm920 arm920t arm9tdmi sa1 strongarm strongarm110 strongarm1100 armv3M XScale iWMMXt iWMMXt2 arch: ! A ! @ A ! "@ B ! )@ 0B ! /@ `B ! 6@ B ! <@ B ! C@ B ! I@ C ! P@ PC ! X@ C ! _@ C ! f@ C ! m@ u ~ ERROR: %B is compiled for the EP9312, whereas %B is compiled for XScale warning: unable to update contents of %s section in %s z 5 y bfd_cache_lookup_worker ../../../toolchain/android-toolchain/binutils-2.19/bfd/cache.c w+ reopening %B: %s @@uninitialized@@ BFD_RELOC_64 BFD_RELOC_32 BFD_RELOC_26 BFD_RELOC_24 BFD_RELOC_16 BFD_RELOC_14 BFD_RELOC_8 BFD_RELOC_64_PCREL BFD_RELOC_32_PCREL BFD_RELOC_24_PCREL BFD_RELOC_16_PCREL BFD_RELOC_12_PCREL BFD_RELOC_8_PCREL BFD_RELOC_32_SECREL BFD_RELOC_32_GOT_PCREL BFD_RELOC_16_GOT_PCREL BFD_RELOC_8_GOT_PCREL BFD_RELOC_32_GOTOFF BFD_RELOC_16_GOTOFF BFD_RELOC_LO16_GOTOFF BFD_RELOC_HI16_GOTOFF BFD_RELOC_HI16_S_GOTOFF BFD_RELOC_8_GOTOFF BFD_RELOC_64_PLT_PCREL BFD_RELOC_32_PLT_PCREL BFD_RELOC_24_PLT_PCREL BFD_RELOC_16_PLT_PCREL BFD_RELOC_8_PLT_PCREL BFD_RELOC_64_PLTOFF BFD_RELOC_32_PLTOFF BFD_RELOC_16_PLTOFF BFD_RELOC_LO16_PLTOFF BFD_RELOC_HI16_PLTOFF BFD_RELOC_HI16_S_PLTOFF BFD_RELOC_8_PLTOFF BFD_RELOC_68K_GLOB_DAT BFD_RELOC_68K_JMP_SLOT BFD_RELOC_68K_RELATIVE BFD_RELOC_32_BASEREL BFD_RELOC_16_BASEREL BFD_RELOC_LO16_BASEREL BFD_RELOC_HI16_BASEREL BFD_RELOC_HI16_S_BASEREL BFD_RELOC_8_BASEREL BFD_RELOC_RVA BFD_RELOC_8_FFnn BFD_RELOC_32_PCREL_S2 BFD_RELOC_16_PCREL_S2 BFD_RELOC_23_PCREL_S2 BFD_RELOC_HI22 BFD_RELOC_LO10 BFD_RELOC_GPREL16 BFD_RELOC_GPREL32 BFD_RELOC_I960_CALLJ BFD_RELOC_NONE BFD_RELOC_SPARC_WDISP22 BFD_RELOC_SPARC22 BFD_RELOC_SPARC13 BFD_RELOC_SPARC_GOT10 BFD_RELOC_SPARC_GOT13 BFD_RELOC_SPARC_GOT22 BFD_RELOC_SPARC_PC10 BFD_RELOC_SPARC_PC22 BFD_RELOC_SPARC_WPLT30 BFD_RELOC_SPARC_COPY BFD_RELOC_SPARC_GLOB_DAT BFD_RELOC_SPARC_JMP_SLOT BFD_RELOC_SPARC_RELATIVE BFD_RELOC_SPARC_UA16 BFD_RELOC_SPARC_UA32 BFD_RELOC_SPARC_UA64 BFD_RELOC_SPARC_GOTDATA_HIX22 BFD_RELOC_SPARC_GOTDATA_LOX10 BFD_RELOC_SPARC_GOTDATA_OP BFD_RELOC_SPARC_BASE13 BFD_RELOC_SPARC_BASE22 BFD_RELOC_SPARC_10 BFD_RELOC_SPARC_11 BFD_RELOC_SPARC_OLO10 BFD_RELOC_SPARC_HH22 BFD_RELOC_SPARC_HM10 BFD_RELOC_SPARC_LM22 BFD_RELOC_SPARC_PC_HH22 BFD_RELOC_SPARC_PC_HM10 BFD_RELOC_SPARC_PC_LM22 BFD_RELOC_SPARC_WDISP16 BFD_RELOC_SPARC_WDISP19 BFD_RELOC_SPARC_7 BFD_RELOC_SPARC_6 BFD_RELOC_SPARC_5 BFD_RELOC_SPARC_PLT32 BFD_RELOC_SPARC_PLT64 BFD_RELOC_SPARC_HIX22 BFD_RELOC_SPARC_LOX10 BFD_RELOC_SPARC_H44 BFD_RELOC_SPARC_M44 BFD_RELOC_SPARC_L44 BFD_RELOC_SPARC_REGISTER BFD_RELOC_SPARC_REV32 BFD_RELOC_SPARC_TLS_GD_HI22 BFD_RELOC_SPARC_TLS_GD_LO10 BFD_RELOC_SPARC_TLS_GD_ADD BFD_RELOC_SPARC_TLS_GD_CALL BFD_RELOC_SPARC_TLS_LDM_HI22 BFD_RELOC_SPARC_TLS_LDM_LO10 BFD_RELOC_SPARC_TLS_LDM_ADD BFD_RELOC_SPARC_TLS_LDM_CALL BFD_RELOC_SPARC_TLS_LDO_HIX22 BFD_RELOC_SPARC_TLS_LDO_LOX10 BFD_RELOC_SPARC_TLS_LDO_ADD BFD_RELOC_SPARC_TLS_IE_HI22 BFD_RELOC_SPARC_TLS_IE_LO10 BFD_RELOC_SPARC_TLS_IE_LD BFD_RELOC_SPARC_TLS_IE_LDX BFD_RELOC_SPARC_TLS_IE_ADD BFD_RELOC_SPARC_TLS_LE_HIX22 BFD_RELOC_SPARC_TLS_LE_LOX10 BFD_RELOC_SPARC_TLS_DTPMOD32 BFD_RELOC_SPARC_TLS_DTPMOD64 BFD_RELOC_SPARC_TLS_DTPOFF32 BFD_RELOC_SPARC_TLS_DTPOFF64 BFD_RELOC_SPARC_TLS_TPOFF32 BFD_RELOC_SPARC_TLS_TPOFF64 BFD_RELOC_SPU_IMM7 BFD_RELOC_SPU_IMM8 BFD_RELOC_SPU_IMM10 BFD_RELOC_SPU_IMM10W BFD_RELOC_SPU_IMM16 BFD_RELOC_SPU_IMM16W BFD_RELOC_SPU_IMM18 BFD_RELOC_SPU_PCREL9a BFD_RELOC_SPU_PCREL9b BFD_RELOC_SPU_PCREL16 BFD_RELOC_SPU_LO16 BFD_RELOC_SPU_HI16 BFD_RELOC_SPU_PPU32 BFD_RELOC_SPU_PPU64 BFD_RELOC_ALPHA_GPDISP_HI16 BFD_RELOC_ALPHA_GPDISP_LO16 BFD_RELOC_ALPHA_GPDISP BFD_RELOC_ALPHA_LITERAL BFD_RELOC_ALPHA_ELF_LITERAL BFD_RELOC_ALPHA_LITUSE BFD_RELOC_ALPHA_HINT BFD_RELOC_ALPHA_LINKAGE BFD_RELOC_ALPHA_CODEADDR BFD_RELOC_ALPHA_GPREL_HI16 BFD_RELOC_ALPHA_GPREL_LO16 BFD_RELOC_ALPHA_BRSGP BFD_RELOC_ALPHA_TLSGD BFD_RELOC_ALPHA_TLSLDM BFD_RELOC_ALPHA_DTPMOD64 BFD_RELOC_ALPHA_GOTDTPREL16 BFD_RELOC_ALPHA_DTPREL64 BFD_RELOC_ALPHA_DTPREL_HI16 BFD_RELOC_ALPHA_DTPREL_LO16 BFD_RELOC_ALPHA_DTPREL16 BFD_RELOC_ALPHA_GOTTPREL16 BFD_RELOC_ALPHA_TPREL64 BFD_RELOC_ALPHA_TPREL_HI16 BFD_RELOC_ALPHA_TPREL_LO16 BFD_RELOC_ALPHA_TPREL16 BFD_RELOC_MIPS_JMP BFD_RELOC_MIPS16_JMP BFD_RELOC_MIPS16_GPREL BFD_RELOC_HI16 BFD_RELOC_HI16_S BFD_RELOC_LO16 BFD_RELOC_HI16_PCREL BFD_RELOC_HI16_S_PCREL BFD_RELOC_LO16_PCREL BFD_RELOC_MIPS16_GOT16 BFD_RELOC_MIPS16_CALL16 BFD_RELOC_MIPS16_HI16 BFD_RELOC_MIPS16_HI16_S BFD_RELOC_MIPS16_LO16 BFD_RELOC_MIPS_LITERAL BFD_RELOC_MIPS_GOT16 BFD_RELOC_MIPS_CALL16 BFD_RELOC_MIPS_GOT_HI16 BFD_RELOC_MIPS_GOT_LO16 BFD_RELOC_MIPS_CALL_HI16 BFD_RELOC_MIPS_CALL_LO16 BFD_RELOC_MIPS_SUB BFD_RELOC_MIPS_GOT_PAGE BFD_RELOC_MIPS_GOT_OFST BFD_RELOC_MIPS_GOT_DISP BFD_RELOC_MIPS_SHIFT5 BFD_RELOC_MIPS_SHIFT6 BFD_RELOC_MIPS_INSERT_A BFD_RELOC_MIPS_INSERT_B BFD_RELOC_MIPS_DELETE BFD_RELOC_MIPS_HIGHEST BFD_RELOC_MIPS_HIGHER BFD_RELOC_MIPS_SCN_DISP BFD_RELOC_MIPS_REL16 BFD_RELOC_MIPS_RELGOT BFD_RELOC_MIPS_JALR BFD_RELOC_MIPS_TLS_DTPMOD32 BFD_RELOC_MIPS_TLS_DTPREL32 BFD_RELOC_MIPS_TLS_DTPMOD64 BFD_RELOC_MIPS_TLS_DTPREL64 BFD_RELOC_MIPS_TLS_GD BFD_RELOC_MIPS_TLS_LDM BFD_RELOC_MIPS_TLS_GOTTPREL BFD_RELOC_MIPS_TLS_TPREL32 BFD_RELOC_MIPS_TLS_TPREL64 BFD_RELOC_MIPS_TLS_TPREL_HI16 BFD_RELOC_MIPS_TLS_TPREL_LO16 BFD_RELOC_MIPS_COPY BFD_RELOC_MIPS_JUMP_SLOT BFD_RELOC_FRV_LABEL16 BFD_RELOC_FRV_LABEL24 BFD_RELOC_FRV_LO16 BFD_RELOC_FRV_HI16 BFD_RELOC_FRV_GPREL12 BFD_RELOC_FRV_GPRELU12 BFD_RELOC_FRV_GPREL32 BFD_RELOC_FRV_GPRELHI BFD_RELOC_FRV_GPRELLO BFD_RELOC_FRV_GOT12 BFD_RELOC_FRV_GOTHI BFD_RELOC_FRV_GOTLO BFD_RELOC_FRV_FUNCDESC BFD_RELOC_FRV_FUNCDESC_GOT12 BFD_RELOC_FRV_FUNCDESC_GOTHI BFD_RELOC_FRV_FUNCDESC_GOTLO BFD_RELOC_FRV_FUNCDESC_VALUE BFD_RELOC_FRV_GOTOFF12 BFD_RELOC_FRV_GOTOFFHI BFD_RELOC_FRV_GOTOFFLO BFD_RELOC_FRV_GETTLSOFF BFD_RELOC_FRV_TLSDESC_VALUE BFD_RELOC_FRV_GOTTLSDESC12 BFD_RELOC_FRV_GOTTLSDESCHI BFD_RELOC_FRV_GOTTLSDESCLO BFD_RELOC_FRV_TLSMOFF12 BFD_RELOC_FRV_TLSMOFFHI BFD_RELOC_FRV_TLSMOFFLO BFD_RELOC_FRV_GOTTLSOFF12 BFD_RELOC_FRV_GOTTLSOFFHI BFD_RELOC_FRV_GOTTLSOFFLO BFD_RELOC_FRV_TLSOFF BFD_RELOC_FRV_TLSDESC_RELAX BFD_RELOC_FRV_GETTLSOFF_RELAX BFD_RELOC_FRV_TLSOFF_RELAX BFD_RELOC_FRV_TLSMOFF BFD_RELOC_MN10300_GOTOFF24 BFD_RELOC_MN10300_GOT32 BFD_RELOC_MN10300_GOT24 BFD_RELOC_MN10300_GOT16 BFD_RELOC_MN10300_COPY BFD_RELOC_MN10300_GLOB_DAT BFD_RELOC_MN10300_JMP_SLOT BFD_RELOC_MN10300_RELATIVE BFD_RELOC_MN10300_SYM_DIFF BFD_RELOC_MN10300_ALIGN BFD_RELOC_386_GOT32 BFD_RELOC_386_PLT32 BFD_RELOC_386_COPY BFD_RELOC_386_GLOB_DAT BFD_RELOC_386_JUMP_SLOT BFD_RELOC_386_RELATIVE BFD_RELOC_386_GOTOFF BFD_RELOC_386_GOTPC BFD_RELOC_386_TLS_TPOFF BFD_RELOC_386_TLS_IE BFD_RELOC_386_TLS_GOTIE BFD_RELOC_386_TLS_LE BFD_RELOC_386_TLS_GD BFD_RELOC_386_TLS_LDM BFD_RELOC_386_TLS_LDO_32 BFD_RELOC_386_TLS_IE_32 BFD_RELOC_386_TLS_LE_32 BFD_RELOC_386_TLS_DTPMOD32 BFD_RELOC_386_TLS_DTPOFF32 BFD_RELOC_386_TLS_TPOFF32 BFD_RELOC_386_TLS_GOTDESC BFD_RELOC_386_TLS_DESC_CALL BFD_RELOC_386_TLS_DESC BFD_RELOC_X86_64_GOT32 BFD_RELOC_X86_64_PLT32 BFD_RELOC_X86_64_COPY BFD_RELOC_X86_64_GLOB_DAT BFD_RELOC_X86_64_JUMP_SLOT BFD_RELOC_X86_64_RELATIVE BFD_RELOC_X86_64_GOTPCREL BFD_RELOC_X86_64_32S BFD_RELOC_X86_64_DTPMOD64 BFD_RELOC_X86_64_DTPOFF64 BFD_RELOC_X86_64_TPOFF64 BFD_RELOC_X86_64_TLSGD BFD_RELOC_X86_64_TLSLD BFD_RELOC_X86_64_DTPOFF32 BFD_RELOC_X86_64_GOTTPOFF BFD_RELOC_X86_64_TPOFF32 BFD_RELOC_X86_64_GOTOFF64 BFD_RELOC_X86_64_GOTPC32 BFD_RELOC_X86_64_GOT64 BFD_RELOC_X86_64_GOTPCREL64 BFD_RELOC_X86_64_GOTPC64 BFD_RELOC_X86_64_GOTPLT64 BFD_RELOC_X86_64_PLTOFF64 BFD_RELOC_X86_64_TLSDESC_CALL BFD_RELOC_X86_64_TLSDESC BFD_RELOC_NS32K_IMM_8 BFD_RELOC_NS32K_IMM_16 BFD_RELOC_NS32K_IMM_32 BFD_RELOC_NS32K_IMM_8_PCREL BFD_RELOC_NS32K_IMM_16_PCREL BFD_RELOC_NS32K_IMM_32_PCREL BFD_RELOC_NS32K_DISP_8 BFD_RELOC_NS32K_DISP_16 BFD_RELOC_NS32K_DISP_32 BFD_RELOC_NS32K_DISP_8_PCREL BFD_RELOC_NS32K_DISP_16_PCREL BFD_RELOC_NS32K_DISP_32_PCREL BFD_RELOC_PDP11_DISP_8_PCREL BFD_RELOC_PDP11_DISP_6_PCREL BFD_RELOC_PJ_CODE_HI16 BFD_RELOC_PJ_CODE_LO16 BFD_RELOC_PJ_CODE_DIR16 BFD_RELOC_PJ_CODE_DIR32 BFD_RELOC_PJ_CODE_REL16 BFD_RELOC_PJ_CODE_REL32 BFD_RELOC_PPC_B26 BFD_RELOC_PPC_BA26 BFD_RELOC_PPC_TOC16 BFD_RELOC_PPC_B16 BFD_RELOC_PPC_B16_BRTAKEN BFD_RELOC_PPC_B16_BRNTAKEN BFD_RELOC_PPC_BA16 BFD_RELOC_PPC_BA16_BRTAKEN BFD_RELOC_PPC_BA16_BRNTAKEN BFD_RELOC_PPC_COPY BFD_RELOC_PPC_GLOB_DAT BFD_RELOC_PPC_JMP_SLOT BFD_RELOC_PPC_RELATIVE BFD_RELOC_PPC_LOCAL24PC BFD_RELOC_PPC_EMB_NADDR32 BFD_RELOC_PPC_EMB_NADDR16 BFD_RELOC_PPC_EMB_NADDR16_LO BFD_RELOC_PPC_EMB_NADDR16_HI BFD_RELOC_PPC_EMB_NADDR16_HA BFD_RELOC_PPC_EMB_SDAI16 BFD_RELOC_PPC_EMB_SDA2I16 BFD_RELOC_PPC_EMB_SDA2REL BFD_RELOC_PPC_EMB_SDA21 BFD_RELOC_PPC_EMB_MRKREF BFD_RELOC_PPC_EMB_RELSEC16 BFD_RELOC_PPC_EMB_RELST_LO BFD_RELOC_PPC_EMB_RELST_HI BFD_RELOC_PPC_EMB_RELST_HA BFD_RELOC_PPC_EMB_BIT_FLD BFD_RELOC_PPC_EMB_RELSDA BFD_RELOC_PPC64_HIGHER BFD_RELOC_PPC64_HIGHER_S BFD_RELOC_PPC64_HIGHEST BFD_RELOC_PPC64_HIGHEST_S BFD_RELOC_PPC64_TOC16_LO BFD_RELOC_PPC64_TOC16_HI BFD_RELOC_PPC64_TOC16_HA BFD_RELOC_PPC64_TOC BFD_RELOC_PPC64_PLTGOT16 BFD_RELOC_PPC64_PLTGOT16_LO BFD_RELOC_PPC64_PLTGOT16_HI BFD_RELOC_PPC64_PLTGOT16_HA BFD_RELOC_PPC64_ADDR16_DS BFD_RELOC_PPC64_ADDR16_LO_DS BFD_RELOC_PPC64_GOT16_DS BFD_RELOC_PPC64_GOT16_LO_DS BFD_RELOC_PPC64_PLT16_LO_DS BFD_RELOC_PPC64_SECTOFF_DS BFD_RELOC_PPC64_SECTOFF_LO_DS BFD_RELOC_PPC64_TOC16_DS BFD_RELOC_PPC64_TOC16_LO_DS BFD_RELOC_PPC64_PLTGOT16_DS BFD_RELOC_PPC_TLS BFD_RELOC_PPC_DTPMOD BFD_RELOC_PPC_TPREL16 BFD_RELOC_PPC_TPREL16_LO BFD_RELOC_PPC_TPREL16_HI BFD_RELOC_PPC_TPREL16_HA BFD_RELOC_PPC_TPREL BFD_RELOC_PPC_DTPREL16 BFD_RELOC_PPC_DTPREL16_LO BFD_RELOC_PPC_DTPREL16_HI BFD_RELOC_PPC_DTPREL16_HA BFD_RELOC_PPC_DTPREL BFD_RELOC_PPC_GOT_TLSGD16 BFD_RELOC_PPC_GOT_TLSGD16_LO BFD_RELOC_PPC_GOT_TLSGD16_HI BFD_RELOC_PPC_GOT_TLSGD16_HA BFD_RELOC_PPC_GOT_TLSLD16 BFD_RELOC_PPC_GOT_TLSLD16_LO BFD_RELOC_PPC_GOT_TLSLD16_HI BFD_RELOC_PPC_GOT_TLSLD16_HA BFD_RELOC_PPC_GOT_TPREL16 BFD_RELOC_PPC_GOT_TPREL16_LO BFD_RELOC_PPC_GOT_TPREL16_HI BFD_RELOC_PPC_GOT_TPREL16_HA BFD_RELOC_PPC_GOT_DTPREL16 BFD_RELOC_PPC_GOT_DTPREL16_LO BFD_RELOC_PPC_GOT_DTPREL16_HI BFD_RELOC_PPC_GOT_DTPREL16_HA BFD_RELOC_PPC64_TPREL16_DS BFD_RELOC_PPC64_TPREL16_LO_DS BFD_RELOC_PPC64_DTPREL16_DS BFD_RELOC_I370_D12 BFD_RELOC_CTOR BFD_RELOC_ARM_PCREL_BRANCH BFD_RELOC_ARM_PCREL_BLX BFD_RELOC_THUMB_PCREL_BLX BFD_RELOC_ARM_PCREL_CALL BFD_RELOC_ARM_PCREL_JUMP BFD_RELOC_THUMB_PCREL_BRANCH7 BFD_RELOC_THUMB_PCREL_BRANCH9 BFD_RELOC_ARM_OFFSET_IMM BFD_RELOC_ARM_THUMB_OFFSET BFD_RELOC_ARM_TARGET1 BFD_RELOC_ARM_ROSEGREL32 BFD_RELOC_ARM_SBREL32 BFD_RELOC_ARM_TARGET2 BFD_RELOC_ARM_PREL31 BFD_RELOC_ARM_MOVW BFD_RELOC_ARM_MOVT BFD_RELOC_ARM_MOVW_PCREL BFD_RELOC_ARM_MOVT_PCREL BFD_RELOC_ARM_THUMB_MOVW BFD_RELOC_ARM_THUMB_MOVT BFD_RELOC_ARM_JUMP_SLOT BFD_RELOC_ARM_GLOB_DAT BFD_RELOC_ARM_GOT32 BFD_RELOC_ARM_PLT32 BFD_RELOC_ARM_RELATIVE BFD_RELOC_ARM_GOTOFF BFD_RELOC_ARM_GOTPC BFD_RELOC_ARM_TLS_GD32 BFD_RELOC_ARM_TLS_LDO32 BFD_RELOC_ARM_TLS_LDM32 BFD_RELOC_ARM_TLS_DTPOFF32 BFD_RELOC_ARM_TLS_DTPMOD32 BFD_RELOC_ARM_TLS_TPOFF32 BFD_RELOC_ARM_TLS_IE32 BFD_RELOC_ARM_TLS_LE32 BFD_RELOC_ARM_ALU_PC_G0_NC BFD_RELOC_ARM_ALU_PC_G0 BFD_RELOC_ARM_ALU_PC_G1_NC BFD_RELOC_ARM_ALU_PC_G1 BFD_RELOC_ARM_ALU_PC_G2 BFD_RELOC_ARM_LDR_PC_G0 BFD_RELOC_ARM_LDR_PC_G1 BFD_RELOC_ARM_LDR_PC_G2 BFD_RELOC_ARM_LDRS_PC_G0 BFD_RELOC_ARM_LDRS_PC_G1 BFD_RELOC_ARM_LDRS_PC_G2 BFD_RELOC_ARM_LDC_PC_G0 BFD_RELOC_ARM_LDC_PC_G1 BFD_RELOC_ARM_LDC_PC_G2 BFD_RELOC_ARM_ALU_SB_G0_NC BFD_RELOC_ARM_ALU_SB_G0 BFD_RELOC_ARM_ALU_SB_G1_NC BFD_RELOC_ARM_ALU_SB_G1 BFD_RELOC_ARM_ALU_SB_G2 BFD_RELOC_ARM_LDR_SB_G0 BFD_RELOC_ARM_LDR_SB_G1 BFD_RELOC_ARM_LDR_SB_G2 BFD_RELOC_ARM_LDRS_SB_G0 BFD_RELOC_ARM_LDRS_SB_G1 BFD_RELOC_ARM_LDRS_SB_G2 BFD_RELOC_ARM_LDC_SB_G0 BFD_RELOC_ARM_LDC_SB_G1 BFD_RELOC_ARM_LDC_SB_G2 BFD_RELOC_ARM_V4BX BFD_RELOC_ARM_IMMEDIATE BFD_RELOC_ARM_ADRL_IMMEDIATE BFD_RELOC_ARM_T32_IMMEDIATE BFD_RELOC_ARM_T32_ADD_IMM BFD_RELOC_ARM_T32_IMM12 BFD_RELOC_ARM_T32_ADD_PC12 BFD_RELOC_ARM_SHIFT_IMM BFD_RELOC_ARM_SMC BFD_RELOC_ARM_SWI BFD_RELOC_ARM_MULTI BFD_RELOC_ARM_CP_OFF_IMM BFD_RELOC_ARM_CP_OFF_IMM_S2 BFD_RELOC_ARM_T32_CP_OFF_IMM BFD_RELOC_ARM_ADR_IMM BFD_RELOC_ARM_LDR_IMM BFD_RELOC_ARM_LITERAL BFD_RELOC_ARM_IN_POOL BFD_RELOC_ARM_OFFSET_IMM8 BFD_RELOC_ARM_T32_OFFSET_U8 BFD_RELOC_ARM_T32_OFFSET_IMM BFD_RELOC_ARM_HWLITERAL BFD_RELOC_ARM_THUMB_ADD BFD_RELOC_ARM_THUMB_IMM BFD_RELOC_ARM_THUMB_SHIFT BFD_RELOC_SH_PCDISP8BY2 BFD_RELOC_SH_PCDISP12BY2 BFD_RELOC_SH_IMM3 BFD_RELOC_SH_IMM3U BFD_RELOC_SH_DISP12 BFD_RELOC_SH_DISP12BY2 BFD_RELOC_SH_DISP12BY4 BFD_RELOC_SH_DISP12BY8 BFD_RELOC_SH_DISP20 BFD_RELOC_SH_DISP20BY8 BFD_RELOC_SH_IMM4 BFD_RELOC_SH_IMM4BY2 BFD_RELOC_SH_IMM4BY4 BFD_RELOC_SH_IMM8 BFD_RELOC_SH_IMM8BY2 BFD_RELOC_SH_IMM8BY4 BFD_RELOC_SH_PCRELIMM8BY2 BFD_RELOC_SH_PCRELIMM8BY4 BFD_RELOC_SH_SWITCH16 BFD_RELOC_SH_SWITCH32 BFD_RELOC_SH_USES BFD_RELOC_SH_COUNT BFD_RELOC_SH_ALIGN BFD_RELOC_SH_CODE BFD_RELOC_SH_DATA BFD_RELOC_SH_LABEL BFD_RELOC_SH_LOOP_START BFD_RELOC_SH_LOOP_END BFD_RELOC_SH_COPY BFD_RELOC_SH_GLOB_DAT BFD_RELOC_SH_JMP_SLOT BFD_RELOC_SH_RELATIVE BFD_RELOC_SH_GOTPC BFD_RELOC_SH_GOT_LOW16 BFD_RELOC_SH_GOT_MEDLOW16 BFD_RELOC_SH_GOT_MEDHI16 BFD_RELOC_SH_GOT_HI16 BFD_RELOC_SH_GOTPLT_LOW16 BFD_RELOC_SH_GOTPLT_MEDLOW16 BFD_RELOC_SH_GOTPLT_MEDHI16 BFD_RELOC_SH_GOTPLT_HI16 BFD_RELOC_SH_PLT_LOW16 BFD_RELOC_SH_PLT_MEDLOW16 BFD_RELOC_SH_PLT_MEDHI16 BFD_RELOC_SH_PLT_HI16 BFD_RELOC_SH_GOTOFF_LOW16 BFD_RELOC_SH_GOTOFF_MEDLOW16 BFD_RELOC_SH_GOTOFF_MEDHI16 BFD_RELOC_SH_GOTOFF_HI16 BFD_RELOC_SH_GOTPC_LOW16 BFD_RELOC_SH_GOTPC_MEDLOW16 BFD_RELOC_SH_GOTPC_MEDHI16 BFD_RELOC_SH_GOTPC_HI16 BFD_RELOC_SH_COPY64 BFD_RELOC_SH_GLOB_DAT64 BFD_RELOC_SH_JMP_SLOT64 BFD_RELOC_SH_RELATIVE64 BFD_RELOC_SH_GOT10BY4 BFD_RELOC_SH_GOT10BY8 BFD_RELOC_SH_GOTPLT10BY4 BFD_RELOC_SH_GOTPLT10BY8 BFD_RELOC_SH_GOTPLT32 BFD_RELOC_SH_SHMEDIA_CODE BFD_RELOC_SH_IMMU5 BFD_RELOC_SH_IMMS6 BFD_RELOC_SH_IMMS6BY32 BFD_RELOC_SH_IMMU6 BFD_RELOC_SH_IMMS10 BFD_RELOC_SH_IMMS10BY2 BFD_RELOC_SH_IMMS10BY4 BFD_RELOC_SH_IMMS10BY8 BFD_RELOC_SH_IMMS16 BFD_RELOC_SH_IMMU16 BFD_RELOC_SH_IMM_LOW16 BFD_RELOC_SH_IMM_LOW16_PCREL BFD_RELOC_SH_IMM_MEDLOW16 BFD_RELOC_SH_IMM_MEDHI16 BFD_RELOC_SH_IMM_HI16 BFD_RELOC_SH_IMM_HI16_PCREL BFD_RELOC_SH_PT_16 BFD_RELOC_SH_TLS_GD_32 BFD_RELOC_SH_TLS_LD_32 BFD_RELOC_SH_TLS_LDO_32 BFD_RELOC_SH_TLS_IE_32 BFD_RELOC_SH_TLS_LE_32 BFD_RELOC_SH_TLS_DTPMOD32 BFD_RELOC_SH_TLS_DTPOFF32 BFD_RELOC_SH_TLS_TPOFF32 BFD_RELOC_ARC_B22_PCREL BFD_RELOC_ARC_B26 BFD_RELOC_BFIN_16_IMM BFD_RELOC_BFIN_16_HIGH BFD_RELOC_BFIN_4_PCREL BFD_RELOC_BFIN_5_PCREL BFD_RELOC_BFIN_16_LOW BFD_RELOC_BFIN_10_PCREL BFD_RELOC_BFIN_11_PCREL BFD_RELOC_BFIN_12_PCREL_JUMP BFD_RELOC_BFIN_GOT17M4 BFD_RELOC_BFIN_GOTHI BFD_RELOC_BFIN_GOTLO BFD_RELOC_BFIN_FUNCDESC BFD_RELOC_BFIN_FUNCDESC_GOTHI BFD_RELOC_BFIN_FUNCDESC_GOTLO BFD_RELOC_BFIN_FUNCDESC_VALUE BFD_RELOC_BFIN_GOTOFF17M4 BFD_RELOC_BFIN_GOTOFFHI BFD_RELOC_BFIN_GOTOFFLO BFD_RELOC_BFIN_GOT BFD_RELOC_BFIN_PLTPC BFD_ARELOC_BFIN_PUSH BFD_ARELOC_BFIN_CONST BFD_ARELOC_BFIN_ADD BFD_ARELOC_BFIN_SUB BFD_ARELOC_BFIN_MULT BFD_ARELOC_BFIN_DIV BFD_ARELOC_BFIN_MOD BFD_ARELOC_BFIN_LSHIFT BFD_ARELOC_BFIN_RSHIFT BFD_ARELOC_BFIN_AND BFD_ARELOC_BFIN_OR BFD_ARELOC_BFIN_XOR BFD_ARELOC_BFIN_LAND BFD_ARELOC_BFIN_LOR BFD_ARELOC_BFIN_LEN BFD_ARELOC_BFIN_NEG BFD_ARELOC_BFIN_COMP BFD_ARELOC_BFIN_PAGE BFD_ARELOC_BFIN_HWPAGE BFD_ARELOC_BFIN_ADDR BFD_RELOC_D10V_10_PCREL_R BFD_RELOC_D10V_10_PCREL_L BFD_RELOC_D10V_18 BFD_RELOC_D10V_18_PCREL BFD_RELOC_D30V_6 BFD_RELOC_D30V_9_PCREL BFD_RELOC_D30V_9_PCREL_R BFD_RELOC_D30V_15 BFD_RELOC_D30V_15_PCREL BFD_RELOC_D30V_15_PCREL_R BFD_RELOC_D30V_21 BFD_RELOC_D30V_21_PCREL BFD_RELOC_D30V_21_PCREL_R BFD_RELOC_D30V_32 BFD_RELOC_D30V_32_PCREL BFD_RELOC_DLX_HI16_S BFD_RELOC_DLX_LO16 BFD_RELOC_DLX_JMP26 BFD_RELOC_M32C_HI8 BFD_RELOC_M32C_RL_JUMP BFD_RELOC_M32C_RL_1ADDR BFD_RELOC_M32C_RL_2ADDR BFD_RELOC_M32R_24 BFD_RELOC_M32R_10_PCREL BFD_RELOC_M32R_18_PCREL BFD_RELOC_M32R_26_PCREL BFD_RELOC_M32R_HI16_ULO BFD_RELOC_M32R_HI16_SLO BFD_RELOC_M32R_LO16 BFD_RELOC_M32R_SDA16 BFD_RELOC_M32R_GOT24 BFD_RELOC_M32R_26_PLTREL BFD_RELOC_M32R_COPY BFD_RELOC_M32R_GLOB_DAT BFD_RELOC_M32R_JMP_SLOT BFD_RELOC_M32R_RELATIVE BFD_RELOC_M32R_GOTOFF BFD_RELOC_M32R_GOTOFF_HI_ULO BFD_RELOC_M32R_GOTOFF_HI_SLO BFD_RELOC_M32R_GOTOFF_LO BFD_RELOC_M32R_GOTPC24 BFD_RELOC_M32R_GOT16_HI_ULO BFD_RELOC_M32R_GOT16_HI_SLO BFD_RELOC_M32R_GOT16_LO BFD_RELOC_M32R_GOTPC_HI_ULO BFD_RELOC_M32R_GOTPC_HI_SLO BFD_RELOC_M32R_GOTPC_LO BFD_RELOC_V850_9_PCREL BFD_RELOC_V850_22_PCREL BFD_RELOC_V850_TDA_6_8_OFFSET BFD_RELOC_V850_TDA_7_8_OFFSET BFD_RELOC_V850_TDA_7_7_OFFSET BFD_RELOC_V850_TDA_4_5_OFFSET BFD_RELOC_V850_TDA_4_4_OFFSET BFD_RELOC_V850_LONGCALL BFD_RELOC_V850_LONGJUMP BFD_RELOC_V850_ALIGN BFD_RELOC_MN10300_32_PCREL BFD_RELOC_MN10300_16_PCREL BFD_RELOC_TIC30_LDP BFD_RELOC_TIC54X_PARTLS7 BFD_RELOC_TIC54X_PARTMS9 BFD_RELOC_TIC54X_23 BFD_RELOC_TIC54X_16_OF_23 BFD_RELOC_TIC54X_MS7_OF_23 BFD_RELOC_FR30_48 BFD_RELOC_FR30_20 BFD_RELOC_FR30_6_IN_4 BFD_RELOC_FR30_8_IN_8 BFD_RELOC_FR30_9_IN_8 BFD_RELOC_FR30_10_IN_8 BFD_RELOC_FR30_9_PCREL BFD_RELOC_FR30_12_PCREL BFD_RELOC_MCORE_PCREL_IMM8BY4 BFD_RELOC_MCORE_PCREL_IMM4BY2 BFD_RELOC_MCORE_PCREL_32 BFD_RELOC_MCORE_RVA BFD_RELOC_MEP_8 BFD_RELOC_MEP_16 BFD_RELOC_MEP_32 BFD_RELOC_MEP_PCREL8A2 BFD_RELOC_MEP_PCREL12A2 BFD_RELOC_MEP_PCREL17A2 BFD_RELOC_MEP_PCREL24A2 BFD_RELOC_MEP_PCABS24A2 BFD_RELOC_MEP_LOW16 BFD_RELOC_MEP_HI16U BFD_RELOC_MEP_HI16S BFD_RELOC_MEP_GPREL BFD_RELOC_MEP_TPREL BFD_RELOC_MEP_TPREL7 BFD_RELOC_MEP_TPREL7A2 BFD_RELOC_MEP_TPREL7A4 BFD_RELOC_MEP_UIMM24 BFD_RELOC_MEP_ADDR24A4 BFD_RELOC_MEP_GNU_VTINHERIT BFD_RELOC_MEP_GNU_VTENTRY BFD_RELOC_MMIX_GETA BFD_RELOC_MMIX_GETA_1 BFD_RELOC_MMIX_GETA_2 BFD_RELOC_MMIX_GETA_3 BFD_RELOC_MMIX_CBRANCH BFD_RELOC_MMIX_CBRANCH_J BFD_RELOC_MMIX_CBRANCH_1 BFD_RELOC_MMIX_CBRANCH_2 BFD_RELOC_MMIX_CBRANCH_3 BFD_RELOC_MMIX_PUSHJ BFD_RELOC_MMIX_PUSHJ_1 BFD_RELOC_MMIX_PUSHJ_2 BFD_RELOC_MMIX_PUSHJ_3 BFD_RELOC_MMIX_JMP BFD_RELOC_MMIX_JMP_1 BFD_RELOC_MMIX_JMP_2 BFD_RELOC_MMIX_JMP_3 BFD_RELOC_MMIX_ADDR19 BFD_RELOC_MMIX_ADDR27 BFD_RELOC_MMIX_REG_OR_BYTE BFD_RELOC_MMIX_REG BFD_RELOC_MMIX_LOCAL BFD_RELOC_AVR_7_PCREL BFD_RELOC_AVR_13_PCREL BFD_RELOC_AVR_16_PM BFD_RELOC_AVR_LO8_LDI BFD_RELOC_AVR_HI8_LDI BFD_RELOC_AVR_HH8_LDI BFD_RELOC_AVR_MS8_LDI BFD_RELOC_AVR_LO8_LDI_NEG BFD_RELOC_AVR_HI8_LDI_NEG BFD_RELOC_AVR_HH8_LDI_NEG BFD_RELOC_AVR_MS8_LDI_NEG BFD_RELOC_AVR_LO8_LDI_PM BFD_RELOC_AVR_LO8_LDI_GS BFD_RELOC_AVR_HI8_LDI_PM BFD_RELOC_AVR_HI8_LDI_GS BFD_RELOC_AVR_HH8_LDI_PM BFD_RELOC_AVR_LO8_LDI_PM_NEG BFD_RELOC_AVR_HI8_LDI_PM_NEG BFD_RELOC_AVR_HH8_LDI_PM_NEG BFD_RELOC_AVR_CALL BFD_RELOC_AVR_LDI BFD_RELOC_AVR_6 BFD_RELOC_AVR_6_ADIW BFD_RELOC_390_12 BFD_RELOC_390_GOT12 BFD_RELOC_390_PLT32 BFD_RELOC_390_COPY BFD_RELOC_390_GLOB_DAT BFD_RELOC_390_JMP_SLOT BFD_RELOC_390_RELATIVE BFD_RELOC_390_GOTPC BFD_RELOC_390_GOT16 BFD_RELOC_390_PC16DBL BFD_RELOC_390_PLT16DBL BFD_RELOC_390_PC32DBL BFD_RELOC_390_PLT32DBL BFD_RELOC_390_GOTPCDBL BFD_RELOC_390_GOT64 BFD_RELOC_390_PLT64 BFD_RELOC_390_GOTENT BFD_RELOC_390_GOTOFF64 BFD_RELOC_390_GOTPLT12 BFD_RELOC_390_GOTPLT16 BFD_RELOC_390_GOTPLT32 BFD_RELOC_390_GOTPLT64 BFD_RELOC_390_GOTPLTENT BFD_RELOC_390_PLTOFF16 BFD_RELOC_390_PLTOFF32 BFD_RELOC_390_PLTOFF64 BFD_RELOC_390_TLS_LOAD BFD_RELOC_390_TLS_GDCALL BFD_RELOC_390_TLS_LDCALL BFD_RELOC_390_TLS_GD32 BFD_RELOC_390_TLS_GD64 BFD_RELOC_390_TLS_GOTIE12 BFD_RELOC_390_TLS_GOTIE32 BFD_RELOC_390_TLS_GOTIE64 BFD_RELOC_390_TLS_LDM32 BFD_RELOC_390_TLS_LDM64 BFD_RELOC_390_TLS_IE32 BFD_RELOC_390_TLS_IE64 BFD_RELOC_390_TLS_IEENT BFD_RELOC_390_TLS_LE32 BFD_RELOC_390_TLS_LE64 BFD_RELOC_390_TLS_LDO32 BFD_RELOC_390_TLS_LDO64 BFD_RELOC_390_TLS_DTPMOD BFD_RELOC_390_TLS_DTPOFF BFD_RELOC_390_TLS_TPOFF BFD_RELOC_390_20 BFD_RELOC_390_GOT20 BFD_RELOC_390_GOTPLT20 BFD_RELOC_390_TLS_GOTIE20 BFD_RELOC_SCORE_DUMMY1 BFD_RELOC_SCORE_GPREL15 BFD_RELOC_SCORE_DUMMY2 BFD_RELOC_SCORE_JMP BFD_RELOC_SCORE_BRANCH BFD_RELOC_SCORE16_JMP BFD_RELOC_SCORE16_BRANCH BFD_RELOC_SCORE_GOT15 BFD_RELOC_SCORE_GOT_LO16 BFD_RELOC_SCORE_CALL15 BFD_RELOC_SCORE_DUMMY_HI16 BFD_RELOC_IP2K_FR9 BFD_RELOC_IP2K_BANK BFD_RELOC_IP2K_ADDR16CJP BFD_RELOC_IP2K_PAGE3 BFD_RELOC_IP2K_LO8DATA BFD_RELOC_IP2K_HI8DATA BFD_RELOC_IP2K_EX8DATA BFD_RELOC_IP2K_LO8INSN BFD_RELOC_IP2K_HI8INSN BFD_RELOC_IP2K_PC_SKIP BFD_RELOC_IP2K_TEXT BFD_RELOC_IP2K_FR_OFFSET BFD_RELOC_VPE4KMATH_DATA BFD_RELOC_VPE4KMATH_INSN BFD_RELOC_VTABLE_INHERIT BFD_RELOC_VTABLE_ENTRY BFD_RELOC_IA64_IMM14 BFD_RELOC_IA64_IMM22 BFD_RELOC_IA64_IMM64 BFD_RELOC_IA64_DIR32MSB BFD_RELOC_IA64_DIR32LSB BFD_RELOC_IA64_DIR64MSB BFD_RELOC_IA64_DIR64LSB BFD_RELOC_IA64_GPREL22 BFD_RELOC_IA64_GPREL64I BFD_RELOC_IA64_GPREL32MSB BFD_RELOC_IA64_GPREL32LSB BFD_RELOC_IA64_GPREL64MSB BFD_RELOC_IA64_GPREL64LSB BFD_RELOC_IA64_LTOFF22 BFD_RELOC_IA64_LTOFF64I BFD_RELOC_IA64_PLTOFF22 BFD_RELOC_IA64_PLTOFF64I BFD_RELOC_IA64_PLTOFF64MSB BFD_RELOC_IA64_PLTOFF64LSB BFD_RELOC_IA64_FPTR64I BFD_RELOC_IA64_FPTR32MSB BFD_RELOC_IA64_FPTR32LSB BFD_RELOC_IA64_FPTR64MSB BFD_RELOC_IA64_FPTR64LSB BFD_RELOC_IA64_PCREL21B BFD_RELOC_IA64_PCREL21BI BFD_RELOC_IA64_PCREL21M BFD_RELOC_IA64_PCREL21F BFD_RELOC_IA64_PCREL22 BFD_RELOC_IA64_PCREL60B BFD_RELOC_IA64_PCREL64I BFD_RELOC_IA64_PCREL32MSB BFD_RELOC_IA64_PCREL32LSB BFD_RELOC_IA64_PCREL64MSB BFD_RELOC_IA64_PCREL64LSB BFD_RELOC_IA64_LTOFF_FPTR22 BFD_RELOC_IA64_LTOFF_FPTR64I BFD_RELOC_IA64_SEGREL32MSB BFD_RELOC_IA64_SEGREL32LSB BFD_RELOC_IA64_SEGREL64MSB BFD_RELOC_IA64_SEGREL64LSB BFD_RELOC_IA64_SECREL32MSB BFD_RELOC_IA64_SECREL32LSB BFD_RELOC_IA64_SECREL64MSB BFD_RELOC_IA64_SECREL64LSB BFD_RELOC_IA64_REL32MSB BFD_RELOC_IA64_REL32LSB BFD_RELOC_IA64_REL64MSB BFD_RELOC_IA64_REL64LSB BFD_RELOC_IA64_LTV32MSB BFD_RELOC_IA64_LTV32LSB BFD_RELOC_IA64_LTV64MSB BFD_RELOC_IA64_LTV64LSB BFD_RELOC_IA64_IPLTMSB BFD_RELOC_IA64_IPLTLSB BFD_RELOC_IA64_COPY BFD_RELOC_IA64_LTOFF22X BFD_RELOC_IA64_LDXMOV BFD_RELOC_IA64_TPREL14 BFD_RELOC_IA64_TPREL22 BFD_RELOC_IA64_TPREL64I BFD_RELOC_IA64_TPREL64MSB BFD_RELOC_IA64_TPREL64LSB BFD_RELOC_IA64_LTOFF_TPREL22 BFD_RELOC_IA64_DTPMOD64MSB BFD_RELOC_IA64_DTPMOD64LSB BFD_RELOC_IA64_LTOFF_DTPMOD22 BFD_RELOC_IA64_DTPREL14 BFD_RELOC_IA64_DTPREL22 BFD_RELOC_IA64_DTPREL64I BFD_RELOC_IA64_DTPREL32MSB BFD_RELOC_IA64_DTPREL32LSB BFD_RELOC_IA64_DTPREL64MSB BFD_RELOC_IA64_DTPREL64LSB BFD_RELOC_IA64_LTOFF_DTPREL22 BFD_RELOC_M68HC11_HI8 BFD_RELOC_M68HC11_LO8 BFD_RELOC_M68HC11_3B BFD_RELOC_M68HC11_RL_JUMP BFD_RELOC_M68HC11_RL_GROUP BFD_RELOC_M68HC11_LO16 BFD_RELOC_M68HC11_PAGE BFD_RELOC_M68HC11_24 BFD_RELOC_M68HC12_5B BFD_RELOC_16C_NUM08 BFD_RELOC_16C_NUM08_C BFD_RELOC_16C_NUM16 BFD_RELOC_16C_NUM16_C BFD_RELOC_16C_NUM32 BFD_RELOC_16C_NUM32_C BFD_RELOC_16C_DISP04 BFD_RELOC_16C_DISP04_C BFD_RELOC_16C_DISP08 BFD_RELOC_16C_DISP08_C BFD_RELOC_16C_DISP16 BFD_RELOC_16C_DISP16_C BFD_RELOC_16C_DISP24 BFD_RELOC_16C_DISP24_C BFD_RELOC_16C_DISP24a BFD_RELOC_16C_DISP24a_C BFD_RELOC_16C_REG04 BFD_RELOC_16C_REG04_C BFD_RELOC_16C_REG04a BFD_RELOC_16C_REG04a_C BFD_RELOC_16C_REG14 BFD_RELOC_16C_REG14_C BFD_RELOC_16C_REG16 BFD_RELOC_16C_REG16_C BFD_RELOC_16C_REG20 BFD_RELOC_16C_REG20_C BFD_RELOC_16C_ABS20 BFD_RELOC_16C_ABS20_C BFD_RELOC_16C_ABS24 BFD_RELOC_16C_ABS24_C BFD_RELOC_16C_IMM04 BFD_RELOC_16C_IMM04_C BFD_RELOC_16C_IMM16 BFD_RELOC_16C_IMM16_C BFD_RELOC_16C_IMM20 BFD_RELOC_16C_IMM20_C BFD_RELOC_16C_IMM24 BFD_RELOC_16C_IMM24_C BFD_RELOC_16C_IMM32 BFD_RELOC_16C_IMM32_C BFD_RELOC_CR16_NUM8 BFD_RELOC_CR16_NUM16 BFD_RELOC_CR16_NUM32 BFD_RELOC_CR16_NUM32a BFD_RELOC_CR16_REGREL0 BFD_RELOC_CR16_REGREL4 BFD_RELOC_CR16_REGREL4a BFD_RELOC_CR16_REGREL14 BFD_RELOC_CR16_REGREL14a BFD_RELOC_CR16_REGREL16 BFD_RELOC_CR16_REGREL20 BFD_RELOC_CR16_REGREL20a BFD_RELOC_CR16_ABS20 BFD_RELOC_CR16_ABS24 BFD_RELOC_CR16_IMM4 BFD_RELOC_CR16_IMM8 BFD_RELOC_CR16_IMM16 BFD_RELOC_CR16_IMM20 BFD_RELOC_CR16_IMM24 BFD_RELOC_CR16_IMM32 BFD_RELOC_CR16_IMM32a BFD_RELOC_CR16_DISP4 BFD_RELOC_CR16_DISP8 BFD_RELOC_CR16_DISP16 BFD_RELOC_CR16_DISP20 BFD_RELOC_CR16_DISP24 BFD_RELOC_CR16_DISP24a BFD_RELOC_CR16_SWITCH8 BFD_RELOC_CR16_SWITCH16 BFD_RELOC_CR16_SWITCH32 BFD_RELOC_CRX_REL4 BFD_RELOC_CRX_REL8 BFD_RELOC_CRX_REL8_CMP BFD_RELOC_CRX_REL16 BFD_RELOC_CRX_REL24 BFD_RELOC_CRX_REL32 BFD_RELOC_CRX_REGREL12 BFD_RELOC_CRX_REGREL22 BFD_RELOC_CRX_REGREL28 BFD_RELOC_CRX_REGREL32 BFD_RELOC_CRX_ABS16 BFD_RELOC_CRX_ABS32 BFD_RELOC_CRX_NUM8 BFD_RELOC_CRX_NUM16 BFD_RELOC_CRX_NUM32 BFD_RELOC_CRX_IMM16 BFD_RELOC_CRX_IMM32 BFD_RELOC_CRX_SWITCH8 BFD_RELOC_CRX_SWITCH16 BFD_RELOC_CRX_SWITCH32 BFD_RELOC_CRIS_BDISP8 BFD_RELOC_CRIS_UNSIGNED_5 BFD_RELOC_CRIS_SIGNED_6 BFD_RELOC_CRIS_UNSIGNED_6 BFD_RELOC_CRIS_SIGNED_8 BFD_RELOC_CRIS_UNSIGNED_8 BFD_RELOC_CRIS_SIGNED_16 BFD_RELOC_CRIS_UNSIGNED_16 BFD_RELOC_CRIS_LAPCQ_OFFSET BFD_RELOC_CRIS_UNSIGNED_4 BFD_RELOC_CRIS_COPY BFD_RELOC_CRIS_GLOB_DAT BFD_RELOC_CRIS_JUMP_SLOT BFD_RELOC_CRIS_RELATIVE BFD_RELOC_CRIS_32_GOT BFD_RELOC_CRIS_16_GOT BFD_RELOC_CRIS_32_GOTPLT BFD_RELOC_CRIS_16_GOTPLT BFD_RELOC_CRIS_32_GOTREL BFD_RELOC_CRIS_32_PLT_GOTREL BFD_RELOC_CRIS_32_PLT_PCREL BFD_RELOC_860_COPY BFD_RELOC_860_GLOB_DAT BFD_RELOC_860_JUMP_SLOT BFD_RELOC_860_RELATIVE BFD_RELOC_860_PC26 BFD_RELOC_860_PLT26 BFD_RELOC_860_PC16 BFD_RELOC_860_LOW0 BFD_RELOC_860_SPLIT0 BFD_RELOC_860_LOW1 BFD_RELOC_860_SPLIT1 BFD_RELOC_860_LOW2 BFD_RELOC_860_SPLIT2 BFD_RELOC_860_LOW3 BFD_RELOC_860_LOGOT0 BFD_RELOC_860_SPGOT0 BFD_RELOC_860_LOGOT1 BFD_RELOC_860_SPGOT1 BFD_RELOC_860_LOGOTOFF0 BFD_RELOC_860_SPGOTOFF0 BFD_RELOC_860_LOGOTOFF1 BFD_RELOC_860_SPGOTOFF1 BFD_RELOC_860_LOGOTOFF2 BFD_RELOC_860_LOGOTOFF3 BFD_RELOC_860_LOPC BFD_RELOC_860_HIGHADJ BFD_RELOC_860_HAGOT BFD_RELOC_860_HAGOTOFF BFD_RELOC_860_HAPC BFD_RELOC_860_HIGH BFD_RELOC_860_HIGOT BFD_RELOC_860_HIGOTOFF BFD_RELOC_OPENRISC_ABS_26 BFD_RELOC_OPENRISC_REL_26 BFD_RELOC_H8_DIR16A8 BFD_RELOC_H8_DIR16R8 BFD_RELOC_H8_DIR24A8 BFD_RELOC_H8_DIR24R8 BFD_RELOC_H8_DIR32A16 BFD_RELOC_XSTORMY16_REL_12 BFD_RELOC_XSTORMY16_12 BFD_RELOC_XSTORMY16_24 BFD_RELOC_XSTORMY16_FPTR16 BFD_RELOC_RELC BFD_RELOC_XC16X_PAG BFD_RELOC_XC16X_POF BFD_RELOC_XC16X_SEG BFD_RELOC_XC16X_SOF BFD_RELOC_VAX_GLOB_DAT BFD_RELOC_VAX_JMP_SLOT BFD_RELOC_VAX_RELATIVE BFD_RELOC_MT_PC16 BFD_RELOC_MT_HI16 BFD_RELOC_MT_LO16 BFD_RELOC_MT_GNU_VTINHERIT BFD_RELOC_MT_GNU_VTENTRY BFD_RELOC_MT_PCINSN8 BFD_RELOC_MSP430_10_PCREL BFD_RELOC_MSP430_16_PCREL BFD_RELOC_MSP430_16 BFD_RELOC_MSP430_16_BYTE BFD_RELOC_MSP430_2X_PCREL BFD_RELOC_MSP430_RL_PCREL BFD_RELOC_IQ2000_OFFSET_16 BFD_RELOC_IQ2000_OFFSET_21 BFD_RELOC_IQ2000_UHI16 BFD_RELOC_XTENSA_RTLD BFD_RELOC_XTENSA_GLOB_DAT BFD_RELOC_XTENSA_JMP_SLOT BFD_RELOC_XTENSA_RELATIVE BFD_RELOC_XTENSA_PLT BFD_RELOC_XTENSA_DIFF8 BFD_RELOC_XTENSA_DIFF16 BFD_RELOC_XTENSA_DIFF32 BFD_RELOC_XTENSA_SLOT0_OP BFD_RELOC_XTENSA_SLOT1_OP BFD_RELOC_XTENSA_SLOT2_OP BFD_RELOC_XTENSA_SLOT3_OP BFD_RELOC_XTENSA_SLOT4_OP BFD_RELOC_XTENSA_SLOT5_OP BFD_RELOC_XTENSA_SLOT6_OP BFD_RELOC_XTENSA_SLOT7_OP BFD_RELOC_XTENSA_SLOT8_OP BFD_RELOC_XTENSA_SLOT9_OP BFD_RELOC_XTENSA_SLOT10_OP BFD_RELOC_XTENSA_SLOT11_OP BFD_RELOC_XTENSA_SLOT12_OP BFD_RELOC_XTENSA_SLOT13_OP BFD_RELOC_XTENSA_SLOT14_OP BFD_RELOC_XTENSA_SLOT0_ALT BFD_RELOC_XTENSA_SLOT1_ALT BFD_RELOC_XTENSA_SLOT2_ALT BFD_RELOC_XTENSA_SLOT3_ALT BFD_RELOC_XTENSA_SLOT4_ALT BFD_RELOC_XTENSA_SLOT5_ALT BFD_RELOC_XTENSA_SLOT6_ALT BFD_RELOC_XTENSA_SLOT7_ALT BFD_RELOC_XTENSA_SLOT8_ALT BFD_RELOC_XTENSA_SLOT9_ALT BFD_RELOC_XTENSA_SLOT10_ALT BFD_RELOC_XTENSA_SLOT11_ALT BFD_RELOC_XTENSA_SLOT12_ALT BFD_RELOC_XTENSA_SLOT13_ALT BFD_RELOC_XTENSA_SLOT14_ALT BFD_RELOC_XTENSA_OP0 BFD_RELOC_XTENSA_OP1 BFD_RELOC_XTENSA_OP2 BFD_RELOC_XTENSA_ASM_EXPAND BFD_RELOC_XTENSA_ASM_SIMPLIFY BFD_RELOC_XTENSA_TLSDESC_FN BFD_RELOC_XTENSA_TLSDESC_ARG BFD_RELOC_XTENSA_TLS_DTPOFF BFD_RELOC_XTENSA_TLS_TPOFF BFD_RELOC_XTENSA_TLS_FUNC BFD_RELOC_XTENSA_TLS_ARG BFD_RELOC_XTENSA_TLS_CALL BFD_RELOC_Z80_DISP8 BFD_RELOC_Z8K_DISP7 BFD_RELOC_Z8K_CALLR BFD_RELOC_Z8K_IMM4L VRT32 coff-Intel-little coff-Intel-big coff-z8k unused BFD_RELOC_SPARC_GOTDATA_OP_HIX22 BFD_RELOC_SPARC_GOTDATA_OP_LOX10 BFD_RELOC_MIPS_TLS_DTPREL_HI16 BFD_RELOC_MIPS_TLS_DTPREL_LO16 BFD_RELOC_FRV_FUNCDESC_GOTOFF12 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI BFD_RELOC_FRV_FUNCDESC_GOTOFFLO BFD_RELOC_X86_64_GOTPC32_TLSDESC BFD_RELOC_PPC64_PLTGOT16_LO_DS BFD_RELOC_PPC64_TPREL16_HIGHER BFD_RELOC_PPC64_TPREL16_HIGHERA BFD_RELOC_PPC64_TPREL16_HIGHEST BFD_RELOC_PPC64_TPREL16_HIGHESTA BFD_RELOC_PPC64_DTPREL16_LO_DS BFD_RELOC_PPC64_DTPREL16_HIGHER BFD_RELOC_PPC64_DTPREL16_HIGHERA BFD_RELOC_PPC64_DTPREL16_HIGHEST BFD_RELOC_PPC64_DTPREL16_HIGHESTA BFD_RELOC_THUMB_PCREL_BRANCH12 BFD_RELOC_THUMB_PCREL_BRANCH20 BFD_RELOC_THUMB_PCREL_BRANCH23 BFD_RELOC_THUMB_PCREL_BRANCH25 BFD_RELOC_ARM_THUMB_MOVW_PCREL BFD_RELOC_ARM_THUMB_MOVT_PCREL BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 BFD_RELOC_SH_IMM_MEDLOW16_PCREL BFD_RELOC_SH_IMM_MEDHI16_PCREL BFD_RELOC_BFIN_12_PCREL_JUMP_S BFD_RELOC_BFIN_24_PCREL_CALL_X BFD_RELOC_BFIN_24_PCREL_JUMP_L BFD_RELOC_BFIN_FUNCDESC_GOT17M4 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO BFD_RELOC_V850_SDA_16_16_OFFSET BFD_RELOC_V850_SDA_15_16_OFFSET BFD_RELOC_V850_ZDA_16_16_OFFSET BFD_RELOC_V850_ZDA_15_16_OFFSET BFD_RELOC_V850_TDA_16_16_OFFSET BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET BFD_RELOC_V850_CALLT_6_7_OFFSET BFD_RELOC_V850_CALLT_16_16_OFFSET BFD_RELOC_V850_LO16_SPLIT_OFFSET BFD_RELOC_MCORE_PCREL_IMM11BY2 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 BFD_RELOC_MMIX_PUSHJ_STUBBABLE BFD_RELOC_MMIX_BASE_PLUS_OFFSET BFD_RELOC_IA64_LTOFF_FPTR32MSB BFD_RELOC_IA64_LTOFF_FPTR32LSB BFD_RELOC_IA64_LTOFF_FPTR64MSB BFD_RELOC_IA64_LTOFF_FPTR64LSB BFD_RELOC_MSP430_16_PCREL_BYTE @@overflow: BFD_RELOC_UNUSED@@ ../../../toolchain/android-toolchain/binutils-2.19/bfd/reloc.c PE bE oE |E E E E E E E E E F F -F AF XF oF F F F F F F G G 2G IG `G vG G G G G G G H H 7H NH cH xH H H H H H H I I 4I CI RI dI vI I I I I I I J J -J BJ YJ nJ J J J J J J K 8 \ 4K OK fK }K K K K K K K L (L @L XL pL L L L L L L L M &M :M SM iM M M M M M N .N KN iN N N N N N O +O HO eO O O O O O P $P 7P KP `P tP P P P P P P Q Q -Q IQ eQ |Q Q Q Q Q Q R (R CR YR oR R R R R R S %S @S XS sS S S S S S S T T )T @T UT lT T T T T T T U "U :U SU lU U U U U U U V #V 9V PV fV ~V V V V V V W -W CW ZW vW W W W W W X +X AX TX gX }X X X X X X X Y )Y FY cY Y Y Y Y Y Y Z 1Z LZ gZ Z Z Z Z Z Z [ .[ L[ g[ }[ [ [ [ [ [ \ -\ H\ c\ {\ \ \ \ \ \ \ ] %] =] R] j] ] ] ] ] ] ] ^ )^ C^ ]^ y^ ^ ^ ^ ^ ^ _ #_ =_ R_ l_ _ _ _ _ _ ` ` 4` M` d` ` ` ` ` ` a a 1a Ha da a a a a a b b >b [b xb b b b b b c c +c ?c Qc kc c c c c c c d (d @d Zd td d d d d d e 0e Ie de e e e e e e f 0f Jf cf |f f f f f f g 0g Mg fg g g g g g h D (h :h Oh eh ~h h h h h h i )i >i Xi ui i i i i j j :j Wj tj j j j j k !k d ?k ( L p [k nk }k k k k k k l 8l Ql ll l l l l l l m m 4m Mm 4 fm ~m m m m m m m n ,n Dn _n zn n n n n n o (o @o Xo po o o o o o p p 6p Np ip p p p p p p q ,q Dq \q tq q q q q q r %r =r Or ar ur r r T r r r s s 9s Us rs s s s s s t t *t >t Ut lt t t t t t t t u &u @u Zu pu u u u u u u u v #v 5v Kv av wv v v v v v w !w =w Vw mw w w w w w x "x ;x Wx rx x x x x x x y +y Dy Zy ty y y y y y y z z 1z Ez \z yz t z z z z z { { 7{ N{ e{ { { { { { { | | 7| M| e| }| | | | | | } /} 4 X | M} g} } } } } } } } ~ '~ ;~ O~ f~ }~ ~ ~ ~ ~ ~ ~ 3 J _ y ( B T l . F X p ' ; S k ; S o , J @ h h ) = W r < Z s 0 D X l 9 M c y 6 M < d w \ % ; R f | & ? X q / D U i } * @ W n 6 M d { & @ X p - F ^ o % ; T j ! 8 O f } # 8 M b z % ? Y p 8 Q j , F ` z | : U p 3 K b y 5 R m % @ [ y 2 G [ q 2 I ^ u # 7 M a w 3 I ] s 7 O h - B W m 7 J ] t 4 G [ o # = U o 6 L b { ( ? R f y . C X p % < O b v + F ] t 3 E W i - G b } $ < T n $ > X s 0 K f % A ] y + G b | bfd_get_reloc_size a + G h a \ U + + + N bfd_check_overflow bfd_perform_relocation N 2 7 B s / _bfd_relocate_contents _bfd_clear_contents / bfd_generic_get_relocated_section_contents _bfd_generic_link_add_one_symbol P & S . ] y Y m x + K _bfd_generic_link_output_symbols P ] i set_symbol_from_hash F 6 _bfd_generic_link_write_global_symbol _bfd_generic_reloc_link_order _bfd_default_link_order _bfd_generic_section_already_linked __real_ __imp_%s ../../../toolchain/android-toolchain/binutils-2.19/bfd/linker.c %B: indirect symbol `%s' to `%s' is a loop Attempt to do relocatable link with %s input and %s output %B: warning: ignoring duplicate section `%A' %B: warning: duplicate section `%A' has different size %B(%A+0x%lx): Stabs entry has invalid string index. ../../../toolchain/android-toolchain/binutils-2.19/bfd/stabs.c _bfd_add_merge_section _bfd_merged_section_offset ../../../toolchain/android-toolchain/binutils-2.19/bfd/merge.c %s: access beyond end of merged section (%ld) none Demangling disabled auto GNU (g++) style demangling lucid Lucid (lcc) style demangling ARM style demangling hp HP (aCC) style demangling edg EDG style demangling gnu-v3 java Java style demangling gnat GNAT style demangling nw new dl delete vn new [] vd delete [] as apl += ami -= mult amu *= aml convert negate trunc_mod amd %= trunc_div adv /= truth_andif aa truth_orif oo truth_not postincrement ++ pp postdecrement -- mm bit_ior aor |= bit_xor aer ^= bit_and aad &= bit_not co alshift als <<= arshift >>= component -> pt method_call ->() compound cm cond ?: cn max >? min * sz sizeof const volatile const __restrict const volatile __restrict T%d assign_ operator operator _imp__ __imp_ _GLOBAL_ __std__ __sti__ __vtbl__ virtual table global constructors keyed to global destructors keyed to import stub for _ada_ ___ <%s> -2147483648 __pt__ __tm__ __ps__ __S {anonymous} [ __complex int%u_t template < > class JArray1Z false true static 0123456789Qt __thunk_ __t type_info node type_info function Automatic selection based on executable GNU (g++) V3 ABI-style demangling virtual function thunk (delta:%d) for # 7 g < W ] z @ H # . - R - R - R R . R R AR 2 1 5 R 9 8 < ? - L - D H K H O W ^ i h l o z y } - - - - K F 8R F v v - - "- "- : A T/ A - - - H - H # - 0 - + - lO - 3 ? }O - + w + D M P U X U [ _ _ b f W f f 0 i m p _E E E E {E tE mE fE k i i i i i i `k i i i i i i i i k i k k i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i k 'k i i i i i i i i j i i i i i j i i i i i i j j 6n Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej tp tp tp tp tp tp tp tp tp tp Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Bn Ej Yn Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej Ej 6n Ej Ej o o no Ej :o Ej Ej q Ej Ej ?p Ej Ej Ej Ej Ej p o i Ej Pq q p m i 9l i i pm ll i i i i i l i l l i Gm i vl i 9l i i i i i i i i i i i i i i i i i i i i i i i i i l i i i i 9l K K Q byte aN aS dV da delete[] eO eo ix lS mI mL na new[] oR pL pm ps qu rM rS std::allocator std::basic_string std::string std::istream basic_istream std::ostream basic_ostream std::iostream basic_iostream (anonymous namespace) string literal JArray VTT for construction vtable for -in- typeinfo for typeinfo name for typeinfo fn for non-virtual thunk to covariant return thunk to java Class for guard variable for reference temporary for hidden alias for ::* ) ) : ( java resource restrict imaginary A A < < j f ] ] 0 0 - - - - T/ A M 0 "- } ! [ - z * - v R - R R . 0 + 3 R - R 6 < 9 H 9 L - < ? R - }J K E - 8R F H 5 2 K i N 0 - Q :c T l W H - +X p m p t E E a Z Z _ b i i n s { F n i , 1 o ` 1 d 2 5 5 5 5 5 5 5 5 5 5 ; f 5 - X 5 o o o o o o o o o o o o o o o o E o o o o o W 6 ` # i # o { a G - a C C C C C C C C C S u o q q q A A q ~ y y @ ] | | | | i i i | | | std::basic_string, std::allocator > std::basic_istream > std::basic_ostream > std::basic_iostream > out of memory floatformat_ibm_long_double floatformat_ia64_quad_little floatformat_ia64_quad_big floatformat_ia64_spill_little floatformat_ia64_spill_big floatformat_arm_ext_big floatformat_m88110_ext_harris floatformat_m88110_ext floatformat_i960_ext floatformat_m68881_ext floatformat_i387_ext floatformat_vax_g floatformat_vax_d floatformat_vax_f floatformat_ieee_double_big floatformat_ieee_single_big 4 ? p 0 ? p 0 @ 0 @ 0 ` ? @ 4 0 ` ? @ 4 0 4 L 0 P ? @ j 0 ` ? @ 0 ` ? @ 0 P ? @ @ 4 0 @ 7 0 0 @ 4 \ 0 @ 4 0 @ 4 0 0 0 floatformat_arm_ext_littlebyte_bigword floatformat_ieee_double_littlebyte_bigword floatformat_ieee_double_little floatformat_ieee_single_little O %I $ < ;G ]t B { = 0 $ ~ `2 fC O m A oE! a 0 P A A ? & * " @ ` 0 P H X ? " A ! ) ? C = 3 ) Cannot find prime bigger than %lu cccccccccccccccccccccccccccccccccccccccccccccccc ccccccc cccccccccccccccccccccccccc ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc/tmp /usr/tmp /var/tmp TMPDIR TMP TEMP /tmp Cannot create temporary file in %s: %s !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`ABCDEFGHIJKLMNOPQRSTUVWXYZ{|}~ !"#$%&'()*+,-./0123456789:;<=>?@abcdefghijklmnopqrstuvwxyz[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ C B B B B Q 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 %s%sout of memory allocating %lu bytes after a total of %lu bytes undocumented error #%d abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789 XXXXXX
$0 h* x t* p * m * a * g * e * C * d * D * M * z + R + T S "+ f /+ F <+ H O+ s '+ h ]+ H +] i b+ l o+ + + r j + h r+ + S + D + I + W / G 10 A0 + t b V + w 0 0 1 D1 h1 1 + 1 1 2 $2 L2 p2 2 2 2 3 83 \3 3 3 3 + 3 4 44 T4 |4 4 4 4 5 G G G G 6 G G : ?- G 3 G H ] H !H 0 + 0 : 2H AH QH \H pm hH sH n H H 0 H H @v H H H H I I &I 7I ;^ 8/ {/ / r/ / / T f ` L Z ` Z ! ( A - G& Zy = m 4m `m x O@ I HT M [ Sd { Pm { { > F H> l q " " z m < 1u | < N X 7{ ( p "/ ! ( A - G& Zy = m 4m `m x O@ I HT M [ Sd ; {{ { oz > F H> l q " z m < 1u < N X 7{ ( p8'/ ! ( A - G& Zy = m 4m `m x O@ I HT M [ Sd ; Pm { oz > F H> l q " " z m < 1u < N X 7{ ( p #/ o L ! ` @ A bV x R " p < < N X t o8 , u@ z@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ A A A A X@ _@ f@ m@ @ "@ )@ *A 6@ <@ C@ I@ P@ 1A _@ 8A ?A $.$ 0
GCC: (GNU) 3.4.6 (Ubuntu 3.4.6-1ubuntu2) GCC: (GNU) 3.4.6 (Ubuntu 3.4.6-1ubuntu2) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 3.4.6 (Ubuntu 3.4.6-1ubuntu2) GCC: (GNU) 4.0.3 (Ubuntu 4.0.3-1ubuntu5) GCC: (GNU) 3.4.6 (Ubuntu 3.4.6-1ubuntu2)
.shstrtab .interp .note.ABI-tag .hash .dynsym .dynstr .gnu.version .gnu.version_r .rel.dyn .rel.plt .init .text .fini .rodata .eh_frame_hdr .eh_frame .ctors .dtors .jcr .dynamic .got .got.plt .data .bss .comment
