1 /* 2 * Copyright (C) 2007, 2008, 2009 Free Software Foundation, Inc. 3 * 4 * This file is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 3, or (at your option) any 7 * later version. 8 * 9 * This file is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * General Public License for more details. 13 * 14 * Under Section 7 of GPL version 3, you are granted additional 15 * permissions described in the GCC Runtime Library Exception, version 16 * 3.1, as published by the Free Software Foundation. 17 * 18 * You should have received a copy of the GNU General Public License and 19 * a copy of the GCC Runtime Library Exception along with this program; 20 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 21 * <http://www.gnu.org/licenses/>. 22 */ 23 24 /* %ecx */ 25 #define bit_SSE3 (1 << 0) 26 #define bit_PCLMUL (1 << 1) 27 #define bit_SSSE3 (1 << 9) 28 #define bit_FMA (1 << 12) 29 #define bit_CMPXCHG16B (1 << 13) 30 #define bit_SSE4_1 (1 << 19) 31 #define bit_SSE4_2 (1 << 20) 32 #define bit_MOVBE (1 << 22) 33 #define bit_POPCNT (1 << 23) 34 #define bit_AES (1 << 25) 35 #define bit_XSAVE (1 << 26) 36 #define bit_OSXSAVE (1 << 27) 37 #define bit_AVX (1 << 28) 38 39 /* %edx */ 40 #define bit_CMPXCHG8B (1 << 8) 41 #define bit_CMOV (1 << 15) 42 #define bit_MMX (1 << 23) 43 #define bit_FXSAVE (1 << 24) 44 #define bit_SSE (1 << 25) 45 #define bit_SSE2 (1 << 26) 46 47 /* Extended Features */ 48 /* %ecx */ 49 #define bit_LAHF_LM (1 << 0) 50 #define bit_LWP (1 << 15) 51 #define bit_SSE4a (1 << 6) 52 #define bit_SSE5 (1 << 11) 53 54 /* %edx */ 55 #define bit_LM (1 << 29) 56 #define bit_3DNOWP (1 << 30) 57 #define bit_3DNOW (1 << 31) 58 59 60 #if defined(__i386__) && defined(__PIC__) 61 /* %ebx may be the PIC register. */ 62 #if __GNUC__ >= 3 63 #define __cpuid(level, a, b, c, d) \ 64 __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ 65 "cpuid\n\t" \ 66 "xchg{l}\t{%%}ebx, %1\n\t" \ 67 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 68 : "0" (level)) 69 70 #define __cpuid_count(level, count, a, b, c, d) \ 71 __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ 72 "cpuid\n\t" \ 73 "xchg{l}\t{%%}ebx, %1\n\t" \ 74 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 75 : "0" (level), "2" (count)) 76 #else 77 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax 78 nor alternatives in i386 code. */ 79 #define __cpuid(level, a, b, c, d) \ 80 __asm__ ("xchgl\t%%ebx, %1\n\t" \ 81 "cpuid\n\t" \ 82 "xchgl\t%%ebx, %1\n\t" \ 83 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 84 : "0" (level)) 85 86 #define __cpuid_count(level, count, a, b, c, d) \ 87 __asm__ ("xchgl\t%%ebx, %1\n\t" \ 88 "cpuid\n\t" \ 89 "xchgl\t%%ebx, %1\n\t" \ 90 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 91 : "0" (level), "2" (count)) 92 #endif 93 #else 94 #define __cpuid(level, a, b, c, d) \ 95 __asm__ ("cpuid\n\t" \ 96 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ 97 : "0" (level)) 98 99 #define __cpuid_count(level, count, a, b, c, d) \ 100 __asm__ ("cpuid\n\t" \ 101 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ 102 : "0" (level), "2" (count)) 103 #endif 104 105 /* Return highest supported input value for cpuid instruction. ext can 106 be either 0x0 or 0x8000000 to return highest supported value for 107 basic or extended cpuid information. Function returns 0 if cpuid 108 is not supported or whatever cpuid returns in eax register. If sig 109 pointer is non-null, then first four bytes of the signature 110 (as found in ebx register) are returned in location pointed by sig. */ 111 112 static __inline unsigned int 113 __get_cpuid_max (unsigned int __ext, unsigned int *__sig) 114 { 115 unsigned int __eax, __ebx, __ecx, __edx; 116 117 #ifndef __x86_64__ 118 #if __GNUC__ >= 3 119 /* See if we can use cpuid. On AMD64 we always can. */ 120 __asm__ ("pushf{l|d}\n\t" 121 "pushf{l|d}\n\t" 122 "pop{l}\t%0\n\t" 123 "mov{l}\t{%0, %1|%1, %0}\n\t" 124 "xor{l}\t{%2, %0|%0, %2}\n\t" 125 "push{l}\t%0\n\t" 126 "popf{l|d}\n\t" 127 "pushf{l|d}\n\t" 128 "pop{l}\t%0\n\t" 129 "popf{l|d}\n\t" 130 : "=&r" (__eax), "=&r" (__ebx) 131 : "i" (0x00200000)); 132 #else 133 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax 134 nor alternatives in i386 code. */ 135 __asm__ ("pushfl\n\t" 136 "pushfl\n\t" 137 "popl\t%0\n\t" 138 "movl\t%0, %1\n\t" 139 "xorl\t%2, %0\n\t" 140 "pushl\t%0\n\t" 141 "popfl\n\t" 142 "pushfl\n\t" 143 "popl\t%0\n\t" 144 "popfl\n\t" 145 : "=&r" (__eax), "=&r" (__ebx) 146 : "i" (0x00200000)); 147 #endif 148 149 if (!((__eax ^ __ebx) & 0x00200000)) 150 return 0; 151 #endif 152 153 /* Host supports cpuid. Return highest supported cpuid input value. */ 154 __cpuid (__ext, __eax, __ebx, __ecx, __edx); 155 156 if (__sig) 157 *__sig = __ebx; 158 159 return __eax; 160 } 161 162 /* Return cpuid data for requested cpuid level, as found in returned 163 eax, ebx, ecx and edx registers. The function checks if cpuid is 164 supported and returns 1 for valid cpuid information or 0 for 165 unsupported cpuid level. All pointers are required to be non-null. */ 166 167 static __inline int 168 __get_cpuid (unsigned int __level, 169 unsigned int *__eax, unsigned int *__ebx, 170 unsigned int *__ecx, unsigned int *__edx) 171 { 172 unsigned int __ext = __level & 0x80000000; 173 174 if (__get_cpuid_max (__ext, 0) < __level) 175 return 0; 176 177 __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx); 178 return 1; 179 } 180
