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      1 /****************************************************************************
      2  ****************************************************************************
      3  ***
      4  ***   This header was automatically generated from a Linux kernel header
      5  ***   of the same name, to make information necessary for userspace to
      6  ***   call into the kernel available to libc.  It contains only constants,
      7  ***   structures, and macros generated from the original header, and thus,
      8  ***   contains no copyrightable information.
      9  ***
     10  ****************************************************************************
     11  ****************************************************************************/
     12 #ifndef __LINUX_MTD_NAND_H
     13 #define __LINUX_MTD_NAND_H
     14 
     15 #include <linux/wait.h>
     16 #include <linux/spinlock.h>
     17 #include <linux/mtd/mtd.h>
     18 
     19 struct mtd_info;
     20 
     21 #define NAND_MAX_CHIPS 8
     22 
     23 #define NAND_MAX_OOBSIZE 64
     24 #define NAND_MAX_PAGESIZE 2048
     25 
     26 #define NAND_NCE 0x01
     27 
     28 #define NAND_CLE 0x02
     29 
     30 #define NAND_ALE 0x04
     31 
     32 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
     33 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
     34 #define NAND_CTRL_CHANGE 0x80
     35 
     36 #define NAND_CMD_READ0 0
     37 #define NAND_CMD_READ1 1
     38 #define NAND_CMD_RNDOUT 5
     39 #define NAND_CMD_PAGEPROG 0x10
     40 #define NAND_CMD_READOOB 0x50
     41 #define NAND_CMD_ERASE1 0x60
     42 #define NAND_CMD_STATUS 0x70
     43 #define NAND_CMD_STATUS_MULTI 0x71
     44 #define NAND_CMD_SEQIN 0x80
     45 #define NAND_CMD_RNDIN 0x85
     46 #define NAND_CMD_READID 0x90
     47 #define NAND_CMD_ERASE2 0xd0
     48 #define NAND_CMD_RESET 0xff
     49 
     50 #define NAND_CMD_READSTART 0x30
     51 #define NAND_CMD_RNDOUTSTART 0xE0
     52 #define NAND_CMD_CACHEDPROG 0x15
     53 
     54 #define NAND_CMD_DEPLETE1 0x100
     55 #define NAND_CMD_DEPLETE2 0x38
     56 #define NAND_CMD_STATUS_MULTI 0x71
     57 #define NAND_CMD_STATUS_ERROR 0x72
     58 
     59 #define NAND_CMD_STATUS_ERROR0 0x73
     60 #define NAND_CMD_STATUS_ERROR1 0x74
     61 #define NAND_CMD_STATUS_ERROR2 0x75
     62 #define NAND_CMD_STATUS_ERROR3 0x76
     63 #define NAND_CMD_STATUS_RESET 0x7f
     64 #define NAND_CMD_STATUS_CLEAR 0xff
     65 
     66 #define NAND_CMD_NONE -1
     67 
     68 #define NAND_STATUS_FAIL 0x01
     69 #define NAND_STATUS_FAIL_N1 0x02
     70 #define NAND_STATUS_TRUE_READY 0x20
     71 #define NAND_STATUS_READY 0x40
     72 #define NAND_STATUS_WP 0x80
     73 
     74 typedef enum {
     75  NAND_ECC_NONE,
     76  NAND_ECC_SOFT,
     77  NAND_ECC_HW,
     78  NAND_ECC_HW_SYNDROME,
     79 } nand_ecc_modes_t;
     80 
     81 #define NAND_ECC_READ 0
     82 
     83 #define NAND_ECC_WRITE 1
     84 
     85 #define NAND_ECC_READSYN 2
     86 
     87 #define NAND_GET_DEVICE 0x80
     88 
     89 #define NAND_NO_AUTOINCR 0x00000001
     90 
     91 #define NAND_BUSWIDTH_16 0x00000002
     92 
     93 #define NAND_NO_PADDING 0x00000004
     94 
     95 #define NAND_CACHEPRG 0x00000008
     96 
     97 #define NAND_COPYBACK 0x00000010
     98 
     99 #define NAND_IS_AND 0x00000020
    100 
    101 #define NAND_4PAGE_ARRAY 0x00000040
    102 
    103 #define BBT_AUTO_REFRESH 0x00000080
    104 
    105 #define NAND_NO_READRDY 0x00000100
    106 
    107 #define NAND_SAMSUNG_LP_OPTIONS   (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
    108 
    109 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
    110 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
    111 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
    112 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
    113 
    114 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
    115 
    116 #define NAND_USE_FLASH_BBT 0x00010000
    117 
    118 #define NAND_SKIP_BBTSCAN 0x00020000
    119 
    120 #define NAND_CONTROLLER_ALLOC 0x80000000
    121 
    122 typedef enum {
    123  FL_READY,
    124  FL_READING,
    125  FL_WRITING,
    126  FL_ERASING,
    127  FL_SYNCING,
    128  FL_CACHEDPRG,
    129  FL_PM_SUSPENDED,
    130 } nand_state_t;
    131 
    132 struct nand_chip;
    133 
    134 struct nand_hw_control {
    135  spinlock_t lock;
    136  struct nand_chip *active;
    137  wait_queue_head_t wq;
    138 };
    139 
    140 struct nand_ecc_ctrl {
    141  nand_ecc_modes_t mode;
    142  int steps;
    143  int size;
    144  int bytes;
    145  int total;
    146  int prepad;
    147  int postpad;
    148  struct nand_ecclayout *layout;
    149  void (*hwctl)(struct mtd_info *mtd, int mode);
    150  int (*calculate)(struct mtd_info *mtd,
    151  const uint8_t *dat,
    152  uint8_t *ecc_code);
    153  int (*correct)(struct mtd_info *mtd, uint8_t *dat,
    154  uint8_t *read_ecc,
    155  uint8_t *calc_ecc);
    156  int (*read_page)(struct mtd_info *mtd,
    157  struct nand_chip *chip,
    158  uint8_t *buf);
    159  void (*write_page)(struct mtd_info *mtd,
    160  struct nand_chip *chip,
    161  const uint8_t *buf);
    162  int (*read_oob)(struct mtd_info *mtd,
    163  struct nand_chip *chip,
    164  int page,
    165  int sndcmd);
    166  int (*write_oob)(struct mtd_info *mtd,
    167  struct nand_chip *chip,
    168  int page);
    169 };
    170 
    171 struct nand_buffers {
    172  uint8_t ecccalc[NAND_MAX_OOBSIZE];
    173  uint8_t ecccode[NAND_MAX_OOBSIZE];
    174  uint8_t oobwbuf[NAND_MAX_OOBSIZE];
    175  uint8_t databuf[NAND_MAX_PAGESIZE];
    176  uint8_t oobrbuf[NAND_MAX_OOBSIZE];
    177 };
    178 
    179 struct nand_chip {
    180  void __iomem *IO_ADDR_R;
    181  void __iomem *IO_ADDR_W;
    182 
    183  uint8_t (*read_byte)(struct mtd_info *mtd);
    184  u16 (*read_word)(struct mtd_info *mtd);
    185  void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
    186  void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
    187  int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
    188  void (*select_chip)(struct mtd_info *mtd, int chip);
    189  int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
    190  int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
    191  void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
    192  unsigned int ctrl);
    193  int (*dev_ready)(struct mtd_info *mtd);
    194  void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
    195  int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
    196  void (*erase_cmd)(struct mtd_info *mtd, int page);
    197  int (*scan_bbt)(struct mtd_info *mtd);
    198  int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
    199 
    200  int chip_delay;
    201  unsigned int options;
    202 
    203  int page_shift;
    204  int phys_erase_shift;
    205  int bbt_erase_shift;
    206  int chip_shift;
    207  int numchips;
    208  unsigned long chipsize;
    209  int pagemask;
    210  int pagebuf;
    211  int badblockpos;
    212 
    213  nand_state_t state;
    214 
    215  uint8_t *oob_poi;
    216  struct nand_hw_control *controller;
    217  struct nand_ecclayout *ecclayout;
    218 
    219  struct nand_ecc_ctrl ecc;
    220  struct nand_buffers buffers;
    221  struct nand_hw_control hwcontrol;
    222 
    223  struct mtd_oob_ops ops;
    224 
    225  uint8_t *bbt;
    226  struct nand_bbt_descr *bbt_td;
    227  struct nand_bbt_descr *bbt_md;
    228 
    229  struct nand_bbt_descr *badblock_pattern;
    230 
    231  void *priv;
    232 };
    233 
    234 #define NAND_MFR_TOSHIBA 0x98
    235 #define NAND_MFR_SAMSUNG 0xec
    236 #define NAND_MFR_FUJITSU 0x04
    237 #define NAND_MFR_NATIONAL 0x8f
    238 #define NAND_MFR_RENESAS 0x07
    239 #define NAND_MFR_STMICRO 0x20
    240 #define NAND_MFR_HYNIX 0xad
    241 
    242 struct nand_flash_dev {
    243  char *name;
    244  int id;
    245  unsigned long pagesize;
    246  unsigned long chipsize;
    247  unsigned long erasesize;
    248  unsigned long options;
    249 };
    250 
    251 struct nand_manufacturers {
    252  int id;
    253  char * name;
    254 };
    255 
    256 struct nand_bbt_descr {
    257  int options;
    258  int pages[NAND_MAX_CHIPS];
    259  int offs;
    260  int veroffs;
    261  uint8_t version[NAND_MAX_CHIPS];
    262  int len;
    263  int maxblocks;
    264  int reserved_block_code;
    265  uint8_t *pattern;
    266 };
    267 
    268 #define NAND_BBT_NRBITS_MSK 0x0000000F
    269 #define NAND_BBT_1BIT 0x00000001
    270 #define NAND_BBT_2BIT 0x00000002
    271 #define NAND_BBT_4BIT 0x00000004
    272 #define NAND_BBT_8BIT 0x00000008
    273 
    274 #define NAND_BBT_LASTBLOCK 0x00000010
    275 
    276 #define NAND_BBT_ABSPAGE 0x00000020
    277 
    278 #define NAND_BBT_SEARCH 0x00000040
    279 
    280 #define NAND_BBT_PERCHIP 0x00000080
    281 
    282 #define NAND_BBT_VERSION 0x00000100
    283 
    284 #define NAND_BBT_CREATE 0x00000200
    285 
    286 #define NAND_BBT_SCANALLPAGES 0x00000400
    287 
    288 #define NAND_BBT_SCANEMPTY 0x00000800
    289 
    290 #define NAND_BBT_WRITE 0x00001000
    291 
    292 #define NAND_BBT_SAVECONTENT 0x00002000
    293 
    294 #define NAND_BBT_SCAN2NDPAGE 0x00004000
    295 
    296 #define NAND_BBT_SCAN_MAXBLOCKS 4
    297 
    298 #define NAND_SMALL_BADBLOCK_POS 5
    299 #define NAND_LARGE_BADBLOCK_POS 0
    300 
    301 struct platform_nand_chip {
    302  int nr_chips;
    303  int chip_offset;
    304  int nr_partitions;
    305  struct mtd_partition *partitions;
    306  struct nand_ecclayout *ecclayout;
    307  int chip_delay;
    308  unsigned int options;
    309  void *priv;
    310 };
    311 
    312 struct platform_nand_ctrl {
    313  void (*hwcontrol)(struct mtd_info *mtd, int cmd);
    314  int (*dev_ready)(struct mtd_info *mtd);
    315  void (*select_chip)(struct mtd_info *mtd, int chip);
    316  void *priv;
    317 };
    318 
    319 #endif
    320