Lines Matching refs:ISD
501 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
502 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
503 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
504 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
505 CCs[RTLIB::UNE_F32] = ISD::SETNE;
506 CCs[RTLIB::UNE_F64] = ISD::SETNE;
507 CCs[RTLIB::OGE_F32] = ISD::SETGE;
508 CCs[RTLIB::OGE_F64] = ISD::SETGE;
509 CCs[RTLIB::OLT_F32] = ISD::SETLT;
510 CCs[RTLIB::OLT_F64] = ISD::SETLT;
511 CCs[RTLIB::OLE_F32] = ISD::SETLE;
512 CCs[RTLIB::OLE_F64] = ISD::SETLE;
513 CCs[RTLIB::OGT_F32] = ISD::SETGT;
514 CCs[RTLIB::OGT_F64] = ISD::SETGT;
515 CCs[RTLIB::UO_F32] = ISD::SETNE;
516 CCs[RTLIB::UO_F64] = ISD::SETNE;
517 CCs[RTLIB::O_F32] = ISD::SETEQ;
518 CCs[RTLIB::O_F64] = ISD::SETEQ;
536 for (unsigned IM = (unsigned)ISD::PRE_INC;
537 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
543 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
553 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
554 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
555 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
556 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
559 setOperationAction(ISD::FLOG , MVT::f16, Expand);
560 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
561 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
562 setOperationAction(ISD::FEXP , MVT::f16, Expand);
563 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
564 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
565 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
566 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
567 setOperationAction(ISD::FRINT, MVT::f16, Expand);
568 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
569 setOperationAction(ISD::FLOG , MVT::f32, Expand);
570 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
571 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
572 setOperationAction(ISD::FEXP , MVT::f32, Expand);
573 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
574 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
575 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
576 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
577 setOperationAction(ISD::FRINT, MVT::f32, Expand);
578 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
579 setOperationAction(ISD::FLOG , MVT::f64, Expand);
580 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
581 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
582 setOperationAction(ISD::FEXP , MVT::f64, Expand);
583 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
584 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
585 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
586 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
587 setOperationAction(ISD::FRINT, MVT::f64, Expand);
588 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
590 // Default ISD::TRAP to expand (which turns it into abort).
591 setOperationAction(ISD::TRAP, MVT::Other, Expand);
642 case ISD::FDIV:
643 case ISD::FREM:
644 case ISD::SDIV:
645 case ISD::UDIV:
646 case ISD::SREM:
647 case ISD::UREM:
1002 SmallVectorImpl<ISD::OutputArg> &Outs,
1013 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1016 ExtendKind = ISD::SIGN_EXTEND;
1018 ExtendKind = ISD::ZERO_EXTEND;
1024 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1036 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1047 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1130 // FIXME: ISD::SELECT, ISD::SELECT_CC
1133 case ISD::XOR:
1134 case ISD::AND:
1135 case ISD::OR: {
1139 if (Op.getOpcode() == ISD::XOR &&
1191 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1193 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1195 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1237 if (Op.getOpcode() != ISD::UNDEF)
1246 case ISD::Constant:
1251 case ISD::AND:
1299 case ISD::OR:
1333 case ISD::XOR:
1357 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1375 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1403 case ISD::SELECT:
1421 case ISD::SELECT_CC:
1439 case ISD::SHL:
1451 if (InOp.getOpcode() == ISD::SRL &&
1455 unsigned Opc = ISD::SHL;
1459 Opc = ISD::SRL;
1476 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1481 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1486 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1490 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1501 case ISD::SRL:
1515 if (InOp.getOpcode() == ISD::SHL &&
1519 unsigned Opc = ISD::SRL;
1523 Opc = ISD::SHL;
1545 case ISD::SRA:
1552 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1584 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1592 case ISD::SIGN_EXTEND_INREG: {
1608 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1655 case ISD::ZERO_EXTEND: {
1664 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1677 case ISD::SIGN_EXTEND: {
1686 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1704 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1718 case ISD::ANY_EXTEND: {
1730 case ISD::TRUNCATE: {
1748 case ISD::SRL:
1752 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1773 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1776 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1788 case ISD::AssertZext: {
1802 case ISD::BITCAST:
1810 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1811 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1816 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1819 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1822 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1828 case ISD::ADD:
1829 case ISD::MUL:
1830 case ISD::SUB: {
1868 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1869 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1870 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1871 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1882 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1883 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1884 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1885 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1898 if (Val.getOpcode() == ISD::SHL)
1906 if (Val.getOpcode() == ISD::SRL)
1928 ISD::CondCode Cond, bool foldBooleans,
1935 case ISD::SETFALSE:
1936 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1937 case ISD::SETTRUE:
1938 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1944 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1952 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1953 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1954 N0.getOperand(1).getOpcode() == ISD::Constant) {
1957 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1959 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1962 Cond = ISD::SETNE;
1966 Cond = ISD::SETEQ;
1976 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1979 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1987 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1988 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1990 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1991 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
2000 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2003 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
2007 } else if (N0->getOpcode() == ISD::AND) {
2016 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2025 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2027 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2038 N0.getOpcode() == ISD::AND && C1 == 0 &&
2051 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2077 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2084 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2093 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2101 case ISD::SETUGT:
2102 case ISD::SETUGE:
2103 case ISD::SETEQ: return DAG.getConstant(0, VT);
2104 case ISD::SETULT:
2105 case ISD::SETULE:
2106 case ISD::SETNE: return DAG.getConstant(1, VT);
2107 case ISD::SETGT:
2108 case ISD::SETGE:
2111 case ISD::SETLT:
2112 case ISD::SETLE:
2122 case ISD::SETEQ:
2123 case ISD::SETNE:
2124 case ISD::SETUGT:
2125 case ISD::SETUGE:
2126 case ISD::SETULT:
2127 case ISD::SETULE: {
2130 (isOperationLegal(ISD::SETCC, newVT) &&
2140 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2141 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2150 return DAG.getConstant(Cond == ISD::SETNE, VT);
2158 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2171 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2173 if (N0.getOpcode() == ISD::SETCC &&
2175 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2177 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2179 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2180 CC = ISD::getSetCCInverse(CC,
2185 if ((N0.getOpcode() == ISD::XOR ||
2186 (N0.getOpcode() == ISD::AND &&
2187 N0.getOperand(0).getOpcode() == ISD::XOR &&
2199 if (N0.getOpcode() == ISD::XOR)
2202 assert(N0.getOpcode() == ISD::AND &&
2203 N0.getOperand(0).getOpcode() == ISD::XOR);
2205 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2211 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2217 if (Op0.getOpcode() == ISD::TRUNCATE)
2220 if ((Op0.getOpcode() == ISD::XOR) &&
2221 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2222 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2224 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2227 } else if (Op0.getOpcode() == ISD::AND &&
2232 Op0 = DAG.getNode(ISD::AND, dl, VT,
2233 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2236 Op0 = DAG.getNode(ISD::AND, dl, VT,
2237 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2242 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2249 if (ISD::isSignedIntSetCC(Cond)) {
2258 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2263 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2266 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2271 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2274 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2276 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2278 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2280 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2284 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2285 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2287 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2288 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2291 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2294 ISD::SETEQ);
2296 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2299 ISD::SETEQ);
2305 if (Cond == ISD::SETUGT &&
2309 ISD::SETLT);
2312 if (Cond == ISD::SETULT &&
2317 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2321 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2324 N0.getOpcode() == ISD::AND)
2329 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2332 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2333 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2336 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2340 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2341 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2357 switch (ISD::getUnorderedFlavor(Cond)) {
2372 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2383 if (Cond == ISD::SETOEQ &&
2384 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2385 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2386 if (Cond == ISD::SETUEQ &&
2387 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2388 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2389 if (Cond == ISD::SETUNE &&
2390 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2391 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2392 if (Cond == ISD::SETONE &&
2393 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2394 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2396 if (Cond == ISD::SETOEQ &&
2397 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2398 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2399 if (Cond == ISD::SETUEQ &&
2400 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2401 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2402 if (Cond == ISD::SETUNE &&
2403 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2404 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2405 if (Cond == ISD::SETONE &&
2406 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2407 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2419 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2421 return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT);
2424 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2426 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2427 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2431 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2436 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2438 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2439 N0.getOpcode() == ISD::XOR) {
2464 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2472 if (N0.getOpcode() == ISD::XOR)
2486 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2514 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2516 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
2526 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2527 N1.getOpcode() == ISD::XOR) {
2537 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2539 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2552 if (N0.getOpcode() == ISD::AND)
2555 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2560 if (N1.getOpcode() == ISD::AND)
2563 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2575 case ISD::SETEQ: // X == Y -> ~(X^Y)
2576 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2581 case ISD::SETNE: // X != Y --> (X^Y)
2582 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2584 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2585 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2587 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2591 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2592 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2594 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2598 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2599 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2601 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2605 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2606 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2608 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2615 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2635 if (N->getOpcode() == ISD::ADD) {
2729 if (Op.getOpcode() == ISD::BasicBlock) {
2744 if (Op.getOpcode() == ISD::ADD) {
3266 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3276 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3279 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3300 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3301 isOperationLegalOrCustom(ISD::MULHS, VT))
3302 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3304 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3305 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3306 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3313 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3319 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3325 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3332 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3336 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3339 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3365 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3377 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3378 isOperationLegalOrCustom(ISD::MULHU, VT))
3379 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3380 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3381 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3382 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3392 return DAG.getNode(ISD::SRL, dl, VT, Q,
3395 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3398 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3402 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3405 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
