Lines Matching full:opc
459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
560 unsigned Opc = MI->getOpcode();
561 switch (Opc) {
603 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
604 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
620 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
622 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
662 unsigned Opc = 0;
664 Opc = ARM::VMOVS;
666 Opc = ARM::VMOVRS;
668 Opc = ARM::VMOVSR;
670 Opc = ARM::VMOVD;
672 Opc = ARM::VORRq;
674 if (Opc) {
675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
677 if (Opc == ARM::VORRq)
690 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
692 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
695 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
697 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
699 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
702 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
704 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
706 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
708 if (Opc) {
715 Mov = AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
718 if (Opc == ARM::VORRq)
1492 int llvm::getMatchingCondBranchOpcode(int Opc) {
1493 if (Opc == ARM::B)
1495 if (Opc == ARM::tB)
1497 if (Opc == ARM::t2B)
1596 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1597 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2078 unsigned Opc = MI->getOpcode();
2079 switch (Opc) {
