1 //===-- llvm/InlineAsm.h - Class to represent inline asm strings-*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This class represents the inline asm strings, which are Value*'s that are 11 // used as the callee operand of call instructions. InlineAsm's are uniqued 12 // like constants, and created via InlineAsm::get(...). 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_INLINEASM_H 17 #define LLVM_INLINEASM_H 18 19 #include "llvm/Value.h" 20 #include "llvm/ADT/StringRef.h" 21 #include <vector> 22 23 namespace llvm { 24 25 class PointerType; 26 class FunctionType; 27 class Module; 28 struct InlineAsmKeyType; 29 template<class ValType, class ValRefType, class TypeClass, class ConstantClass, 30 bool HasLargeKey> 31 class ConstantUniqueMap; 32 template<class ConstantClass, class TypeClass, class ValType> 33 struct ConstantCreator; 34 35 class InlineAsm : public Value { 36 friend struct ConstantCreator<InlineAsm, PointerType, InlineAsmKeyType>; 37 friend class ConstantUniqueMap<InlineAsmKeyType, const InlineAsmKeyType&, 38 PointerType, InlineAsm, false>; 39 40 InlineAsm(const InlineAsm &); // do not implement 41 void operator=(const InlineAsm&); // do not implement 42 43 std::string AsmString, Constraints; 44 bool HasSideEffects; 45 bool IsAlignStack; 46 47 InlineAsm(PointerType *Ty, const std::string &AsmString, 48 const std::string &Constraints, bool hasSideEffects, 49 bool isAlignStack); 50 virtual ~InlineAsm(); 51 52 /// When the ConstantUniqueMap merges two types and makes two InlineAsms 53 /// identical, it destroys one of them with this method. 54 void destroyConstant(); 55 public: 56 57 /// InlineAsm::get - Return the specified uniqued inline asm string. 58 /// 59 static InlineAsm *get(FunctionType *Ty, StringRef AsmString, 60 StringRef Constraints, bool hasSideEffects, 61 bool isAlignStack = false); 62 63 bool hasSideEffects() const { return HasSideEffects; } 64 bool isAlignStack() const { return IsAlignStack; } 65 66 /// getType - InlineAsm's are always pointers. 67 /// 68 PointerType *getType() const { 69 return reinterpret_cast<PointerType*>(Value::getType()); 70 } 71 72 /// getFunctionType - InlineAsm's are always pointers to functions. 73 /// 74 FunctionType *getFunctionType() const; 75 76 const std::string &getAsmString() const { return AsmString; } 77 const std::string &getConstraintString() const { return Constraints; } 78 79 /// Verify - This static method can be used by the parser to check to see if 80 /// the specified constraint string is legal for the type. This returns true 81 /// if legal, false if not. 82 /// 83 static bool Verify(FunctionType *Ty, StringRef Constraints); 84 85 // Constraint String Parsing 86 enum ConstraintPrefix { 87 isInput, // 'x' 88 isOutput, // '=x' 89 isClobber // '~x' 90 }; 91 92 typedef std::vector<std::string> ConstraintCodeVector; 93 94 struct SubConstraintInfo { 95 /// MatchingInput - If this is not -1, this is an output constraint where an 96 /// input constraint is required to match it (e.g. "0"). The value is the 97 /// constraint number that matches this one (for example, if this is 98 /// constraint #0 and constraint #4 has the value "0", this will be 4). 99 signed char MatchingInput; 100 /// Code - The constraint code, either the register name (in braces) or the 101 /// constraint letter/number. 102 ConstraintCodeVector Codes; 103 /// Default constructor. 104 SubConstraintInfo() : MatchingInput(-1) {} 105 }; 106 107 typedef std::vector<SubConstraintInfo> SubConstraintInfoVector; 108 struct ConstraintInfo; 109 typedef std::vector<ConstraintInfo> ConstraintInfoVector; 110 111 struct ConstraintInfo { 112 /// Type - The basic type of the constraint: input/output/clobber 113 /// 114 ConstraintPrefix Type; 115 116 /// isEarlyClobber - "&": output operand writes result before inputs are all 117 /// read. This is only ever set for an output operand. 118 bool isEarlyClobber; 119 120 /// MatchingInput - If this is not -1, this is an output constraint where an 121 /// input constraint is required to match it (e.g. "0"). The value is the 122 /// constraint number that matches this one (for example, if this is 123 /// constraint #0 and constraint #4 has the value "0", this will be 4). 124 signed char MatchingInput; 125 126 /// hasMatchingInput - Return true if this is an output constraint that has 127 /// a matching input constraint. 128 bool hasMatchingInput() const { return MatchingInput != -1; } 129 130 /// isCommutative - This is set to true for a constraint that is commutative 131 /// with the next operand. 132 bool isCommutative; 133 134 /// isIndirect - True if this operand is an indirect operand. This means 135 /// that the address of the source or destination is present in the call 136 /// instruction, instead of it being returned or passed in explicitly. This 137 /// is represented with a '*' in the asm string. 138 bool isIndirect; 139 140 /// Code - The constraint code, either the register name (in braces) or the 141 /// constraint letter/number. 142 ConstraintCodeVector Codes; 143 144 /// isMultipleAlternative - '|': has multiple-alternative constraints. 145 bool isMultipleAlternative; 146 147 /// multipleAlternatives - If there are multiple alternative constraints, 148 /// this array will contain them. Otherwise it will be empty. 149 SubConstraintInfoVector multipleAlternatives; 150 151 /// The currently selected alternative constraint index. 152 unsigned currentAlternativeIndex; 153 154 ///Default constructor. 155 ConstraintInfo(); 156 157 /// Copy constructor. 158 ConstraintInfo(const ConstraintInfo &other); 159 160 /// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the 161 /// fields in this structure. If the constraint string is not understood, 162 /// return true, otherwise return false. 163 bool Parse(StringRef Str, ConstraintInfoVector &ConstraintsSoFar); 164 165 /// selectAlternative - Point this constraint to the alternative constraint 166 /// indicated by the index. 167 void selectAlternative(unsigned index); 168 }; 169 170 /// ParseConstraints - Split up the constraint string into the specific 171 /// constraints and their prefixes. If this returns an empty vector, and if 172 /// the constraint string itself isn't empty, there was an error parsing. 173 static ConstraintInfoVector ParseConstraints(StringRef ConstraintString); 174 175 /// ParseConstraints - Parse the constraints of this inlineasm object, 176 /// returning them the same way that ParseConstraints(str) does. 177 ConstraintInfoVector ParseConstraints() const { 178 return ParseConstraints(Constraints); 179 } 180 181 // Methods for support type inquiry through isa, cast, and dyn_cast: 182 static inline bool classof(const InlineAsm *) { return true; } 183 static inline bool classof(const Value *V) { 184 return V->getValueID() == Value::InlineAsmVal; 185 } 186 187 188 // These are helper methods for dealing with flags in the INLINEASM SDNode 189 // in the backend. 190 191 enum { 192 // Fixed operands on an INLINEASM SDNode. 193 Op_InputChain = 0, 194 Op_AsmString = 1, 195 Op_MDNode = 2, 196 Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack 197 Op_FirstOperand = 4, 198 199 // Fixed operands on an INLINEASM MachineInstr. 200 MIOp_AsmString = 0, 201 MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack 202 MIOp_FirstOperand = 2, 203 204 // Interpretation of the MIOp_ExtraInfo bit field. 205 Extra_HasSideEffects = 1, 206 Extra_IsAlignStack = 2, 207 208 // Inline asm operands map to multiple SDNode / MachineInstr operands. 209 // The first operand is an immediate describing the asm operand, the low 210 // bits is the kind: 211 Kind_RegUse = 1, // Input register, "r". 212 Kind_RegDef = 2, // Output register, "=r". 213 Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r". 214 Kind_Clobber = 4, // Clobbered register, "~r". 215 Kind_Imm = 5, // Immediate. 216 Kind_Mem = 6, // Memory operand, "m". 217 218 Flag_MatchingOperand = 0x80000000 219 }; 220 221 static unsigned getFlagWord(unsigned Kind, unsigned NumOps) { 222 assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!"); 223 assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind"); 224 return Kind | (NumOps << 3); 225 } 226 227 /// getFlagWordForMatchingOp - Augment an existing flag word returned by 228 /// getFlagWord with information indicating that this input operand is tied 229 /// to a previous output operand. 230 static unsigned getFlagWordForMatchingOp(unsigned InputFlag, 231 unsigned MatchedOperandNo) { 232 assert(MatchedOperandNo <= 0x7fff && "Too big matched operand"); 233 assert((InputFlag & ~0xffff) == 0 && "High bits already contain data"); 234 return InputFlag | Flag_MatchingOperand | (MatchedOperandNo << 16); 235 } 236 237 /// getFlagWordForRegClass - Augment an existing flag word returned by 238 /// getFlagWord with the required register class for the following register 239 /// operands. 240 /// A tied use operand cannot have a register class, use the register class 241 /// from the def operand instead. 242 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) { 243 // Store RC + 1, reserve the value 0 to mean 'no register class'. 244 ++RC; 245 assert(RC <= 0x7fff && "Too large register class ID"); 246 assert((InputFlag & ~0xffff) == 0 && "High bits already contain data"); 247 return InputFlag | (RC << 16); 248 } 249 250 static unsigned getKind(unsigned Flags) { 251 return Flags & 7; 252 } 253 254 static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;} 255 static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; } 256 static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; } 257 static bool isRegDefEarlyClobberKind(unsigned Flag) { 258 return getKind(Flag) == Kind_RegDefEarlyClobber; 259 } 260 static bool isClobberKind(unsigned Flag) { 261 return getKind(Flag) == Kind_Clobber; 262 } 263 264 /// getNumOperandRegisters - Extract the number of registers field from the 265 /// inline asm operand flag. 266 static unsigned getNumOperandRegisters(unsigned Flag) { 267 return (Flag & 0xffff) >> 3; 268 } 269 270 /// isUseOperandTiedToDef - Return true if the flag of the inline asm 271 /// operand indicates it is an use operand that's matched to a def operand. 272 static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx) { 273 if ((Flag & Flag_MatchingOperand) == 0) 274 return false; 275 Idx = (Flag & ~Flag_MatchingOperand) >> 16; 276 return true; 277 } 278 279 /// hasRegClassConstraint - Returns true if the flag contains a register 280 /// class constraint. Sets RC to the register class ID. 281 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) { 282 if (Flag & Flag_MatchingOperand) 283 return false; 284 unsigned High = Flag >> 16; 285 // getFlagWordForRegClass() uses 0 to mean no register class, and otherwise 286 // stores RC + 1. 287 if (!High) 288 return false; 289 RC = High - 1; 290 return true; 291 } 292 293 }; 294 295 } // End llvm namespace 296 297 #endif 298
