1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef POWERPC_INSTRUCTIONINFO_H 15 #define POWERPC_INSTRUCTIONINFO_H 16 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "llvm/Target/TargetInstrInfo.h" 20 21 #define GET_INSTRINFO_HEADER 22 #include "PPCGenInstrInfo.inc" 23 24 namespace llvm { 25 26 /// PPCII - This namespace holds all of the PowerPC target-specific 27 /// per-instruction flags. These must match the corresponding definitions in 28 /// PPC.td and PPCInstrFormats.td. 29 namespace PPCII { 30 enum { 31 // PPC970 Instruction Flags. These flags describe the characteristics of the 32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 33 // raw machine instructions. 34 35 /// PPC970_First - This instruction starts a new dispatch group, so it will 36 /// always be the first one in the group. 37 PPC970_First = 0x1, 38 39 /// PPC970_Single - This instruction starts a new dispatch group and 40 /// terminates it, so it will be the sole instruction in the group. 41 PPC970_Single = 0x2, 42 43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 44 /// two dispatch pipes to be available to issue. 45 PPC970_Cracked = 0x4, 46 47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 48 /// an instruction is issued to. 49 PPC970_Shift = 3, 50 PPC970_Mask = 0x07 << PPC970_Shift 51 }; 52 enum PPC970_Unit { 53 /// These are the various PPC970 execution unit pipelines. Each instruction 54 /// is one of these. 55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 63 }; 64 } // end namespace PPCII 65 66 67 class PPCInstrInfo : public PPCGenInstrInfo { 68 PPCTargetMachine &TM; 69 const PPCRegisterInfo RI; 70 71 bool StoreRegToStackSlot(MachineFunction &MF, 72 unsigned SrcReg, bool isKill, int FrameIdx, 73 const TargetRegisterClass *RC, 74 SmallVectorImpl<MachineInstr*> &NewMIs) const; 75 bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 76 unsigned DestReg, int FrameIdx, 77 const TargetRegisterClass *RC, 78 SmallVectorImpl<MachineInstr*> &NewMIs) const; 79 public: 80 explicit PPCInstrInfo(PPCTargetMachine &TM); 81 82 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 83 /// such, whenever a client has an instance of instruction info, it should 84 /// always be able to get register info as well (through this method). 85 /// 86 virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; } 87 88 ScheduleHazardRecognizer * 89 CreateTargetHazardRecognizer(const TargetMachine *TM, 90 const ScheduleDAG *DAG) const; 91 ScheduleHazardRecognizer * 92 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 93 const ScheduleDAG *DAG) const; 94 95 unsigned isLoadFromStackSlot(const MachineInstr *MI, 96 int &FrameIndex) const; 97 unsigned isStoreToStackSlot(const MachineInstr *MI, 98 int &FrameIndex) const; 99 100 // commuteInstruction - We can commute rlwimi instructions, but only if the 101 // rotate amt is zero. We also have to munge the immediates a bit. 102 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 103 104 virtual void insertNoop(MachineBasicBlock &MBB, 105 MachineBasicBlock::iterator MI) const; 106 107 108 // Branch analysis. 109 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 110 MachineBasicBlock *&FBB, 111 SmallVectorImpl<MachineOperand> &Cond, 112 bool AllowModify) const; 113 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 114 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 115 MachineBasicBlock *FBB, 116 const SmallVectorImpl<MachineOperand> &Cond, 117 DebugLoc DL) const; 118 virtual void copyPhysReg(MachineBasicBlock &MBB, 119 MachineBasicBlock::iterator I, DebugLoc DL, 120 unsigned DestReg, unsigned SrcReg, 121 bool KillSrc) const; 122 123 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 124 MachineBasicBlock::iterator MBBI, 125 unsigned SrcReg, bool isKill, int FrameIndex, 126 const TargetRegisterClass *RC, 127 const TargetRegisterInfo *TRI) const; 128 129 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 130 MachineBasicBlock::iterator MBBI, 131 unsigned DestReg, int FrameIndex, 132 const TargetRegisterClass *RC, 133 const TargetRegisterInfo *TRI) const; 134 135 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 136 int FrameIx, 137 uint64_t Offset, 138 const MDNode *MDPtr, 139 DebugLoc DL) const; 140 141 virtual 142 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 143 144 /// GetInstSize - Return the number of bytes of code the specified 145 /// instruction may be. This returns the maximum number of bytes. 146 /// 147 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 148 }; 149 150 } 151 152 #endif 153
