1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SelectionDAG::LegalizeVectors method. 11 // 12 // The vector legalizer looks for vector operations which might need to be 13 // scalarized and legalizes them. This is a separate step from Legalize because 14 // scalarizing can introduce illegal types. For example, suppose we have an 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition 16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the 17 // operation, which introduces nodes with the illegal type i64 which must be 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 19 // the operation must be unrolled, which introduces nodes with the illegal 20 // type i8 which must be promoted. 21 // 22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR, 23 // or operations that happen to take a vector which are custom-lowered; 24 // the legalization for such operations never produces nodes 25 // with illegal types, so it's okay to put off legalizing them until 26 // SelectionDAG::Legalize runs. 27 // 28 //===----------------------------------------------------------------------===// 29 30 #include "llvm/CodeGen/SelectionDAG.h" 31 #include "llvm/Target/TargetLowering.h" 32 using namespace llvm; 33 34 namespace { 35 class VectorLegalizer { 36 SelectionDAG& DAG; 37 const TargetLowering &TLI; 38 bool Changed; // Keep track of whether anything changed 39 40 /// LegalizedNodes - For nodes that are of legal width, and that have more 41 /// than one use, this map indicates what regularized operand to use. This 42 /// allows us to avoid legalizing the same thing more than once. 43 DenseMap<SDValue, SDValue> LegalizedNodes; 44 45 // Adds a node to the translation cache 46 void AddLegalizedOperand(SDValue From, SDValue To) { 47 LegalizedNodes.insert(std::make_pair(From, To)); 48 // If someone requests legalization of the new node, return itself. 49 if (From != To) 50 LegalizedNodes.insert(std::make_pair(To, To)); 51 } 52 53 // Legalizes the given node 54 SDValue LegalizeOp(SDValue Op); 55 // Assuming the node is legal, "legalize" the results 56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result); 57 // Implements unrolling a VSETCC. 58 SDValue UnrollVSETCC(SDValue Op); 59 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB 60 // isn't legal. 61 // Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if 62 // SINT_TO_FLOAT and SHR on vectors isn't legal. 63 SDValue ExpandUINT_TO_FLOAT(SDValue Op); 64 // Implement vselect in terms of XOR, AND, OR when blend is not supported 65 // by the target. 66 SDValue ExpandVSELECT(SDValue Op); 67 SDValue ExpandLoad(SDValue Op); 68 SDValue ExpandStore(SDValue Op); 69 SDValue ExpandFNEG(SDValue Op); 70 // Implements vector promotion; this is essentially just bitcasting the 71 // operands to a different type and bitcasting the result back to the 72 // original type. 73 SDValue PromoteVectorOp(SDValue Op); 74 75 public: 76 bool Run(); 77 VectorLegalizer(SelectionDAG& dag) : 78 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} 79 }; 80 81 bool VectorLegalizer::Run() { 82 // The legalize process is inherently a bottom-up recursive process (users 83 // legalize their uses before themselves). Given infinite stack space, we 84 // could just start legalizing on the root and traverse the whole graph. In 85 // practice however, this causes us to run out of stack space on large basic 86 // blocks. To avoid this problem, compute an ordering of the nodes where each 87 // node is only legalized after all of its operands are legalized. 88 DAG.AssignTopologicalOrder(); 89 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 90 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 91 LegalizeOp(SDValue(I, 0)); 92 93 // Finally, it's possible the root changed. Get the new root. 94 SDValue OldRoot = DAG.getRoot(); 95 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 96 DAG.setRoot(LegalizedNodes[OldRoot]); 97 98 LegalizedNodes.clear(); 99 100 // Remove dead nodes now. 101 DAG.RemoveDeadNodes(); 102 103 return Changed; 104 } 105 106 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) { 107 // Generic legalization: just pass the operand through. 108 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) 109 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 110 return Result.getValue(Op.getResNo()); 111 } 112 113 SDValue VectorLegalizer::LegalizeOp(SDValue Op) { 114 // Note that LegalizeOp may be reentered even from single-use nodes, which 115 // means that we always must cache transformed nodes. 116 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 117 if (I != LegalizedNodes.end()) return I->second; 118 119 SDNode* Node = Op.getNode(); 120 121 // Legalize the operands 122 SmallVector<SDValue, 8> Ops; 123 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 124 Ops.push_back(LegalizeOp(Node->getOperand(i))); 125 126 SDValue Result = 127 SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0); 128 129 if (Op.getOpcode() == ISD::LOAD) { 130 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); 131 ISD::LoadExtType ExtType = LD->getExtensionType(); 132 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { 133 if (TLI.isLoadExtLegal(LD->getExtensionType(), LD->getMemoryVT())) 134 return TranslateLegalizeResults(Op, Result); 135 Changed = true; 136 return LegalizeOp(ExpandLoad(Op)); 137 } 138 } else if (Op.getOpcode() == ISD::STORE) { 139 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode()); 140 EVT StVT = ST->getMemoryVT(); 141 EVT ValVT = ST->getValue().getValueType(); 142 if (StVT.isVector() && ST->isTruncatingStore()) 143 switch (TLI.getTruncStoreAction(ValVT, StVT)) { 144 default: llvm_unreachable("This action is not supported yet!"); 145 case TargetLowering::Legal: 146 return TranslateLegalizeResults(Op, Result); 147 case TargetLowering::Custom: 148 Changed = true; 149 return LegalizeOp(TLI.LowerOperation(Result, DAG)); 150 case TargetLowering::Expand: 151 Changed = true; 152 return LegalizeOp(ExpandStore(Op)); 153 } 154 } 155 156 bool HasVectorValue = false; 157 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end(); 158 J != E; 159 ++J) 160 HasVectorValue |= J->isVector(); 161 if (!HasVectorValue) 162 return TranslateLegalizeResults(Op, Result); 163 164 EVT QueryType; 165 switch (Op.getOpcode()) { 166 default: 167 return TranslateLegalizeResults(Op, Result); 168 case ISD::ADD: 169 case ISD::SUB: 170 case ISD::MUL: 171 case ISD::SDIV: 172 case ISD::UDIV: 173 case ISD::SREM: 174 case ISD::UREM: 175 case ISD::FADD: 176 case ISD::FSUB: 177 case ISD::FMUL: 178 case ISD::FDIV: 179 case ISD::FREM: 180 case ISD::AND: 181 case ISD::OR: 182 case ISD::XOR: 183 case ISD::SHL: 184 case ISD::SRA: 185 case ISD::SRL: 186 case ISD::ROTL: 187 case ISD::ROTR: 188 case ISD::CTLZ: 189 case ISD::CTTZ: 190 case ISD::CTLZ_ZERO_UNDEF: 191 case ISD::CTTZ_ZERO_UNDEF: 192 case ISD::CTPOP: 193 case ISD::SELECT: 194 case ISD::VSELECT: 195 case ISD::SELECT_CC: 196 case ISD::SETCC: 197 case ISD::ZERO_EXTEND: 198 case ISD::ANY_EXTEND: 199 case ISD::TRUNCATE: 200 case ISD::SIGN_EXTEND: 201 case ISD::FP_TO_SINT: 202 case ISD::FP_TO_UINT: 203 case ISD::FNEG: 204 case ISD::FABS: 205 case ISD::FSQRT: 206 case ISD::FSIN: 207 case ISD::FCOS: 208 case ISD::FPOWI: 209 case ISD::FPOW: 210 case ISD::FLOG: 211 case ISD::FLOG2: 212 case ISD::FLOG10: 213 case ISD::FEXP: 214 case ISD::FEXP2: 215 case ISD::FCEIL: 216 case ISD::FTRUNC: 217 case ISD::FRINT: 218 case ISD::FNEARBYINT: 219 case ISD::FFLOOR: 220 case ISD::SIGN_EXTEND_INREG: 221 QueryType = Node->getValueType(0); 222 break; 223 case ISD::FP_ROUND_INREG: 224 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 225 break; 226 case ISD::SINT_TO_FP: 227 case ISD::UINT_TO_FP: 228 QueryType = Node->getOperand(0).getValueType(); 229 break; 230 } 231 232 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) { 233 case TargetLowering::Promote: 234 // "Promote" the operation by bitcasting 235 Result = PromoteVectorOp(Op); 236 Changed = true; 237 break; 238 case TargetLowering::Legal: break; 239 case TargetLowering::Custom: { 240 SDValue Tmp1 = TLI.LowerOperation(Op, DAG); 241 if (Tmp1.getNode()) { 242 Result = Tmp1; 243 break; 244 } 245 // FALL THROUGH 246 } 247 case TargetLowering::Expand: 248 if (Node->getOpcode() == ISD::VSELECT) 249 Result = ExpandVSELECT(Op); 250 else if (Node->getOpcode() == ISD::UINT_TO_FP) 251 Result = ExpandUINT_TO_FLOAT(Op); 252 else if (Node->getOpcode() == ISD::FNEG) 253 Result = ExpandFNEG(Op); 254 else if (Node->getOpcode() == ISD::SETCC) 255 Result = UnrollVSETCC(Op); 256 else 257 Result = DAG.UnrollVectorOp(Op.getNode()); 258 break; 259 } 260 261 // Make sure that the generated code is itself legal. 262 if (Result != Op) { 263 Result = LegalizeOp(Result); 264 Changed = true; 265 } 266 267 // Note that LegalizeOp may be reentered even from single-use nodes, which 268 // means that we always must cache transformed nodes. 269 AddLegalizedOperand(Op, Result); 270 return Result; 271 } 272 273 SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) { 274 // Vector "promotion" is basically just bitcasting and doing the operation 275 // in a different type. For example, x86 promotes ISD::AND on v2i32 to 276 // v1i64. 277 EVT VT = Op.getValueType(); 278 assert(Op.getNode()->getNumValues() == 1 && 279 "Can't promote a vector with multiple results!"); 280 EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); 281 DebugLoc dl = Op.getDebugLoc(); 282 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 283 284 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 285 if (Op.getOperand(j).getValueType().isVector()) 286 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); 287 else 288 Operands[j] = Op.getOperand(j); 289 } 290 291 Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size()); 292 293 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 294 } 295 296 297 SDValue VectorLegalizer::ExpandLoad(SDValue Op) { 298 DebugLoc dl = Op.getDebugLoc(); 299 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); 300 SDValue Chain = LD->getChain(); 301 SDValue BasePTR = LD->getBasePtr(); 302 EVT SrcVT = LD->getMemoryVT(); 303 ISD::LoadExtType ExtType = LD->getExtensionType(); 304 305 SmallVector<SDValue, 8> LoadVals; 306 SmallVector<SDValue, 8> LoadChains; 307 unsigned NumElem = SrcVT.getVectorNumElements(); 308 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8; 309 310 for (unsigned Idx=0; Idx<NumElem; Idx++) { 311 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl, 312 Op.getNode()->getValueType(0).getScalarType(), 313 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride), 314 SrcVT.getScalarType(), 315 LD->isVolatile(), LD->isNonTemporal(), 316 LD->getAlignment()); 317 318 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, 319 DAG.getIntPtrConstant(Stride)); 320 321 LoadVals.push_back(ScalarLoad.getValue(0)); 322 LoadChains.push_back(ScalarLoad.getValue(1)); 323 } 324 325 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 326 &LoadChains[0], LoadChains.size()); 327 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, 328 Op.getNode()->getValueType(0), &LoadVals[0], LoadVals.size()); 329 330 AddLegalizedOperand(Op.getValue(0), Value); 331 AddLegalizedOperand(Op.getValue(1), NewChain); 332 333 return (Op.getResNo() ? NewChain : Value); 334 } 335 336 SDValue VectorLegalizer::ExpandStore(SDValue Op) { 337 DebugLoc dl = Op.getDebugLoc(); 338 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode()); 339 SDValue Chain = ST->getChain(); 340 SDValue BasePTR = ST->getBasePtr(); 341 SDValue Value = ST->getValue(); 342 EVT StVT = ST->getMemoryVT(); 343 344 unsigned Alignment = ST->getAlignment(); 345 bool isVolatile = ST->isVolatile(); 346 bool isNonTemporal = ST->isNonTemporal(); 347 348 unsigned NumElem = StVT.getVectorNumElements(); 349 // The type of the data we want to save 350 EVT RegVT = Value.getValueType(); 351 EVT RegSclVT = RegVT.getScalarType(); 352 // The type of data as saved in memory. 353 EVT MemSclVT = StVT.getScalarType(); 354 355 // Cast floats into integers 356 unsigned ScalarSize = MemSclVT.getSizeInBits(); 357 358 // Round odd types to the next pow of two. 359 if (!isPowerOf2_32(ScalarSize)) 360 ScalarSize = NextPowerOf2(ScalarSize); 361 362 // Store Stride in bytes 363 unsigned Stride = ScalarSize/8; 364 // Extract each of the elements from the original vector 365 // and save them into memory individually. 366 SmallVector<SDValue, 8> Stores; 367 for (unsigned Idx = 0; Idx < NumElem; Idx++) { 368 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 369 RegSclVT, Value, DAG.getIntPtrConstant(Idx)); 370 371 // This scalar TruncStore may be illegal, but we legalize it later. 372 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR, 373 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT, 374 isVolatile, isNonTemporal, Alignment); 375 376 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, 377 DAG.getIntPtrConstant(Stride)); 378 379 Stores.push_back(Store); 380 } 381 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 382 &Stores[0], Stores.size()); 383 AddLegalizedOperand(Op, TF); 384 return TF; 385 } 386 387 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) { 388 // Implement VSELECT in terms of XOR, AND, OR 389 // on platforms which do not support blend natively. 390 EVT VT = Op.getOperand(0).getValueType(); 391 DebugLoc DL = Op.getDebugLoc(); 392 393 SDValue Mask = Op.getOperand(0); 394 SDValue Op1 = Op.getOperand(1); 395 SDValue Op2 = Op.getOperand(2); 396 397 // If we can't even use the basic vector operations of 398 // AND,OR,XOR, we will have to scalarize the op. 399 // Notice that the operation may be 'promoted' which means that it is 400 // 'bitcasted' to another type which is handled. 401 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand || 402 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand || 403 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand) 404 return DAG.UnrollVectorOp(Op.getNode()); 405 406 assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits() 407 && "Invalid mask size"); 408 // Bitcast the operands to be the same type as the mask. 409 // This is needed when we select between FP types because 410 // the mask is a vector of integers. 411 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); 412 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); 413 414 SDValue AllOnes = DAG.getConstant( 415 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT); 416 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); 417 418 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); 419 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); 420 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); 421 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); 422 } 423 424 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) { 425 EVT VT = Op.getOperand(0).getValueType(); 426 DebugLoc DL = Op.getDebugLoc(); 427 428 // Make sure that the SINT_TO_FP and SRL instructions are available. 429 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || 430 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) 431 return DAG.UnrollVectorOp(Op.getNode()); 432 433 EVT SVT = VT.getScalarType(); 434 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) && 435 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide"); 436 437 unsigned BW = SVT.getSizeInBits(); 438 SDValue HalfWord = DAG.getConstant(BW/2, VT); 439 440 // Constants to clear the upper part of the word. 441 // Notice that we can also use SHL+SHR, but using a constant is slightly 442 // faster on x86. 443 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF; 444 SDValue HalfWordMask = DAG.getConstant(HWMask, VT); 445 446 // Two to the power of half-word-size. 447 SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType()); 448 449 // Clear upper part of LO, lower HI 450 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord); 451 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask); 452 453 // Convert hi and lo to floats 454 // Convert the hi part back to the upper values 455 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); 456 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW); 457 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO); 458 459 // Add the two halves 460 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO); 461 } 462 463 464 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) { 465 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { 466 SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType()); 467 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 468 Zero, Op.getOperand(0)); 469 } 470 return DAG.UnrollVectorOp(Op.getNode()); 471 } 472 473 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) { 474 EVT VT = Op.getValueType(); 475 unsigned NumElems = VT.getVectorNumElements(); 476 EVT EltVT = VT.getVectorElementType(); 477 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2); 478 EVT TmpEltVT = LHS.getValueType().getVectorElementType(); 479 DebugLoc dl = Op.getDebugLoc(); 480 SmallVector<SDValue, 8> Ops(NumElems); 481 for (unsigned i = 0; i < NumElems; ++i) { 482 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, 483 DAG.getIntPtrConstant(i)); 484 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, 485 DAG.getIntPtrConstant(i)); 486 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT), 487 LHSElem, RHSElem, CC); 488 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], 489 DAG.getConstant(APInt::getAllOnesValue 490 (EltVT.getSizeInBits()), EltVT), 491 DAG.getConstant(0, EltVT)); 492 } 493 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems); 494 } 495 496 } 497 498 bool SelectionDAG::LegalizeVectors() { 499 return VectorLegalizer(*this).Run(); 500 } 501
