1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines interfaces to access the target independent code generation 11 // passes provided by the LLVM backend. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_PASSES_H 16 #define LLVM_CODEGEN_PASSES_H 17 18 #include "llvm/Pass.h" 19 #include "llvm/Target/TargetMachine.h" 20 #include <string> 21 22 namespace llvm { 23 24 class FunctionPass; 25 class MachineFunctionPass; 26 class PassInfo; 27 class TargetLowering; 28 class TargetRegisterClass; 29 class raw_ostream; 30 } 31 32 namespace llvm { 33 34 extern char &NoPassID; // Allow targets to choose not to run a pass. 35 36 class PassConfigImpl; 37 38 /// Target-Independent Code Generator Pass Configuration Options. 39 /// 40 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options 41 /// to the internals of other CodeGen passes. 42 class TargetPassConfig : public ImmutablePass { 43 public: 44 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they 45 /// are unregistered pass IDs. They are only useful for use with 46 /// TargetPassConfig APIs to identify multiple occurrences of the same pass. 47 /// 48 49 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early 50 /// during codegen, on SSA form. 51 static char EarlyTailDuplicateID; 52 53 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine 54 /// optimization after regalloc. 55 static char PostRAMachineLICMID; 56 57 protected: 58 TargetMachine *TM; 59 PassManagerBase &PM; 60 PassConfigImpl *Impl; // Internal data structures 61 bool Initialized; // Flagged after all passes are configured. 62 63 // Target Pass Options 64 // Targets provide a default setting, user flags override. 65 // 66 bool DisableVerify; 67 68 /// Default setting for -enable-tail-merge on this target. 69 bool EnableTailMerge; 70 71 public: 72 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm); 73 // Dummy constructor. 74 TargetPassConfig(); 75 76 virtual ~TargetPassConfig(); 77 78 static char ID; 79 80 /// Get the right type of TargetMachine for this target. 81 template<typename TMC> TMC &getTM() const { 82 return *static_cast<TMC*>(TM); 83 } 84 85 const TargetLowering *getTargetLowering() const { 86 return TM->getTargetLowering(); 87 } 88 89 // 90 void setInitialized() { Initialized = true; } 91 92 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } 93 94 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); } 95 96 bool getEnableTailMerge() const { return EnableTailMerge; } 97 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); } 98 99 /// Allow the target to override a specific pass without overriding the pass 100 /// pipeline. When passes are added to the standard pipeline at the 101 /// point where StadardID is expected, add TargetID in its place. 102 void substitutePass(char &StandardID, char &TargetID); 103 104 /// Allow the target to enable a specific standard pass by default. 105 void enablePass(char &ID) { substitutePass(ID, ID); } 106 107 /// Allow the target to disable a specific standard pass by default. 108 void disablePass(char &ID) { substitutePass(ID, NoPassID); } 109 110 /// Return the pass ssubtituted for StandardID by the target. 111 /// If no substitution exists, return StandardID. 112 AnalysisID getPassSubstitution(AnalysisID StandardID) const; 113 114 /// Return true if the optimized regalloc pipeline is enabled. 115 bool getOptimizeRegAlloc() const; 116 117 /// Add common target configurable passes that perform LLVM IR to IR 118 /// transforms following machine independent optimization. 119 virtual void addIRPasses(); 120 121 /// Add common passes that perform LLVM IR to IR transforms in preparation for 122 /// instruction selection. 123 virtual void addISelPrepare(); 124 125 /// addInstSelector - This method should install an instruction selector pass, 126 /// which converts from LLVM code to machine instructions. 127 virtual bool addInstSelector() { 128 return true; 129 } 130 131 /// Add the complete, standard set of LLVM CodeGen passes. 132 /// Fully developed targets will not generally override this. 133 virtual void addMachinePasses(); 134 135 protected: 136 // Helper to verify the analysis is really immutable. 137 void setOpt(bool &Opt, bool Val); 138 139 /// Methods with trivial inline returns are convenient points in the common 140 /// codegen pass pipeline where targets may insert passes. Methods with 141 /// out-of-line standard implementations are major CodeGen stages called by 142 /// addMachinePasses. Some targets may override major stages when inserting 143 /// passes is insufficient, but maintaining overriden stages is more work. 144 /// 145 146 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM 147 /// passes (which are run just before instruction selector). 148 virtual bool addPreISel() { 149 return true; 150 } 151 152 /// addMachineSSAOptimization - Add standard passes that optimize machine 153 /// instructions in SSA form. 154 virtual void addMachineSSAOptimization(); 155 156 /// addPreRegAlloc - This method may be implemented by targets that want to 157 /// run passes immediately before register allocation. This should return 158 /// true if -print-machineinstrs should print after these passes. 159 virtual bool addPreRegAlloc() { 160 return false; 161 } 162 163 /// createTargetRegisterAllocator - Create the register allocator pass for 164 /// this target at the current optimization level. 165 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized); 166 167 /// addFastRegAlloc - Add the minimum set of target-independent passes that 168 /// are required for fast register allocation. 169 virtual void addFastRegAlloc(FunctionPass *RegAllocPass); 170 171 /// addOptimizedRegAlloc - Add passes related to register allocation. 172 /// LLVMTargetMachine provides standard regalloc passes for most targets. 173 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); 174 175 /// addFinalizeRegAlloc - This method may be implemented by targets that want 176 /// to run passes within the regalloc pipeline, immediately after the register 177 /// allocation pass itself. These passes run as soon as virtual regisiters 178 /// have been rewritten to physical registers but before and other postRA 179 /// optimization happens. Targets that have marked instructions for bundling 180 /// must have finalized those bundles by the time these passes have run, 181 /// because subsequent passes are not guaranteed to be bundle-aware. 182 virtual bool addFinalizeRegAlloc() { 183 return false; 184 } 185 186 /// addPostRegAlloc - This method may be implemented by targets that want to 187 /// run passes after register allocation pass pipeline but before 188 /// prolog-epilog insertion. This should return true if -print-machineinstrs 189 /// should print after these passes. 190 virtual bool addPostRegAlloc() { 191 return false; 192 } 193 194 /// Add passes that optimize machine instructions after register allocation. 195 virtual void addMachineLateOptimization(); 196 197 /// addPreSched2 - This method may be implemented by targets that want to 198 /// run passes after prolog-epilog insertion and before the second instruction 199 /// scheduling pass. This should return true if -print-machineinstrs should 200 /// print after these passes. 201 virtual bool addPreSched2() { 202 return false; 203 } 204 205 /// Add standard basic block placement passes. 206 virtual void addBlockPlacement(); 207 208 /// addPreEmitPass - This pass may be implemented by targets that want to run 209 /// passes immediately before machine code is emitted. This should return 210 /// true if -print-machineinstrs should print out the code after the passes. 211 virtual bool addPreEmitPass() { 212 return false; 213 } 214 215 /// Utilities for targets to add passes to the pass manager. 216 /// 217 218 /// Add a CodeGen pass at this point in the pipeline after checking overrides. 219 /// Return the pass that was added, or NoPassID. 220 AnalysisID addPass(char &ID); 221 222 /// addMachinePasses helper to create the target-selected or overriden 223 /// regalloc pass. 224 FunctionPass *createRegAllocPass(bool Optimized); 225 226 /// printAndVerify - Add a pass to dump then verify the machine function, if 227 /// those steps are enabled. 228 /// 229 void printAndVerify(const char *Banner) const; 230 }; 231 } // namespace llvm 232 233 /// List of target independent CodeGen pass IDs. 234 namespace llvm { 235 /// createUnreachableBlockEliminationPass - The LLVM code generator does not 236 /// work well with unreachable basic blocks (what live ranges make sense for a 237 /// block that cannot be reached?). As such, a code generator should either 238 /// not instruction select unreachable blocks, or run this pass as its 239 /// last LLVM modifying pass to clean up blocks that are not reachable from 240 /// the entry block. 241 FunctionPass *createUnreachableBlockEliminationPass(); 242 243 /// MachineFunctionPrinter pass - This pass prints out the machine function to 244 /// the given stream as a debugging tool. 245 MachineFunctionPass * 246 createMachineFunctionPrinterPass(raw_ostream &OS, 247 const std::string &Banner =""); 248 249 /// MachineLoopInfo - This pass is a loop analysis pass. 250 extern char &MachineLoopInfoID; 251 252 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis. 253 extern char &MachineLoopRangesID; 254 255 /// MachineDominators - This pass is a machine dominators analysis pass. 256 extern char &MachineDominatorsID; 257 258 /// EdgeBundles analysis - Bundle machine CFG edges. 259 extern char &EdgeBundlesID; 260 261 /// LiveVariables pass - This pass computes the set of blocks in which each 262 /// variable is life and sets machine operand kill flags. 263 extern char &LiveVariablesID; 264 265 /// PHIElimination - This pass eliminates machine instruction PHI nodes 266 /// by inserting copy instructions. This destroys SSA information, but is the 267 /// desired input for some register allocators. This pass is "required" by 268 /// these register allocator like this: AU.addRequiredID(PHIEliminationID); 269 extern char &PHIEliminationID; 270 271 /// StrongPHIElimination - This pass eliminates machine instruction PHI 272 /// nodes by inserting copy instructions. This destroys SSA information, but 273 /// is the desired input for some register allocators. This pass is 274 /// "required" by these register allocator like this: 275 /// AU.addRequiredID(PHIEliminationID); 276 /// This pass is still in development 277 extern char &StrongPHIEliminationID; 278 279 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots. 280 extern char &LiveStacksID; 281 282 /// TwoAddressInstruction - This pass reduces two-address instructions to 283 /// use two operands. This destroys SSA information but it is desired by 284 /// register allocators. 285 extern char &TwoAddressInstructionPassID; 286 287 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. 288 extern char &ProcessImplicitDefsID; 289 290 /// RegisterCoalescer - This pass merges live ranges to eliminate copies. 291 extern char &RegisterCoalescerID; 292 293 /// MachineScheduler - This pass schedules machine instructions. 294 extern char &MachineSchedulerID; 295 296 /// SpillPlacement analysis. Suggest optimal placement of spill code between 297 /// basic blocks. 298 extern char &SpillPlacementID; 299 300 /// UnreachableMachineBlockElimination - This pass removes unreachable 301 /// machine basic blocks. 302 extern char &UnreachableMachineBlockElimID; 303 304 /// DeadMachineInstructionElim - This pass removes dead machine instructions. 305 extern char &DeadMachineInstructionElimID; 306 307 /// FastRegisterAllocation Pass - This pass register allocates as fast as 308 /// possible. It is best suited for debug code where live ranges are short. 309 /// 310 FunctionPass *createFastRegisterAllocator(); 311 312 /// BasicRegisterAllocation Pass - This pass implements a degenerate global 313 /// register allocator using the basic regalloc framework. 314 /// 315 FunctionPass *createBasicRegisterAllocator(); 316 317 /// Greedy register allocation pass - This pass implements a global register 318 /// allocator for optimized builds. 319 /// 320 FunctionPass *createGreedyRegisterAllocator(); 321 322 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean 323 /// Quadratic Prograaming (PBQP) based register allocator. 324 /// 325 FunctionPass *createDefaultPBQPRegisterAllocator(); 326 327 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code, 328 /// and eliminates abstract frame references. 329 extern char &PrologEpilogCodeInserterID; 330 331 /// ExpandPostRAPseudos - This pass expands pseudo instructions after 332 /// register allocation. 333 extern char &ExpandPostRAPseudosID; 334 335 /// createPostRAScheduler - This pass performs post register allocation 336 /// scheduling. 337 extern char &PostRASchedulerID; 338 339 /// BranchFolding - This pass performs machine code CFG based 340 /// optimizations to delete branches to branches, eliminate branches to 341 /// successor blocks (creating fall throughs), and eliminating branches over 342 /// branches. 343 extern char &BranchFolderPassID; 344 345 /// TailDuplicate - Duplicate blocks with unconditional branches 346 /// into tails of their predecessors. 347 extern char &TailDuplicateID; 348 349 /// IfConverter - This pass performs machine code if conversion. 350 extern char &IfConverterID; 351 352 /// MachineBlockPlacement - This pass places basic blocks based on branch 353 /// probabilities. 354 extern char &MachineBlockPlacementID; 355 356 /// MachineBlockPlacementStats - This pass collects statistics about the 357 /// basic block placement using branch probabilities and block frequency 358 /// information. 359 extern char &MachineBlockPlacementStatsID; 360 361 /// Code Placement - This pass optimize code placement and aligns loop 362 /// headers to target specific alignment boundary. 363 extern char &CodePlacementOptID; 364 365 /// GCLowering Pass - Performs target-independent LLVM IR transformations for 366 /// highly portable strategies. 367 /// 368 FunctionPass *createGCLoweringPass(); 369 370 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points 371 /// in machine code. Must be added very late during code generation, just 372 /// prior to output, and importantly after all CFG transformations (such as 373 /// branch folding). 374 extern char &GCMachineCodeAnalysisID; 375 376 /// Deleter Pass - Releases GC metadata. 377 /// 378 FunctionPass *createGCInfoDeleter(); 379 380 /// Creates a pass to print GC metadata. 381 /// 382 FunctionPass *createGCInfoPrinter(raw_ostream &OS); 383 384 /// MachineCSE - This pass performs global CSE on machine instructions. 385 extern char &MachineCSEID; 386 387 /// MachineLICM - This pass performs LICM on machine instructions. 388 extern char &MachineLICMID; 389 390 /// MachineSinking - This pass performs sinking on machine instructions. 391 extern char &MachineSinkingID; 392 393 /// MachineCopyPropagation - This pass performs copy propagation on 394 /// machine instructions. 395 extern char &MachineCopyPropagationID; 396 397 /// PeepholeOptimizer - This pass performs peephole optimizations - 398 /// like extension and comparison eliminations. 399 extern char &PeepholeOptimizerID; 400 401 /// OptimizePHIs - This pass optimizes machine instruction PHIs 402 /// to take advantage of opportunities created during DAG legalization. 403 extern char &OptimizePHIsID; 404 405 /// StackSlotColoring - This pass performs stack slot coloring. 406 extern char &StackSlotColoringID; 407 408 /// createStackProtectorPass - This pass adds stack protectors to functions. 409 /// 410 FunctionPass *createStackProtectorPass(const TargetLowering *tli); 411 412 /// createMachineVerifierPass - This pass verifies cenerated machine code 413 /// instructions for correctness. 414 /// 415 FunctionPass *createMachineVerifierPass(const char *Banner = 0); 416 417 /// createDwarfEHPass - This pass mulches exception handling code into a form 418 /// adapted to code generation. Required if using dwarf exception handling. 419 FunctionPass *createDwarfEHPass(const TargetMachine *tm); 420 421 /// createSjLjEHPreparePass - This pass adapts exception handling code to use 422 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. 423 /// 424 FunctionPass *createSjLjEHPreparePass(const TargetLowering *tli); 425 426 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack 427 /// slots relative to one another and allocates base registers to access them 428 /// when it is estimated by the target to be out of range of normal frame 429 /// pointer or stack pointer index addressing. 430 extern char &LocalStackSlotAllocationID; 431 432 /// ExpandISelPseudos - This pass expands pseudo-instructions. 433 extern char &ExpandISelPseudosID; 434 435 /// createExecutionDependencyFixPass - This pass fixes execution time 436 /// problems with dependent instructions, such as switching execution 437 /// domains to match. 438 /// 439 /// The pass will examine instructions using and defining registers in RC. 440 /// 441 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC); 442 443 /// UnpackMachineBundles - This pass unpack machine instruction bundles. 444 extern char &UnpackMachineBundlesID; 445 446 /// FinalizeMachineBundles - This pass finalize machine instruction 447 /// bundles (created earlier, e.g. during pre-RA scheduling). 448 extern char &FinalizeMachineBundlesID; 449 450 } // End llvm namespace 451 452 #endif 453
