1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86DisassemblerShared.h" 18 #include "X86RecognizableInstr.h" 19 #include "X86ModRMFilters.h" 20 21 #include "llvm/Support/ErrorHandling.h" 22 23 #include <string> 24 25 using namespace llvm; 26 27 #define MRM_MAPPING \ 28 MAP(C1, 33) \ 29 MAP(C2, 34) \ 30 MAP(C3, 35) \ 31 MAP(C4, 36) \ 32 MAP(C8, 37) \ 33 MAP(C9, 38) \ 34 MAP(E8, 39) \ 35 MAP(F0, 40) \ 36 MAP(F8, 41) \ 37 MAP(F9, 42) \ 38 MAP(D0, 45) \ 39 MAP(D1, 46) \ 40 MAP(D4, 47) \ 41 MAP(D8, 48) \ 42 MAP(D9, 49) \ 43 MAP(DA, 50) \ 44 MAP(DB, 51) \ 45 MAP(DC, 52) \ 46 MAP(DD, 53) \ 47 MAP(DE, 54) \ 48 MAP(DF, 55) 49 50 // A clone of X86 since we can't depend on something that is generated. 51 namespace X86Local { 52 enum { 53 Pseudo = 0, 54 RawFrm = 1, 55 AddRegFrm = 2, 56 MRMDestReg = 3, 57 MRMDestMem = 4, 58 MRMSrcReg = 5, 59 MRMSrcMem = 6, 60 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, 61 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, 62 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, 63 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, 64 MRMInitReg = 32, 65 #define MAP(from, to) MRM_##from = to, 66 MRM_MAPPING 67 #undef MAP 68 RawFrmImm8 = 43, 69 RawFrmImm16 = 44, 70 lastMRM 71 }; 72 73 enum { 74 TB = 1, 75 REP = 2, 76 D8 = 3, D9 = 4, DA = 5, DB = 6, 77 DC = 7, DD = 8, DE = 9, DF = 10, 78 XD = 11, XS = 12, 79 T8 = 13, P_TA = 14, 80 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19 81 }; 82 } 83 84 // If rows are added to the opcode extension tables, then corresponding entries 85 // must be added here. 86 // 87 // If the row corresponds to a single byte (i.e., 8f), then add an entry for 88 // that byte to ONE_BYTE_EXTENSION_TABLES. 89 // 90 // If the row corresponds to two bytes where the first is 0f, add an entry for 91 // the second byte to TWO_BYTE_EXTENSION_TABLES. 92 // 93 // If the row corresponds to some other set of bytes, you will need to modify 94 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes 95 // to the X86 TD files, except in two cases: if the first two bytes of such a 96 // new combination are 0f 38 or 0f 3a, you just have to add maps called 97 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a 98 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line 99 // in RecognizableInstr::emitDecodePath(). 100 101 #define ONE_BYTE_EXTENSION_TABLES \ 102 EXTENSION_TABLE(80) \ 103 EXTENSION_TABLE(81) \ 104 EXTENSION_TABLE(82) \ 105 EXTENSION_TABLE(83) \ 106 EXTENSION_TABLE(8f) \ 107 EXTENSION_TABLE(c0) \ 108 EXTENSION_TABLE(c1) \ 109 EXTENSION_TABLE(c6) \ 110 EXTENSION_TABLE(c7) \ 111 EXTENSION_TABLE(d0) \ 112 EXTENSION_TABLE(d1) \ 113 EXTENSION_TABLE(d2) \ 114 EXTENSION_TABLE(d3) \ 115 EXTENSION_TABLE(f6) \ 116 EXTENSION_TABLE(f7) \ 117 EXTENSION_TABLE(fe) \ 118 EXTENSION_TABLE(ff) 119 120 #define TWO_BYTE_EXTENSION_TABLES \ 121 EXTENSION_TABLE(00) \ 122 EXTENSION_TABLE(01) \ 123 EXTENSION_TABLE(18) \ 124 EXTENSION_TABLE(71) \ 125 EXTENSION_TABLE(72) \ 126 EXTENSION_TABLE(73) \ 127 EXTENSION_TABLE(ae) \ 128 EXTENSION_TABLE(ba) \ 129 EXTENSION_TABLE(c7) 130 131 #define THREE_BYTE_38_EXTENSION_TABLES \ 132 EXTENSION_TABLE(F3) 133 134 using namespace X86Disassembler; 135 136 /// needsModRMForDecode - Indicates whether a particular instruction requires a 137 /// ModR/M byte for the instruction to be properly decoded. For example, a 138 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to 139 /// 0b11. 140 /// 141 /// @param form - The form of the instruction. 142 /// @return - true if the form implies that a ModR/M byte is required, false 143 /// otherwise. 144 static bool needsModRMForDecode(uint8_t form) { 145 if (form == X86Local::MRMDestReg || 146 form == X86Local::MRMDestMem || 147 form == X86Local::MRMSrcReg || 148 form == X86Local::MRMSrcMem || 149 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) || 150 (form >= X86Local::MRM0m && form <= X86Local::MRM7m)) 151 return true; 152 else 153 return false; 154 } 155 156 /// isRegFormat - Indicates whether a particular form requires the Mod field of 157 /// the ModR/M byte to be 0b11. 158 /// 159 /// @param form - The form of the instruction. 160 /// @return - true if the form implies that Mod must be 0b11, false 161 /// otherwise. 162 static bool isRegFormat(uint8_t form) { 163 if (form == X86Local::MRMDestReg || 164 form == X86Local::MRMSrcReg || 165 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)) 166 return true; 167 else 168 return false; 169 } 170 171 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 172 /// Useful for switch statements and the like. 173 /// 174 /// @param init - A reference to the BitsInit to be decoded. 175 /// @return - The field, with the first bit in the BitsInit as the lowest 176 /// order bit. 177 static uint8_t byteFromBitsInit(BitsInit &init) { 178 int width = init.getNumBits(); 179 180 assert(width <= 8 && "Field is too large for uint8_t!"); 181 182 int index; 183 uint8_t mask = 0x01; 184 185 uint8_t ret = 0; 186 187 for (index = 0; index < width; index++) { 188 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 189 ret |= mask; 190 191 mask <<= 1; 192 } 193 194 return ret; 195 } 196 197 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 198 /// name of the field. 199 /// 200 /// @param rec - The record from which to extract the value. 201 /// @param name - The name of the field in the record. 202 /// @return - The field, as translated by byteFromBitsInit(). 203 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 204 BitsInit* bits = rec->getValueAsBitsInit(name); 205 return byteFromBitsInit(*bits); 206 } 207 208 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 209 const CodeGenInstruction &insn, 210 InstrUID uid) { 211 UID = uid; 212 213 Rec = insn.TheDef; 214 Name = Rec->getName(); 215 Spec = &tables.specForUID(UID); 216 217 if (!Rec->isSubClassOf("X86Inst")) { 218 ShouldBeEmitted = false; 219 return; 220 } 221 222 Prefix = byteFromRec(Rec, "Prefix"); 223 Opcode = byteFromRec(Rec, "Opcode"); 224 Form = byteFromRec(Rec, "FormBits"); 225 SegOvr = byteFromRec(Rec, "SegOvrBits"); 226 227 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix"); 228 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix"); 229 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 230 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix"); 231 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix"); 232 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix"); 233 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix"); 234 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix"); 235 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 236 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); 237 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 238 239 Name = Rec->getName(); 240 AsmString = Rec->getValueAsString("AsmString"); 241 242 Operands = &insn.Operands.OperandList; 243 244 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) || 245 (Name.find("CRC32") != Name.npos); 246 HasFROperands = hasFROperands(); 247 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L"); 248 249 // Check for 64-bit inst which does not require REX 250 Is32Bit = false; 251 Is64Bit = false; 252 // FIXME: Is there some better way to check for In64BitMode? 253 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 254 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 255 if (Predicates[i]->getName().find("32Bit") != Name.npos) { 256 Is32Bit = true; 257 break; 258 } 259 if (Predicates[i]->getName().find("64Bit") != Name.npos) { 260 Is64Bit = true; 261 break; 262 } 263 } 264 // FIXME: These instructions aren't marked as 64-bit in any way 265 Is64Bit |= Rec->getName() == "JMP64pcrel32" || 266 Rec->getName() == "MASKMOVDQU64" || 267 Rec->getName() == "POPFS64" || 268 Rec->getName() == "POPGS64" || 269 Rec->getName() == "PUSHFS64" || 270 Rec->getName() == "PUSHGS64" || 271 Rec->getName() == "REX64_PREFIX" || 272 Rec->getName().find("MOV64") != Name.npos || 273 Rec->getName().find("PUSH64") != Name.npos || 274 Rec->getName().find("POP64") != Name.npos; 275 276 ShouldBeEmitted = true; 277 } 278 279 void RecognizableInstr::processInstr(DisassemblerTables &tables, 280 const CodeGenInstruction &insn, 281 InstrUID uid) 282 { 283 // Ignore "asm parser only" instructions. 284 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 285 return; 286 287 RecognizableInstr recogInstr(tables, insn, uid); 288 289 recogInstr.emitInstructionSpecifier(tables); 290 291 if (recogInstr.shouldBeEmitted()) 292 recogInstr.emitDecodePath(tables); 293 } 294 295 InstructionContext RecognizableInstr::insnContext() const { 296 InstructionContext insnContext; 297 298 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) { 299 if (HasVEX_LPrefix && HasVEX_WPrefix) { 300 if (HasOpSizePrefix) 301 insnContext = IC_VEX_L_W_OPSIZE; 302 else 303 llvm_unreachable("Don't support VEX.L and VEX.W together"); 304 } else if (HasOpSizePrefix && HasVEX_LPrefix) 305 insnContext = IC_VEX_L_OPSIZE; 306 else if (HasOpSizePrefix && HasVEX_WPrefix) 307 insnContext = IC_VEX_W_OPSIZE; 308 else if (HasOpSizePrefix) 309 insnContext = IC_VEX_OPSIZE; 310 else if (HasVEX_LPrefix && 311 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) 312 insnContext = IC_VEX_L_XS; 313 else if (HasVEX_LPrefix && (Prefix == X86Local::XD || 314 Prefix == X86Local::T8XD || 315 Prefix == X86Local::TAXD)) 316 insnContext = IC_VEX_L_XD; 317 else if (HasVEX_WPrefix && 318 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) 319 insnContext = IC_VEX_W_XS; 320 else if (HasVEX_WPrefix && (Prefix == X86Local::XD || 321 Prefix == X86Local::T8XD || 322 Prefix == X86Local::TAXD)) 323 insnContext = IC_VEX_W_XD; 324 else if (HasVEX_WPrefix) 325 insnContext = IC_VEX_W; 326 else if (HasVEX_LPrefix) 327 insnContext = IC_VEX_L; 328 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || 329 Prefix == X86Local::TAXD) 330 insnContext = IC_VEX_XD; 331 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) 332 insnContext = IC_VEX_XS; 333 else 334 insnContext = IC_VEX; 335 } else if (Is64Bit || HasREX_WPrefix) { 336 if (HasREX_WPrefix && HasOpSizePrefix) 337 insnContext = IC_64BIT_REXW_OPSIZE; 338 else if (HasOpSizePrefix && (Prefix == X86Local::XD || 339 Prefix == X86Local::T8XD || 340 Prefix == X86Local::TAXD)) 341 insnContext = IC_64BIT_XD_OPSIZE; 342 else if (HasOpSizePrefix && 343 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) 344 insnContext = IC_64BIT_XS_OPSIZE; 345 else if (HasOpSizePrefix) 346 insnContext = IC_64BIT_OPSIZE; 347 else if (HasAdSizePrefix) 348 insnContext = IC_64BIT_ADSIZE; 349 else if (HasREX_WPrefix && 350 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) 351 insnContext = IC_64BIT_REXW_XS; 352 else if (HasREX_WPrefix && (Prefix == X86Local::XD || 353 Prefix == X86Local::T8XD || 354 Prefix == X86Local::TAXD)) 355 insnContext = IC_64BIT_REXW_XD; 356 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || 357 Prefix == X86Local::TAXD) 358 insnContext = IC_64BIT_XD; 359 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) 360 insnContext = IC_64BIT_XS; 361 else if (HasREX_WPrefix) 362 insnContext = IC_64BIT_REXW; 363 else 364 insnContext = IC_64BIT; 365 } else { 366 if (HasOpSizePrefix && (Prefix == X86Local::XD || 367 Prefix == X86Local::T8XD || 368 Prefix == X86Local::TAXD)) 369 insnContext = IC_XD_OPSIZE; 370 else if (HasOpSizePrefix && 371 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) 372 insnContext = IC_XS_OPSIZE; 373 else if (HasOpSizePrefix) 374 insnContext = IC_OPSIZE; 375 else if (HasAdSizePrefix) 376 insnContext = IC_ADSIZE; 377 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || 378 Prefix == X86Local::TAXD) 379 insnContext = IC_XD; 380 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS || 381 Prefix == X86Local::REP) 382 insnContext = IC_XS; 383 else 384 insnContext = IC; 385 } 386 387 return insnContext; 388 } 389 390 RecognizableInstr::filter_ret RecognizableInstr::filter() const { 391 /////////////////// 392 // FILTER_STRONG 393 // 394 395 // Filter out intrinsics 396 397 if (!Rec->isSubClassOf("X86Inst")) 398 return FILTER_STRONG; 399 400 if (Form == X86Local::Pseudo || 401 (IsCodeGenOnly && Name.find("_REV") == Name.npos)) 402 return FILTER_STRONG; 403 404 if (Form == X86Local::MRMInitReg) 405 return FILTER_STRONG; 406 407 408 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is 409 // printed as a separate "instruction". 410 411 if (Name.find("_Int") != Name.npos || 412 Name.find("Int_") != Name.npos || 413 Name.find("_NOREX") != Name.npos || 414 Name.find("2SDL") != Name.npos) 415 return FILTER_STRONG; 416 417 // Filter out instructions with segment override prefixes. 418 // They're too messy to handle now and we'll special case them if needed. 419 420 if (SegOvr) 421 return FILTER_STRONG; 422 423 // Filter out instructions that can't be printed. 424 425 if (AsmString.size() == 0) 426 return FILTER_STRONG; 427 428 // Filter out instructions with subreg operands. 429 430 if (AsmString.find("subreg") != AsmString.npos) 431 return FILTER_STRONG; 432 433 ///////////////// 434 // FILTER_WEAK 435 // 436 437 438 // Filter out instructions with a LOCK prefix; 439 // prefer forms that do not have the prefix 440 if (HasLockPrefix) 441 return FILTER_WEAK; 442 443 // Filter out alternate forms of AVX instructions 444 if (Name.find("_alt") != Name.npos || 445 Name.find("XrYr") != Name.npos || 446 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) || 447 Name.find("_64mr") != Name.npos || 448 Name.find("Xrr") != Name.npos || 449 Name.find("rr64") != Name.npos) 450 return FILTER_WEAK; 451 452 // Special cases. 453 454 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI") 455 return FILTER_WEAK; 456 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI") 457 return FILTER_WEAK; 458 459 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos) 460 return FILTER_WEAK; 461 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos) 462 return FILTER_WEAK; 463 if (Name.find("Fs") != Name.npos) 464 return FILTER_WEAK; 465 if (Name == "PUSH64i16" || 466 Name == "MOVPQI2QImr" || 467 Name == "VMOVPQI2QImr" || 468 Name == "MMX_MOVD64rrv164" || 469 Name == "MOV64ri64i32" || 470 Name == "VMASKMOVDQU64" || 471 Name == "VEXTRACTPSrr64" || 472 Name == "VMOVQd64rr" || 473 Name == "VMOVQs64rr") 474 return FILTER_WEAK; 475 476 if (HasFROperands && Name.find("MOV") != Name.npos && 477 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || 478 (Name.find("to") != Name.npos))) 479 return FILTER_WEAK; 480 481 return FILTER_NORMAL; 482 } 483 484 bool RecognizableInstr::hasFROperands() const { 485 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 486 unsigned numOperands = OperandList.size(); 487 488 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 489 const std::string &recName = OperandList[operandIndex].Rec->getName(); 490 491 if (recName.find("FR") != recName.npos) 492 return true; 493 } 494 return false; 495 } 496 497 bool RecognizableInstr::has256BitOperands() const { 498 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 499 unsigned numOperands = OperandList.size(); 500 501 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 502 const std::string &recName = OperandList[operandIndex].Rec->getName(); 503 504 if (!recName.compare("VR256") || !recName.compare("f256mem")) { 505 return true; 506 } 507 } 508 return false; 509 } 510 511 void RecognizableInstr::handleOperand( 512 bool optional, 513 unsigned &operandIndex, 514 unsigned &physicalOperandIndex, 515 unsigned &numPhysicalOperands, 516 unsigned *operandMapping, 517 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) { 518 if (optional) { 519 if (physicalOperandIndex >= numPhysicalOperands) 520 return; 521 } else { 522 assert(physicalOperandIndex < numPhysicalOperands); 523 } 524 525 while (operandMapping[operandIndex] != operandIndex) { 526 Spec->operands[operandIndex].encoding = ENCODING_DUP; 527 Spec->operands[operandIndex].type = 528 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 529 ++operandIndex; 530 } 531 532 const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); 533 534 Spec->operands[operandIndex].encoding = encodingFromString(typeName, 535 HasOpSizePrefix); 536 Spec->operands[operandIndex].type = typeFromString(typeName, 537 IsSSE, 538 HasREX_WPrefix, 539 HasOpSizePrefix); 540 541 ++operandIndex; 542 ++physicalOperandIndex; 543 } 544 545 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { 546 Spec->name = Name; 547 548 if (!Rec->isSubClassOf("X86Inst")) 549 return; 550 551 switch (filter()) { 552 case FILTER_WEAK: 553 Spec->filtered = true; 554 break; 555 case FILTER_STRONG: 556 ShouldBeEmitted = false; 557 return; 558 case FILTER_NORMAL: 559 break; 560 } 561 562 Spec->insnContext = insnContext(); 563 564 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 565 566 unsigned operandIndex; 567 unsigned numOperands = OperandList.size(); 568 unsigned numPhysicalOperands = 0; 569 570 // operandMapping maps from operands in OperandList to their originals. 571 // If operandMapping[i] != i, then the entry is a duplicate. 572 unsigned operandMapping[X86_MAX_OPERANDS]; 573 574 bool hasFROperands = false; 575 576 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 577 578 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 579 if (OperandList[operandIndex].Constraints.size()) { 580 const CGIOperandList::ConstraintInfo &Constraint = 581 OperandList[operandIndex].Constraints[0]; 582 if (Constraint.isTied()) { 583 operandMapping[operandIndex] = Constraint.getTiedOperand(); 584 } else { 585 ++numPhysicalOperands; 586 operandMapping[operandIndex] = operandIndex; 587 } 588 } else { 589 ++numPhysicalOperands; 590 operandMapping[operandIndex] = operandIndex; 591 } 592 593 const std::string &recName = OperandList[operandIndex].Rec->getName(); 594 595 if (recName.find("FR") != recName.npos) 596 hasFROperands = true; 597 } 598 599 if (hasFROperands && Name.find("MOV") != Name.npos && 600 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || 601 (Name.find("to") != Name.npos))) 602 ShouldBeEmitted = false; 603 604 if (!ShouldBeEmitted) 605 return; 606 607 #define HANDLE_OPERAND(class) \ 608 handleOperand(false, \ 609 operandIndex, \ 610 physicalOperandIndex, \ 611 numPhysicalOperands, \ 612 operandMapping, \ 613 class##EncodingFromString); 614 615 #define HANDLE_OPTIONAL(class) \ 616 handleOperand(true, \ 617 operandIndex, \ 618 physicalOperandIndex, \ 619 numPhysicalOperands, \ 620 operandMapping, \ 621 class##EncodingFromString); 622 623 // operandIndex should always be < numOperands 624 operandIndex = 0; 625 // physicalOperandIndex should always be < numPhysicalOperands 626 unsigned physicalOperandIndex = 0; 627 628 switch (Form) { 629 case X86Local::RawFrm: 630 // Operand 1 (optional) is an address or immediate. 631 // Operand 2 (optional) is an immediate. 632 assert(numPhysicalOperands <= 2 && 633 "Unexpected number of operands for RawFrm"); 634 HANDLE_OPTIONAL(relocation) 635 HANDLE_OPTIONAL(immediate) 636 break; 637 case X86Local::AddRegFrm: 638 // Operand 1 is added to the opcode. 639 // Operand 2 (optional) is an address. 640 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 641 "Unexpected number of operands for AddRegFrm"); 642 HANDLE_OPERAND(opcodeModifier) 643 HANDLE_OPTIONAL(relocation) 644 break; 645 case X86Local::MRMDestReg: 646 // Operand 1 is a register operand in the R/M field. 647 // Operand 2 is a register operand in the Reg/Opcode field. 648 // - In AVX, there is a register operand in the VEX.vvvv field here - 649 // Operand 3 (optional) is an immediate. 650 if (HasVEX_4VPrefix) 651 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 652 "Unexpected number of operands for MRMDestRegFrm with VEX_4V"); 653 else 654 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 655 "Unexpected number of operands for MRMDestRegFrm"); 656 657 HANDLE_OPERAND(rmRegister) 658 659 if (HasVEX_4VPrefix) 660 // FIXME: In AVX, the register below becomes the one encoded 661 // in ModRMVEX and the one above the one in the VEX.VVVV field 662 HANDLE_OPERAND(vvvvRegister) 663 664 HANDLE_OPERAND(roRegister) 665 HANDLE_OPTIONAL(immediate) 666 break; 667 case X86Local::MRMDestMem: 668 // Operand 1 is a memory operand (possibly SIB-extended) 669 // Operand 2 is a register operand in the Reg/Opcode field. 670 // - In AVX, there is a register operand in the VEX.vvvv field here - 671 // Operand 3 (optional) is an immediate. 672 if (HasVEX_4VPrefix) 673 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 674 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 675 else 676 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 677 "Unexpected number of operands for MRMDestMemFrm"); 678 HANDLE_OPERAND(memory) 679 680 if (HasVEX_4VPrefix) 681 // FIXME: In AVX, the register below becomes the one encoded 682 // in ModRMVEX and the one above the one in the VEX.VVVV field 683 HANDLE_OPERAND(vvvvRegister) 684 685 HANDLE_OPERAND(roRegister) 686 HANDLE_OPTIONAL(immediate) 687 break; 688 case X86Local::MRMSrcReg: 689 // Operand 1 is a register operand in the Reg/Opcode field. 690 // Operand 2 is a register operand in the R/M field. 691 // - In AVX, there is a register operand in the VEX.vvvv field here - 692 // Operand 3 (optional) is an immediate. 693 694 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix) 695 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && 696 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V"); 697 else 698 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 699 "Unexpected number of operands for MRMSrcRegFrm"); 700 701 HANDLE_OPERAND(roRegister) 702 703 if (HasVEX_4VPrefix) 704 // FIXME: In AVX, the register below becomes the one encoded 705 // in ModRMVEX and the one above the one in the VEX.VVVV field 706 HANDLE_OPERAND(vvvvRegister) 707 708 if (HasMemOp4Prefix) 709 HANDLE_OPERAND(immediate) 710 711 HANDLE_OPERAND(rmRegister) 712 713 if (HasVEX_4VOp3Prefix) 714 HANDLE_OPERAND(vvvvRegister) 715 716 if (!HasMemOp4Prefix) 717 HANDLE_OPTIONAL(immediate) 718 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 719 break; 720 case X86Local::MRMSrcMem: 721 // Operand 1 is a register operand in the Reg/Opcode field. 722 // Operand 2 is a memory operand (possibly SIB-extended) 723 // - In AVX, there is a register operand in the VEX.vvvv field here - 724 // Operand 3 (optional) is an immediate. 725 726 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix) 727 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && 728 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); 729 else 730 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 731 "Unexpected number of operands for MRMSrcMemFrm"); 732 733 HANDLE_OPERAND(roRegister) 734 735 if (HasVEX_4VPrefix) 736 // FIXME: In AVX, the register below becomes the one encoded 737 // in ModRMVEX and the one above the one in the VEX.VVVV field 738 HANDLE_OPERAND(vvvvRegister) 739 740 if (HasMemOp4Prefix) 741 HANDLE_OPERAND(immediate) 742 743 HANDLE_OPERAND(memory) 744 745 if (HasVEX_4VOp3Prefix) 746 HANDLE_OPERAND(vvvvRegister) 747 748 if (!HasMemOp4Prefix) 749 HANDLE_OPTIONAL(immediate) 750 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 751 break; 752 case X86Local::MRM0r: 753 case X86Local::MRM1r: 754 case X86Local::MRM2r: 755 case X86Local::MRM3r: 756 case X86Local::MRM4r: 757 case X86Local::MRM5r: 758 case X86Local::MRM6r: 759 case X86Local::MRM7r: 760 // Operand 1 is a register operand in the R/M field. 761 // Operand 2 (optional) is an immediate or relocation. 762 if (HasVEX_4VPrefix) 763 assert(numPhysicalOperands <= 3 && 764 "Unexpected number of operands for MRMnRFrm with VEX_4V"); 765 else 766 assert(numPhysicalOperands <= 2 && 767 "Unexpected number of operands for MRMnRFrm"); 768 if (HasVEX_4VPrefix) 769 HANDLE_OPERAND(vvvvRegister) 770 HANDLE_OPTIONAL(rmRegister) 771 HANDLE_OPTIONAL(relocation) 772 break; 773 case X86Local::MRM0m: 774 case X86Local::MRM1m: 775 case X86Local::MRM2m: 776 case X86Local::MRM3m: 777 case X86Local::MRM4m: 778 case X86Local::MRM5m: 779 case X86Local::MRM6m: 780 case X86Local::MRM7m: 781 // Operand 1 is a memory operand (possibly SIB-extended) 782 // Operand 2 (optional) is an immediate or relocation. 783 if (HasVEX_4VPrefix) 784 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 785 "Unexpected number of operands for MRMnMFrm"); 786 else 787 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 788 "Unexpected number of operands for MRMnMFrm"); 789 if (HasVEX_4VPrefix) 790 HANDLE_OPERAND(vvvvRegister) 791 HANDLE_OPERAND(memory) 792 HANDLE_OPTIONAL(relocation) 793 break; 794 case X86Local::RawFrmImm8: 795 // operand 1 is a 16-bit immediate 796 // operand 2 is an 8-bit immediate 797 assert(numPhysicalOperands == 2 && 798 "Unexpected number of operands for X86Local::RawFrmImm8"); 799 HANDLE_OPERAND(immediate) 800 HANDLE_OPERAND(immediate) 801 break; 802 case X86Local::RawFrmImm16: 803 // operand 1 is a 16-bit immediate 804 // operand 2 is a 16-bit immediate 805 HANDLE_OPERAND(immediate) 806 HANDLE_OPERAND(immediate) 807 break; 808 case X86Local::MRMInitReg: 809 // Ignored. 810 break; 811 } 812 813 #undef HANDLE_OPERAND 814 #undef HANDLE_OPTIONAL 815 } 816 817 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 818 // Special cases where the LLVM tables are not complete 819 820 #define MAP(from, to) \ 821 case X86Local::MRM_##from: \ 822 filter = new ExactFilter(0x##from); \ 823 break; 824 825 OpcodeType opcodeType = (OpcodeType)-1; 826 827 ModRMFilter* filter = NULL; 828 uint8_t opcodeToSet = 0; 829 830 switch (Prefix) { 831 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f 832 case X86Local::XD: 833 case X86Local::XS: 834 case X86Local::TB: 835 opcodeType = TWOBYTE; 836 837 switch (Opcode) { 838 default: 839 if (needsModRMForDecode(Form)) 840 filter = new ModFilter(isRegFormat(Form)); 841 else 842 filter = new DumbFilter(); 843 break; 844 #define EXTENSION_TABLE(n) case 0x##n: 845 TWO_BYTE_EXTENSION_TABLES 846 #undef EXTENSION_TABLE 847 switch (Form) { 848 default: 849 llvm_unreachable("Unhandled two-byte extended opcode"); 850 case X86Local::MRM0r: 851 case X86Local::MRM1r: 852 case X86Local::MRM2r: 853 case X86Local::MRM3r: 854 case X86Local::MRM4r: 855 case X86Local::MRM5r: 856 case X86Local::MRM6r: 857 case X86Local::MRM7r: 858 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 859 break; 860 case X86Local::MRM0m: 861 case X86Local::MRM1m: 862 case X86Local::MRM2m: 863 case X86Local::MRM3m: 864 case X86Local::MRM4m: 865 case X86Local::MRM5m: 866 case X86Local::MRM6m: 867 case X86Local::MRM7m: 868 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 869 break; 870 MRM_MAPPING 871 } // switch (Form) 872 break; 873 } // switch (Opcode) 874 opcodeToSet = Opcode; 875 break; 876 case X86Local::T8: 877 case X86Local::T8XD: 878 case X86Local::T8XS: 879 opcodeType = THREEBYTE_38; 880 switch (Opcode) { 881 default: 882 if (needsModRMForDecode(Form)) 883 filter = new ModFilter(isRegFormat(Form)); 884 else 885 filter = new DumbFilter(); 886 break; 887 #define EXTENSION_TABLE(n) case 0x##n: 888 THREE_BYTE_38_EXTENSION_TABLES 889 #undef EXTENSION_TABLE 890 switch (Form) { 891 default: 892 llvm_unreachable("Unhandled two-byte extended opcode"); 893 case X86Local::MRM0r: 894 case X86Local::MRM1r: 895 case X86Local::MRM2r: 896 case X86Local::MRM3r: 897 case X86Local::MRM4r: 898 case X86Local::MRM5r: 899 case X86Local::MRM6r: 900 case X86Local::MRM7r: 901 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 902 break; 903 case X86Local::MRM0m: 904 case X86Local::MRM1m: 905 case X86Local::MRM2m: 906 case X86Local::MRM3m: 907 case X86Local::MRM4m: 908 case X86Local::MRM5m: 909 case X86Local::MRM6m: 910 case X86Local::MRM7m: 911 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 912 break; 913 MRM_MAPPING 914 } // switch (Form) 915 break; 916 } // switch (Opcode) 917 opcodeToSet = Opcode; 918 break; 919 case X86Local::P_TA: 920 case X86Local::TAXD: 921 opcodeType = THREEBYTE_3A; 922 if (needsModRMForDecode(Form)) 923 filter = new ModFilter(isRegFormat(Form)); 924 else 925 filter = new DumbFilter(); 926 opcodeToSet = Opcode; 927 break; 928 case X86Local::A6: 929 opcodeType = THREEBYTE_A6; 930 if (needsModRMForDecode(Form)) 931 filter = new ModFilter(isRegFormat(Form)); 932 else 933 filter = new DumbFilter(); 934 opcodeToSet = Opcode; 935 break; 936 case X86Local::A7: 937 opcodeType = THREEBYTE_A7; 938 if (needsModRMForDecode(Form)) 939 filter = new ModFilter(isRegFormat(Form)); 940 else 941 filter = new DumbFilter(); 942 opcodeToSet = Opcode; 943 break; 944 case X86Local::D8: 945 case X86Local::D9: 946 case X86Local::DA: 947 case X86Local::DB: 948 case X86Local::DC: 949 case X86Local::DD: 950 case X86Local::DE: 951 case X86Local::DF: 952 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode"); 953 opcodeType = ONEBYTE; 954 if (Form == X86Local::AddRegFrm) { 955 Spec->modifierType = MODIFIER_MODRM; 956 Spec->modifierBase = Opcode; 957 filter = new AddRegEscapeFilter(Opcode); 958 } else { 959 filter = new EscapeFilter(true, Opcode); 960 } 961 opcodeToSet = 0xd8 + (Prefix - X86Local::D8); 962 break; 963 case X86Local::REP: 964 default: 965 opcodeType = ONEBYTE; 966 switch (Opcode) { 967 #define EXTENSION_TABLE(n) case 0x##n: 968 ONE_BYTE_EXTENSION_TABLES 969 #undef EXTENSION_TABLE 970 switch (Form) { 971 default: 972 llvm_unreachable("Fell through the cracks of a single-byte " 973 "extended opcode"); 974 case X86Local::MRM0r: 975 case X86Local::MRM1r: 976 case X86Local::MRM2r: 977 case X86Local::MRM3r: 978 case X86Local::MRM4r: 979 case X86Local::MRM5r: 980 case X86Local::MRM6r: 981 case X86Local::MRM7r: 982 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 983 break; 984 case X86Local::MRM0m: 985 case X86Local::MRM1m: 986 case X86Local::MRM2m: 987 case X86Local::MRM3m: 988 case X86Local::MRM4m: 989 case X86Local::MRM5m: 990 case X86Local::MRM6m: 991 case X86Local::MRM7m: 992 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 993 break; 994 MRM_MAPPING 995 } // switch (Form) 996 break; 997 case 0xd8: 998 case 0xd9: 999 case 0xda: 1000 case 0xdb: 1001 case 0xdc: 1002 case 0xdd: 1003 case 0xde: 1004 case 0xdf: 1005 filter = new EscapeFilter(false, Form - X86Local::MRM0m); 1006 break; 1007 default: 1008 if (needsModRMForDecode(Form)) 1009 filter = new ModFilter(isRegFormat(Form)); 1010 else 1011 filter = new DumbFilter(); 1012 break; 1013 } // switch (Opcode) 1014 opcodeToSet = Opcode; 1015 } // switch (Prefix) 1016 1017 assert(opcodeType != (OpcodeType)-1 && 1018 "Opcode type not set"); 1019 assert(filter && "Filter not set"); 1020 1021 if (Form == X86Local::AddRegFrm) { 1022 if(Spec->modifierType != MODIFIER_MODRM) { 1023 assert(opcodeToSet < 0xf9 && 1024 "Not enough room for all ADDREG_FRM operands"); 1025 1026 uint8_t currentOpcode; 1027 1028 for (currentOpcode = opcodeToSet; 1029 currentOpcode < opcodeToSet + 8; 1030 ++currentOpcode) 1031 tables.setTableFields(opcodeType, 1032 insnContext(), 1033 currentOpcode, 1034 *filter, 1035 UID, Is32Bit, IgnoresVEX_L); 1036 1037 Spec->modifierType = MODIFIER_OPCODE; 1038 Spec->modifierBase = opcodeToSet; 1039 } else { 1040 // modifierBase was set where MODIFIER_MODRM was set 1041 tables.setTableFields(opcodeType, 1042 insnContext(), 1043 opcodeToSet, 1044 *filter, 1045 UID, Is32Bit, IgnoresVEX_L); 1046 } 1047 } else { 1048 tables.setTableFields(opcodeType, 1049 insnContext(), 1050 opcodeToSet, 1051 *filter, 1052 UID, Is32Bit, IgnoresVEX_L); 1053 1054 Spec->modifierType = MODIFIER_NONE; 1055 Spec->modifierBase = opcodeToSet; 1056 } 1057 1058 delete filter; 1059 1060 #undef MAP 1061 } 1062 1063 #define TYPE(str, type) if (s == str) return type; 1064 OperandType RecognizableInstr::typeFromString(const std::string &s, 1065 bool isSSE, 1066 bool hasREX_WPrefix, 1067 bool hasOpSizePrefix) { 1068 if (isSSE) { 1069 // For SSE instructions, we ignore the OpSize prefix and force operand 1070 // sizes. 1071 TYPE("GR16", TYPE_R16) 1072 TYPE("GR32", TYPE_R32) 1073 TYPE("GR64", TYPE_R64) 1074 } 1075 if(hasREX_WPrefix) { 1076 // For instructions with a REX_W prefix, a declared 32-bit register encoding 1077 // is special. 1078 TYPE("GR32", TYPE_R32) 1079 } 1080 if(!hasOpSizePrefix) { 1081 // For instructions without an OpSize prefix, a declared 16-bit register or 1082 // immediate encoding is special. 1083 TYPE("GR16", TYPE_R16) 1084 TYPE("i16imm", TYPE_IMM16) 1085 } 1086 TYPE("i16mem", TYPE_Mv) 1087 TYPE("i16imm", TYPE_IMMv) 1088 TYPE("i16i8imm", TYPE_IMMv) 1089 TYPE("GR16", TYPE_Rv) 1090 TYPE("i32mem", TYPE_Mv) 1091 TYPE("i32imm", TYPE_IMMv) 1092 TYPE("i32i8imm", TYPE_IMM32) 1093 TYPE("u32u8imm", TYPE_IMM32) 1094 TYPE("GR32", TYPE_Rv) 1095 TYPE("i64mem", TYPE_Mv) 1096 TYPE("i64i32imm", TYPE_IMM64) 1097 TYPE("i64i8imm", TYPE_IMM64) 1098 TYPE("GR64", TYPE_R64) 1099 TYPE("i8mem", TYPE_M8) 1100 TYPE("i8imm", TYPE_IMM8) 1101 TYPE("GR8", TYPE_R8) 1102 TYPE("VR128", TYPE_XMM128) 1103 TYPE("f128mem", TYPE_M128) 1104 TYPE("f256mem", TYPE_M256) 1105 TYPE("FR64", TYPE_XMM64) 1106 TYPE("f64mem", TYPE_M64FP) 1107 TYPE("sdmem", TYPE_M64FP) 1108 TYPE("FR32", TYPE_XMM32) 1109 TYPE("f32mem", TYPE_M32FP) 1110 TYPE("ssmem", TYPE_M32FP) 1111 TYPE("RST", TYPE_ST) 1112 TYPE("i128mem", TYPE_M128) 1113 TYPE("i256mem", TYPE_M256) 1114 TYPE("i64i32imm_pcrel", TYPE_REL64) 1115 TYPE("i16imm_pcrel", TYPE_REL16) 1116 TYPE("i32imm_pcrel", TYPE_REL32) 1117 TYPE("SSECC", TYPE_IMM3) 1118 TYPE("AVXCC", TYPE_IMM5) 1119 TYPE("brtarget", TYPE_RELv) 1120 TYPE("uncondbrtarget", TYPE_RELv) 1121 TYPE("brtarget8", TYPE_REL8) 1122 TYPE("f80mem", TYPE_M80FP) 1123 TYPE("lea32mem", TYPE_LEA) 1124 TYPE("lea64_32mem", TYPE_LEA) 1125 TYPE("lea64mem", TYPE_LEA) 1126 TYPE("VR64", TYPE_MM64) 1127 TYPE("i64imm", TYPE_IMMv) 1128 TYPE("opaque32mem", TYPE_M1616) 1129 TYPE("opaque48mem", TYPE_M1632) 1130 TYPE("opaque80mem", TYPE_M1664) 1131 TYPE("opaque512mem", TYPE_M512) 1132 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 1133 TYPE("DEBUG_REG", TYPE_DEBUGREG) 1134 TYPE("CONTROL_REG", TYPE_CONTROLREG) 1135 TYPE("offset8", TYPE_MOFFS8) 1136 TYPE("offset16", TYPE_MOFFS16) 1137 TYPE("offset32", TYPE_MOFFS32) 1138 TYPE("offset64", TYPE_MOFFS64) 1139 TYPE("VR256", TYPE_XMM256) 1140 TYPE("GR16_NOAX", TYPE_Rv) 1141 TYPE("GR32_NOAX", TYPE_Rv) 1142 TYPE("GR64_NOAX", TYPE_R64) 1143 errs() << "Unhandled type string " << s << "\n"; 1144 llvm_unreachable("Unhandled type string"); 1145 } 1146 #undef TYPE 1147 1148 #define ENCODING(str, encoding) if (s == str) return encoding; 1149 OperandEncoding RecognizableInstr::immediateEncodingFromString 1150 (const std::string &s, 1151 bool hasOpSizePrefix) { 1152 if(!hasOpSizePrefix) { 1153 // For instructions without an OpSize prefix, a declared 16-bit register or 1154 // immediate encoding is special. 1155 ENCODING("i16imm", ENCODING_IW) 1156 } 1157 ENCODING("i32i8imm", ENCODING_IB) 1158 ENCODING("u32u8imm", ENCODING_IB) 1159 ENCODING("SSECC", ENCODING_IB) 1160 ENCODING("AVXCC", ENCODING_IB) 1161 ENCODING("i16imm", ENCODING_Iv) 1162 ENCODING("i16i8imm", ENCODING_IB) 1163 ENCODING("i32imm", ENCODING_Iv) 1164 ENCODING("i64i32imm", ENCODING_ID) 1165 ENCODING("i64i8imm", ENCODING_IB) 1166 ENCODING("i8imm", ENCODING_IB) 1167 // This is not a typo. Instructions like BLENDVPD put 1168 // register IDs in 8-bit immediates nowadays. 1169 ENCODING("VR256", ENCODING_IB) 1170 ENCODING("VR128", ENCODING_IB) 1171 errs() << "Unhandled immediate encoding " << s << "\n"; 1172 llvm_unreachable("Unhandled immediate encoding"); 1173 } 1174 1175 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString 1176 (const std::string &s, 1177 bool hasOpSizePrefix) { 1178 ENCODING("GR16", ENCODING_RM) 1179 ENCODING("GR32", ENCODING_RM) 1180 ENCODING("GR64", ENCODING_RM) 1181 ENCODING("GR8", ENCODING_RM) 1182 ENCODING("VR128", ENCODING_RM) 1183 ENCODING("FR64", ENCODING_RM) 1184 ENCODING("FR32", ENCODING_RM) 1185 ENCODING("VR64", ENCODING_RM) 1186 ENCODING("VR256", ENCODING_RM) 1187 errs() << "Unhandled R/M register encoding " << s << "\n"; 1188 llvm_unreachable("Unhandled R/M register encoding"); 1189 } 1190 1191 OperandEncoding RecognizableInstr::roRegisterEncodingFromString 1192 (const std::string &s, 1193 bool hasOpSizePrefix) { 1194 ENCODING("GR16", ENCODING_REG) 1195 ENCODING("GR32", ENCODING_REG) 1196 ENCODING("GR64", ENCODING_REG) 1197 ENCODING("GR8", ENCODING_REG) 1198 ENCODING("VR128", ENCODING_REG) 1199 ENCODING("FR64", ENCODING_REG) 1200 ENCODING("FR32", ENCODING_REG) 1201 ENCODING("VR64", ENCODING_REG) 1202 ENCODING("SEGMENT_REG", ENCODING_REG) 1203 ENCODING("DEBUG_REG", ENCODING_REG) 1204 ENCODING("CONTROL_REG", ENCODING_REG) 1205 ENCODING("VR256", ENCODING_REG) 1206 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1207 llvm_unreachable("Unhandled reg/opcode register encoding"); 1208 } 1209 1210 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString 1211 (const std::string &s, 1212 bool hasOpSizePrefix) { 1213 ENCODING("GR32", ENCODING_VVVV) 1214 ENCODING("GR64", ENCODING_VVVV) 1215 ENCODING("FR32", ENCODING_VVVV) 1216 ENCODING("FR64", ENCODING_VVVV) 1217 ENCODING("VR128", ENCODING_VVVV) 1218 ENCODING("VR256", ENCODING_VVVV) 1219 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1220 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1221 } 1222 1223 OperandEncoding RecognizableInstr::memoryEncodingFromString 1224 (const std::string &s, 1225 bool hasOpSizePrefix) { 1226 ENCODING("i16mem", ENCODING_RM) 1227 ENCODING("i32mem", ENCODING_RM) 1228 ENCODING("i64mem", ENCODING_RM) 1229 ENCODING("i8mem", ENCODING_RM) 1230 ENCODING("ssmem", ENCODING_RM) 1231 ENCODING("sdmem", ENCODING_RM) 1232 ENCODING("f128mem", ENCODING_RM) 1233 ENCODING("f256mem", ENCODING_RM) 1234 ENCODING("f64mem", ENCODING_RM) 1235 ENCODING("f32mem", ENCODING_RM) 1236 ENCODING("i128mem", ENCODING_RM) 1237 ENCODING("i256mem", ENCODING_RM) 1238 ENCODING("f80mem", ENCODING_RM) 1239 ENCODING("lea32mem", ENCODING_RM) 1240 ENCODING("lea64_32mem", ENCODING_RM) 1241 ENCODING("lea64mem", ENCODING_RM) 1242 ENCODING("opaque32mem", ENCODING_RM) 1243 ENCODING("opaque48mem", ENCODING_RM) 1244 ENCODING("opaque80mem", ENCODING_RM) 1245 ENCODING("opaque512mem", ENCODING_RM) 1246 errs() << "Unhandled memory encoding " << s << "\n"; 1247 llvm_unreachable("Unhandled memory encoding"); 1248 } 1249 1250 OperandEncoding RecognizableInstr::relocationEncodingFromString 1251 (const std::string &s, 1252 bool hasOpSizePrefix) { 1253 if(!hasOpSizePrefix) { 1254 // For instructions without an OpSize prefix, a declared 16-bit register or 1255 // immediate encoding is special. 1256 ENCODING("i16imm", ENCODING_IW) 1257 } 1258 ENCODING("i16imm", ENCODING_Iv) 1259 ENCODING("i16i8imm", ENCODING_IB) 1260 ENCODING("i32imm", ENCODING_Iv) 1261 ENCODING("i32i8imm", ENCODING_IB) 1262 ENCODING("i64i32imm", ENCODING_ID) 1263 ENCODING("i64i8imm", ENCODING_IB) 1264 ENCODING("i8imm", ENCODING_IB) 1265 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1266 ENCODING("i16imm_pcrel", ENCODING_IW) 1267 ENCODING("i32imm_pcrel", ENCODING_ID) 1268 ENCODING("brtarget", ENCODING_Iv) 1269 ENCODING("brtarget8", ENCODING_IB) 1270 ENCODING("i64imm", ENCODING_IO) 1271 ENCODING("offset8", ENCODING_Ia) 1272 ENCODING("offset16", ENCODING_Ia) 1273 ENCODING("offset32", ENCODING_Ia) 1274 ENCODING("offset64", ENCODING_Ia) 1275 errs() << "Unhandled relocation encoding " << s << "\n"; 1276 llvm_unreachable("Unhandled relocation encoding"); 1277 } 1278 1279 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString 1280 (const std::string &s, 1281 bool hasOpSizePrefix) { 1282 ENCODING("RST", ENCODING_I) 1283 ENCODING("GR32", ENCODING_Rv) 1284 ENCODING("GR64", ENCODING_RO) 1285 ENCODING("GR16", ENCODING_Rv) 1286 ENCODING("GR8", ENCODING_RB) 1287 ENCODING("GR16_NOAX", ENCODING_Rv) 1288 ENCODING("GR32_NOAX", ENCODING_Rv) 1289 ENCODING("GR64_NOAX", ENCODING_RO) 1290 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1291 llvm_unreachable("Unhandled opcode modifier encoding"); 1292 } 1293 #undef ENCODING 1294
