1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Base ARM implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef ARMBASEINSTRUCTIONINFO_H 15 #define ARMBASEINSTRUCTIONINFO_H 16 17 #include "ARM.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/Target/TargetInstrInfo.h" 20 #include "llvm/ADT/DenseMap.h" 21 #include "llvm/ADT/SmallSet.h" 22 23 #define GET_INSTRINFO_HEADER 24 #include "ARMGenInstrInfo.inc" 25 26 namespace llvm { 27 class ARMSubtarget; 28 class ARMBaseRegisterInfo; 29 30 class ARMBaseInstrInfo : public ARMGenInstrInfo { 31 const ARMSubtarget &Subtarget; 32 33 protected: 34 // Can be only subclassed. 35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI); 36 37 public: 38 // Return whether the target has an explicit NOP encoding. 39 bool hasNOP() const; 40 41 // Return the non-pre/post incrementing version of 'Opc'. Return 0 42 // if there is not such an opcode. 43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; 44 45 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 46 MachineBasicBlock::iterator &MBBI, 47 LiveVariables *LV) const; 48 49 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0; 50 const ARMSubtarget &getSubtarget() const { return Subtarget; } 51 52 ScheduleHazardRecognizer * 53 CreateTargetHazardRecognizer(const TargetMachine *TM, 54 const ScheduleDAG *DAG) const; 55 56 ScheduleHazardRecognizer * 57 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 58 const ScheduleDAG *DAG) const; 59 60 // Branch analysis. 61 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 62 MachineBasicBlock *&FBB, 63 SmallVectorImpl<MachineOperand> &Cond, 64 bool AllowModify = false) const; 65 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 66 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 67 MachineBasicBlock *FBB, 68 const SmallVectorImpl<MachineOperand> &Cond, 69 DebugLoc DL) const; 70 71 virtual 72 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 73 74 // Predication support. 75 bool isPredicated(const MachineInstr *MI) const; 76 77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { 78 int PIdx = MI->findFirstPredOperandIdx(); 79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() 80 : ARMCC::AL; 81 } 82 83 virtual 84 bool PredicateInstruction(MachineInstr *MI, 85 const SmallVectorImpl<MachineOperand> &Pred) const; 86 87 virtual 88 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 89 const SmallVectorImpl<MachineOperand> &Pred2) const; 90 91 virtual bool DefinesPredicate(MachineInstr *MI, 92 std::vector<MachineOperand> &Pred) const; 93 94 virtual bool isPredicable(MachineInstr *MI) const; 95 96 /// GetInstSize - Returns the size of the specified MachineInstr. 97 /// 98 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const; 99 100 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 101 int &FrameIndex) const; 102 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 103 int &FrameIndex) const; 104 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 105 int &FrameIndex) const; 106 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 107 int &FrameIndex) const; 108 109 virtual void copyPhysReg(MachineBasicBlock &MBB, 110 MachineBasicBlock::iterator I, DebugLoc DL, 111 unsigned DestReg, unsigned SrcReg, 112 bool KillSrc) const; 113 114 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 115 MachineBasicBlock::iterator MBBI, 116 unsigned SrcReg, bool isKill, int FrameIndex, 117 const TargetRegisterClass *RC, 118 const TargetRegisterInfo *TRI) const; 119 120 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 121 MachineBasicBlock::iterator MBBI, 122 unsigned DestReg, int FrameIndex, 123 const TargetRegisterClass *RC, 124 const TargetRegisterInfo *TRI) const; 125 126 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 127 128 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 129 int FrameIx, 130 uint64_t Offset, 131 const MDNode *MDPtr, 132 DebugLoc DL) const; 133 134 virtual void reMaterialize(MachineBasicBlock &MBB, 135 MachineBasicBlock::iterator MI, 136 unsigned DestReg, unsigned SubIdx, 137 const MachineInstr *Orig, 138 const TargetRegisterInfo &TRI) const; 139 140 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const; 141 142 MachineInstr *commuteInstruction(MachineInstr*, bool=false) const; 143 144 virtual bool produceSameValue(const MachineInstr *MI0, 145 const MachineInstr *MI1, 146 const MachineRegisterInfo *MRI) const; 147 148 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 149 /// determine if two loads are loading from the same base address. It should 150 /// only return true if the base pointers are the same and the only 151 /// differences between the two addresses is the offset. It also returns the 152 /// offsets by reference. 153 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 154 int64_t &Offset1, int64_t &Offset2)const; 155 156 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 157 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 158 /// should be scheduled togther. On some targets if two loads are loading from 159 /// addresses in the same cache line, it's better if they are scheduled 160 /// together. This function takes two integers that represent the load offsets 161 /// from the common base address. It returns true if it decides it's desirable 162 /// to schedule the two loads together. "NumLoads" is the number of loads that 163 /// have already been scheduled after Load1. 164 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 165 int64_t Offset1, int64_t Offset2, 166 unsigned NumLoads) const; 167 168 virtual bool isSchedulingBoundary(const MachineInstr *MI, 169 const MachineBasicBlock *MBB, 170 const MachineFunction &MF) const; 171 172 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, 173 unsigned NumCycles, unsigned ExtraPredCycles, 174 const BranchProbability &Probability) const; 175 176 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 177 unsigned NumT, unsigned ExtraT, 178 MachineBasicBlock &FMBB, 179 unsigned NumF, unsigned ExtraF, 180 const BranchProbability &Probability) const; 181 182 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 183 unsigned NumCycles, 184 const BranchProbability 185 &Probability) const { 186 return NumCycles == 1; 187 } 188 189 /// AnalyzeCompare - For a comparison instruction, return the source register 190 /// in SrcReg and the value it compares against in CmpValue. Return true if 191 /// the comparison instruction can be analyzed. 192 virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, 193 int &CmpMask, int &CmpValue) const; 194 195 /// OptimizeCompareInstr - Convert the instruction to set the zero flag so 196 /// that we can remove a "comparison with zero". 197 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, 198 int CmpMask, int CmpValue, 199 const MachineRegisterInfo *MRI) const; 200 201 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 202 /// instruction, try to fold the immediate into the use instruction. 203 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 204 unsigned Reg, MachineRegisterInfo *MRI) const; 205 206 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 207 const MachineInstr *MI) const; 208 209 virtual 210 int getOperandLatency(const InstrItineraryData *ItinData, 211 const MachineInstr *DefMI, unsigned DefIdx, 212 const MachineInstr *UseMI, unsigned UseIdx) const; 213 virtual 214 int getOperandLatency(const InstrItineraryData *ItinData, 215 SDNode *DefNode, unsigned DefIdx, 216 SDNode *UseNode, unsigned UseIdx) const; 217 218 virtual unsigned getOutputLatency(const InstrItineraryData *ItinData, 219 const MachineInstr *DefMI, unsigned DefIdx, 220 const MachineInstr *DepMI) const; 221 222 /// VFP/NEON execution domains. 223 std::pair<uint16_t, uint16_t> 224 getExecutionDomain(const MachineInstr *MI) const; 225 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const; 226 227 private: 228 unsigned getInstBundleLength(const MachineInstr *MI) const; 229 230 int getVLDMDefCycle(const InstrItineraryData *ItinData, 231 const MCInstrDesc &DefMCID, 232 unsigned DefClass, 233 unsigned DefIdx, unsigned DefAlign) const; 234 int getLDMDefCycle(const InstrItineraryData *ItinData, 235 const MCInstrDesc &DefMCID, 236 unsigned DefClass, 237 unsigned DefIdx, unsigned DefAlign) const; 238 int getVSTMUseCycle(const InstrItineraryData *ItinData, 239 const MCInstrDesc &UseMCID, 240 unsigned UseClass, 241 unsigned UseIdx, unsigned UseAlign) const; 242 int getSTMUseCycle(const InstrItineraryData *ItinData, 243 const MCInstrDesc &UseMCID, 244 unsigned UseClass, 245 unsigned UseIdx, unsigned UseAlign) const; 246 int getOperandLatency(const InstrItineraryData *ItinData, 247 const MCInstrDesc &DefMCID, 248 unsigned DefIdx, unsigned DefAlign, 249 const MCInstrDesc &UseMCID, 250 unsigned UseIdx, unsigned UseAlign) const; 251 252 int getInstrLatency(const InstrItineraryData *ItinData, 253 const MachineInstr *MI, unsigned *PredCost = 0) const; 254 255 int getInstrLatency(const InstrItineraryData *ItinData, 256 SDNode *Node) const; 257 258 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 259 const MachineRegisterInfo *MRI, 260 const MachineInstr *DefMI, unsigned DefIdx, 261 const MachineInstr *UseMI, unsigned UseIdx) const; 262 bool hasLowDefLatency(const InstrItineraryData *ItinData, 263 const MachineInstr *DefMI, unsigned DefIdx) const; 264 265 /// verifyInstruction - Perform target specific instruction verification. 266 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const; 267 268 private: 269 /// Modeling special VFP / NEON fp MLA / MLS hazards. 270 271 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal 272 /// MLx table. 273 DenseMap<unsigned, unsigned> MLxEntryMap; 274 275 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause 276 /// stalls when scheduled together with fp MLA / MLS opcodes. 277 SmallSet<unsigned, 16> MLxHazardOpcodes; 278 279 public: 280 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS 281 /// instruction. 282 bool isFpMLxInstruction(unsigned Opcode) const { 283 return MLxEntryMap.count(Opcode); 284 } 285 286 /// isFpMLxInstruction - This version also returns the multiply opcode and the 287 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for 288 /// the MLX instructions with an extra lane operand. 289 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 290 unsigned &AddSubOpc, bool &NegAcc, 291 bool &HasLane) const; 292 293 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode 294 /// will cause stalls when scheduled after (within 4-cycle window) a fp 295 /// MLA / MLS instruction. 296 bool canCauseFpMLxStall(unsigned Opcode) const { 297 return MLxHazardOpcodes.count(Opcode); 298 } 299 }; 300 301 static inline 302 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 303 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 304 } 305 306 static inline 307 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 308 return MIB.addReg(0); 309 } 310 311 static inline 312 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, 313 bool isDead = false) { 314 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 315 } 316 317 static inline 318 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { 319 return MIB.addReg(0); 320 } 321 322 static inline 323 bool isUncondBranchOpcode(int Opc) { 324 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 325 } 326 327 static inline 328 bool isCondBranchOpcode(int Opc) { 329 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; 330 } 331 332 static inline 333 bool isJumpTableBranchOpcode(int Opc) { 334 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || 335 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; 336 } 337 338 static inline 339 bool isIndirectBranchOpcode(int Opc) { 340 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; 341 } 342 343 /// getInstrPredicate - If instruction is predicated, returns its predicate 344 /// condition, otherwise returns AL. It also returns the condition code 345 /// register by reference. 346 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 347 348 int getMatchingCondBranchOpcode(int Opc); 349 350 351 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether 352 /// the instruction is encoded with an 'S' bit is determined by the optional 353 /// CPSR def operand. 354 unsigned convertAddSubFlagsOpcode(unsigned OldOpc); 355 356 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of 357 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 358 /// code. 359 void emitARMRegPlusImmediate(MachineBasicBlock &MBB, 360 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 361 unsigned DestReg, unsigned BaseReg, int NumBytes, 362 ARMCC::CondCodes Pred, unsigned PredReg, 363 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 364 365 void emitT2RegPlusImmediate(MachineBasicBlock &MBB, 366 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 367 unsigned DestReg, unsigned BaseReg, int NumBytes, 368 ARMCC::CondCodes Pred, unsigned PredReg, 369 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 370 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 371 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 372 unsigned DestReg, unsigned BaseReg, 373 int NumBytes, const TargetInstrInfo &TII, 374 const ARMBaseRegisterInfo& MRI, 375 unsigned MIFlags = 0); 376 377 378 /// rewriteARMFrameIndex / rewriteT2FrameIndex - 379 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the 380 /// offset could not be handled directly in MI, and return the left-over 381 /// portion by reference. 382 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 383 unsigned FrameReg, int &Offset, 384 const ARMBaseInstrInfo &TII); 385 386 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 387 unsigned FrameReg, int &Offset, 388 const ARMBaseInstrInfo &TII); 389 390 } // End llvm namespace 391 392 #endif 393
