| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 22 namespace ARM_AM {
25 default: return ARM_AM::no_shift;
26 case ISD::SHL: return ARM_AM::lsl;
27 case ISD::SRL: return ARM_AM::lsr;
28 case ISD::SRA: return ARM_AM::asr;
29 case ISD::ROTR: return ARM_AM::ror;
33 //case ARMISD::RRX: return ARM_AM::rrx;
36 } // end namespace ARM_AM
|
| ARMLoadStoreOptimizer.cpp | 137 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
144 case ARM_AM::ia: return ARM::LDMIA;
145 case ARM_AM::da: return ARM::LDMDA;
146 case ARM_AM::db: return ARM::LDMDB;
147 case ARM_AM::ib: return ARM::LDMIB;
153 case ARM_AM::ia: return ARM::STMIA;
154 case ARM_AM::da: return ARM::STMDA;
155 case ARM_AM::db: return ARM::STMDB;
156 case ARM_AM::ib: return ARM::STMIB;
163 case ARM_AM::ia: return ARM::t2LDMIA
[all...] |
| ARMCodeEmitter.cpp | 323 if (uint32_t ImmOffs = ARM_AM::getAM5Offset(MO1.getImm())) {
324 if (ARM_AM::getAM5Op(MO1.getImm()) == ARM_AM::add)
418 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
420 case ARM_AM::asr: return 2;
421 case ARM_AM::lsl: return 0;
422 case ARM_AM::lsr: return 1;
423 case ARM_AM::ror:
424 case ARM_AM::rrx: return 3;
769 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &
[all...] |
| ARMISelDAGToDAG.cpp | 97 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
184 return ARM_AM::getSOImmVal(Imm) != -1;
188 return ARM_AM::getSOImmVal(~Imm) != -1;
192 return ARM_AM::getT2SOImmVal(Imm) != -1;
196 return ARM_AM::getT2SOImmVal(~Imm) != -1;
381 ARM_AM::ShiftOpc ShOpcVal,
388 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
398 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
402 if (ShOpcVal == ARM_AM::no_shift) return false
[all...] |
| Thumb2InstrInfo.cpp | 189 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
249 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
254 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
256 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
262 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
271 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
273 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
427 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
453 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
458 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &
[all...] |
| ARMJITInfo.cpp | 312 int SoImmVal = ARM_AM::getSOImmVal(ResultPtr);
314 *((intptr_t*)RelocPos) |= (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
316 *((intptr_t*)RelocPos) |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
|
| ARMBaseInstrInfo.cpp | 161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
162 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
164 if (ARM_AM::getSOImmVal(Amt) == -1)
173 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
188 unsigned Amt = ARM_AM::getAM3Offset(OffImm)
[all...] |
| ARMBaseRegisterInfo.cpp | 799 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
800 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
807 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
808 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
814 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
815 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
[all...] |
| ARMExpandPseudoInsts.cpp | 632 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
633 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
[all...] |
| ARMFastISel.cpp | 519 Imm = ARM_AM::getFP64Imm(Val);
522 Imm = ARM_AM::getFP32Imm(Val);
573 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
574 (ARM_AM::getSOImmVal(Imm) != -1);
[all...] |
| ARMISelLowering.cpp | [all...] |
| ARMFrameLowering.cpp | 704 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 63 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
71 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
82 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
89 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
94 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
251 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm())
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 169 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
172 case ARM_AM::da: return 0;
173 case ARM_AM::ia: return 1;
174 case ARM_AM::db: return 2;
175 case ARM_AM::ib: return 3;
180 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
182 case ARM_AM::no_shift:
183 case ARM_AM::lsl: return 0;
184 case ARM_AM::lsr: return 1
[all...] |
| ARMAddressingModes.h | 25 /// ARM_AM - ARM Addressing Mode Stuff
26 namespace ARM_AM {
48 case ARM_AM::asr: return "asr";
49 case ARM_AM::lsl: return "lsl";
50 case ARM_AM::lsr: return "lsr";
51 case ARM_AM::ror: return "ror";
52 case ARM_AM::rrx: return "rrx";
59 case ARM_AM::asr: return 2;
60 case ARM_AM::lsl: return 0;
61 case ARM_AM::lsr: return 1
[all...] |
| ARMAsmBackend.cpp | 348 assert(ARM_AM::getSOImmVal(Value) != -1 &&
351 return ARM_AM::getSOImmVal(Value) | (opc << 21);
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 101 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
368 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
378 ARM_AM::ShiftOpc ShiftTy;
387 ARM_AM::ShiftOpc ShiftTy;
393 ARM_AM::ShiftOpc ShiftTy;
552 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
801 return ARM_AM::getSOImmVal(Value) != -1;
808 return ARM_AM::getSOImmVal(~Value) != -1;
816 return ARM_AM::getSOImmVal(Value) == -1 &&
817 ARM_AM::getSOImmVal(-Value) != -1
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
