| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 383 FP_TO_SINT,
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 331 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
333 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
337 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
339 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
341 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand);
389 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
392 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 587 case ISD::FP_TO_SINT: Res = SoftenFloatOp_FP_TO_SINT(N); break;
734 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
[all...] |
| LegalizeVectorOps.cpp | 201 case ISD::FP_TO_SINT:
|
| SelectionDAGDumper.cpp | 225 case ISD::FP_TO_SINT: return "fp_to_sint";
|
| LegalizeVectorTypes.cpp | 83 case ISD::FP_TO_SINT:
497 case ISD::FP_TO_SINT:
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 97 case ISD::FP_TO_SINT:
357 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
362 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
363 NewOpc = ISD::FP_TO_SINT;
[all...] |
| FastISel.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 720 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 185 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
276 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 112 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
117 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
542 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
558 setTargetDAGCombine(ISD::FP_TO_SINT);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 283 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
286 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
288 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
289 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
292 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
294 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
[all...] |
