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  /external/llvm/lib/CodeGen/
CallingConvLower.cpp 69 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
71 unsigned NumArgs = Ins.size();
74 MVT ArgVT = Ins[i].VT;
75 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
157 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
159 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
160 MVT VT = Ins[i].VT;
161 ISD::ArgFlagsTy Flags = Ins[i].Flags;
RegAllocGreedy.cpp 702 unsigned Ins = 0;
707 BC.Entry = SpillPlacement::MustSpill, ++Ins;
709 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
711 ++Ins;
717 BC.Exit = SpillPlacement::MustSpill, ++Ins;
719 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
721 ++Ins;
725 if (Ins)
726 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
913 unsigned Ins = 0
    [all...]
  /external/llvm/lib/Target/PTX/
PTXISelLowering.h 50 const SmallVectorImpl<ISD::InputArg> &Ins,
69 const SmallVectorImpl<ISD::InputArg> &Ins,
PTXISelLowering.cpp 210 const SmallVectorImpl<ISD::InputArg> &Ins,
237 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
238 assert((!MFI->isKernel() || Ins[i].VT != MVT::i1) &&
241 unsigned ParamSize = Ins[i].VT.getStoreSizeInBits();
246 SDValue ArgValue = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain,
252 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
253 EVT RegVT = Ins[i].VT;
389 const SmallVectorImpl<ISD::InputArg> &Ins,
414 // The layout of the ops will be [Chain, #Ins, Ins, Callee, #Outs, Outs
    [all...]
  /external/llvm/lib/Target/MSP430/
MSP430ISelLowering.h 130 const SmallVectorImpl<ISD::InputArg> &Ins,
137 const SmallVectorImpl<ISD::InputArg> &Ins,
144 const SmallVectorImpl<ISD::InputArg> &Ins,
151 const SmallVectorImpl<ISD::InputArg> &Ins,
159 const SmallVectorImpl<ISD::InputArg> &Ins,
MSP430ISelLowering.cpp 249 &Ins,
260 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
262 if (Ins.empty())
274 const SmallVectorImpl<ISD::InputArg> &Ins,
286 Outs, OutVals, Ins, dl, DAG, InVals);
301 &Ins,
314 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
442 const SmallVectorImpl<ISD::InputArg> &Ins,
554 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
564 const SmallVectorImpl<ISD::InputArg> &Ins,
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonCallingConvLower.cpp 70 &Ins,
73 unsigned NumArgs = Ins.size();
84 EVT ArgVT = Ins[i].VT;
85 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
183 Hexagon_CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
187 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
188 EVT VT = Ins[i].VT;
HexagonISelLowering.h 77 const SmallVectorImpl<ISD::InputArg> &Ins,
92 const SmallVectorImpl<ISD::InputArg> &Ins,
102 const SmallVectorImpl<ISD::InputArg> &Ins,
108 const SmallVectorImpl<ISD::InputArg> &Ins,
HexagonCallingConvLower.h 80 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
102 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
HexagonISelLowering.cpp 342 SmallVectorImpl<ISD::InputArg> &Ins,
354 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
376 const SmallVectorImpl<ISD::InputArg> &Ins,
417 Outs, OutVals, Ins, DAG);
581 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
799 SmallVectorImpl<ISD::InputArg> &Ins,
816 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
829 ISD::ArgFlagsTy Flags = Ins[i].Flags;
    [all...]
  /external/llvm/lib/Target/Mips/
MipsISelLowering.h 82 Ins
118 const SmallVectorImpl<ISD::InputArg> &Ins,
142 const SmallVectorImpl<ISD::InputArg> &Ins,
152 const SmallVectorImpl<ISD::InputArg> &Ins,
  /external/llvm/lib/Target/Sparc/
SparcISelLowering.h 74 const SmallVectorImpl<ISD::InputArg> &Ins,
83 const SmallVectorImpl<ISD::InputArg> &Ins,
  /external/llvm/lib/Target/PowerPC/
PPCISelLowering.h 377 const SmallVectorImpl<ISD::InputArg> &Ins,
420 const SmallVectorImpl<ISD::InputArg> &Ins,
431 const SmallVectorImpl<ISD::InputArg> &Ins,
437 const SmallVectorImpl<ISD::InputArg> &Ins,
446 const SmallVectorImpl<ISD::InputArg> &Ins,
466 const SmallVectorImpl<ISD::InputArg> &Ins,
472 const SmallVectorImpl<ISD::InputArg> &Ins,
481 const SmallVectorImpl<ISD::InputArg> &Ins,
489 const SmallVectorImpl<ISD::InputArg> &Ins,
PPCISelLowering.cpp     [all...]
  /external/llvm/lib/Target/XCore/
XCoreISelLowering.h 114 const SmallVectorImpl<ISD::InputArg> &Ins,
122 const SmallVectorImpl<ISD::InputArg> &Ins,
127 const SmallVectorImpl<ISD::InputArg> &Ins,
172 const SmallVectorImpl<ISD::InputArg> &Ins,
181 const SmallVectorImpl<ISD::InputArg> &Ins,
  /external/llvm/lib/Target/MBlaze/
MBlazeISelLowering.h 115 const SmallVectorImpl<ISD::InputArg> &Ins,
130 const SmallVectorImpl<ISD::InputArg> &Ins,
140 const SmallVectorImpl<ISD::InputArg> &Ins,
MBlazeISelLowering.cpp 688 const SmallVectorImpl<ISD::InputArg> &Ins,
825 if (!Ins.empty())
831 Ins, dl, DAG, InVals);
838 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins,
846 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze);
868 const SmallVectorImpl<ISD::InputArg> &Ins,
    [all...]
  /external/llvm/lib/Transforms/IPO/
PartialInlining.cpp 93 BasicBlock::iterator Ins = newReturnBlock->begin();
98 PHINode* retPhi = PHINode::Create(OldPhi->getType(), 2, "", Ins);
100 Ins = newReturnBlock->getFirstNonPHI();
IPConstantPropagation.cpp 250 Instruction *Ins = cast<Instruction>(*I);
257 if (ExtractValueInst *EV = dyn_cast<ExtractValueInst>(Ins))
270 Ins->replaceAllUsesWith(New);
271 Ins->eraseFromParent();
  /external/llvm/lib/Target/CellSPU/
SPUISelLowering.h 157 const SmallVectorImpl<ISD::InputArg> &Ins,
167 const SmallVectorImpl<ISD::InputArg> &Ins,
  /external/llvm/utils/TableGen/
CodeGenRegisters.h 70 std::pair<CompMap::iterator, bool> Ins =
72 return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
  /external/llvm/lib/Target/ARM/
ARMISelLowering.h 446 const SmallVectorImpl<ISD::InputArg> &Ins,
453 const SmallVectorImpl<ISD::InputArg> &Ins,
470 const SmallVectorImpl<ISD::InputArg> &Ins,
487 const SmallVectorImpl<ISD::InputArg> &Ins,
  /external/llvm/include/llvm/CodeGen/
CallingConvLower.h 196 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
223 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
  /external/llvm/lib/Target/X86/
X86ISelLowering.h 680 const SmallVectorImpl<ISD::InputArg> &Ins,
706 const SmallVectorImpl<ISD::InputArg> &Ins,
    [all...]
  /external/llvm/include/llvm/Transforms/Utils/
SSAUpdaterImpl.h 71 SmallVectorImpl<PhiT*> *Ins) :
72 Updater(U), AvailableVals(A), InsertedPHIs(Ins) { }

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