| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| SPUInstrInfo.cpp | 360 MachineInstrBuilder MIB;
368 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
374 MIB = BuildMI(&MBB, DL, get(SPU::BR));
375 MIB.addMBB(TBB);
378 DEBUG((*MIB).dump());
382 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
383 MIB.addSym(branchLabel);
384 MIB.addMBB(TBB);
388 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
389 MIB.addReg(Cond[1].getReg()).addMBB(TBB)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
98 addOffset(const MachineInstrBuilder &MIB, int Offset) {
99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
107 addRegOffset(const MachineInstrBuilder &MIB,
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
114 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
122 addFullAddress(const MachineInstrBuilder &MIB,
127 MIB.addReg(AM.Base.Reg)
[all...] |
| X86InstrInfo.cpp | [all...] |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| Thumb1FrameLowering.cpp | 280 MachineInstrBuilder MIB =
283 AddDefaultPred(MIB);
284 MIB->copyImplicitOps(&*MBBI);
304 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
305 AddDefaultPred(MIB);
323 MIB.addReg(Reg, getKillRegState(isKill));
325 MIB.setMIFlags(MachineInstr::FrameSetup);
343 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
344 AddDefaultPred(MIB);
354 (*MIB).setDesc(TII.get(ARM::tPOP_RET))
[all...] |
| Thumb1RegisterInfo.cpp | 129 MachineInstrBuilder MIB =
132 MIB = AddDefaultT1CC(MIB);
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
137 AddDefaultPred(MIB);
241 const MachineInstrBuilder MIB =
244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
260 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
262 MIB = AddDefaultT1CC(MIB)
[all...] |
| Thumb2SizeReduction.cpp | 455 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
457 MIB.addOperand(MI->getOperand(0));
458 MIB.addOperand(MI->getOperand(1));
461 MIB.addImm(OffsetImm / Scale);
466 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
471 MIB.addOperand(MI->getOperand(OpNum));
474 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
477 MIB.setMIFlags(MI->getFlags());
479 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
516 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc()
[all...] |
| ARMBaseInstrInfo.h | 302 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
303 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
307 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
308 return MIB.addReg(0);
312 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
314 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
318 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
319 return MIB.addReg(0);
|
| MLxExpansionPass.cpp | 225 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
229 MIB.addImm(LaneImm);
230 MIB.addImm(Pred).addReg(PredReg);
232 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
237 MIB.addReg(TmpReg, getKillRegState(true))
240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
242 MIB.addImm(Pred).addReg(PredReg);
|
| ARMBaseInstrInfo.cpp | 675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
676 MIB.addReg(SrcReg, getKillRegState(KillSrc));
678 MIB.addReg(SrcReg, getKillRegState(KillSrc));
679 AddDefaultPred(MIB);
732 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
736 return MIB.addReg(Reg, State);
739 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
740 return MIB.addReg(Reg, State, SubIdx);
808 MachineInstrBuilder MIB =
812 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI)
[all...] |
| ARMFastISel.cpp | 219 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
221 const MachineInstrBuilder &MIB,
267 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
268 MachineInstr *MI = &*MIB;
274 AddDefaultPred(MIB);
281 AddDefaultT1CC(MIB);
283 AddDefaultCC(MIB);
285 return MIB;
662 MachineInstrBuilder MIB;
665 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg
[all...] |
| ARMFrameLowering.cpp | 216 MachineInstrBuilder MIB =
220 AddDefaultCC(AddDefaultPred(MIB));
435 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
437 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
441 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
446 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
616 MachineInstrBuilder MIB =
620 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
622 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
627 AddDefaultPred(MIB);
[all...] |
| Thumb2ITBlockPass.cpp | 185 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
193 MachineBasicBlock::iterator InsertPos = MIB;
236 MIB.addImm(Mask);
|
| ARMLoadStoreOptimizer.cpp | 349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
779 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
786 MIB.addOperand(MI->getOperand(OpNum));
789 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
[all...] |
| Thumb2InstrInfo.cpp | 279 MachineInstrBuilder MIB =
284 AddDefaultCC(MIB);
411 MachineInstrBuilder MIB(&MI);
412 AddDefaultPred(MIB);
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 159 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
162 MIB.addReg(DestReg, RegState::Define);
165 MIB.addReg(ZeroReg);
168 MIB.addReg(SrcReg, getKillRegState(KillSrc));
239 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
241 return &*MIB;
382 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
385 MIB.addReg(Cond[i].getReg());
387 MIB.addMBB(TBB);
|
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 109 MachineInstrBuilder MIB = BuildMI(MBB, FirstMI, FirstMI->getDebugLoc(),
190 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
199 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
|
| MachineSSAUpdater.cpp | 190 MachineInstrBuilder MIB(InsertedPHI);
192 MIB.addReg(PredValues[i].second).addMBB(PredValues[i].first);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 622 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
633 MIB.addReg(0U); // undef
635 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
641 MIB.addCImm(CI);
643 MIB.addImm(CI->getSExtValue());
645 MIB.addFPImm(CF);
649 MIB.addReg(0U);
653 MIB.addReg(0U);
656 MIB.addImm(Offset).addMetadata(MDPtr)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 59 MachineInstr::mop_iterator MIB = MBB->operands_begin();
62 for (MachineInstr::mop_iterator MII = MIB; MII != MIE; ++MII) {
99 MachineBasicBlock::iterator MIB = MBB->begin();
121 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
171 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE))
395 return &*MIB;
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 121 MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE))
123 return &*MIB;
|
