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    Searched refs:Reg0 (Results 1 - 6 of 6) sorted by null

  /external/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 190 unsigned Reg0 = Op0.getReg();
191 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
195 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
197 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
  /external/llvm/lib/CodeGen/
TargetInstrInfoImpl.cpp 78 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
88 if (HasDef && Reg0 == Reg1 &&
91 Reg0 = Reg2;
93 } else if (HasDef && Reg0 == Reg2 &&
96 Reg0 = Reg1;
106 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead), SubReg0)
116 MI->getOperand(0).setReg(Reg0);
  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp     [all...]
Thumb2SizeReduction.cpp 598 unsigned Reg0 = MI->getOperand(0).getReg();
604 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
607 if (Reg0 != Reg2) {
610 if (Reg1 != Reg0)
617 } else if (Reg0 != Reg1) {
621 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
627 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
    [all...]
  /external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp     [all...]
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 136 unsigned Reg0 = MI->getOperand(0).getReg();
144 if (Reg0 == Reg1) {
158 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
161 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))

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