1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCInstrInfo.h" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCTargetMachine.h" 19 #include "PPCHazardRecognizers.h" 20 #include "MCTargetDesc/PPCPredicates.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineMemOperand.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/PseudoSourceValue.h" 26 #include "llvm/MC/MCAsmInfo.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/ADT/STLExtras.h" 32 33 #define GET_INSTRINFO_CTOR 34 #include "PPCGenInstrInfo.inc" 35 36 namespace llvm { 37 extern cl::opt<bool> DisablePPC32RS; 38 extern cl::opt<bool> DisablePPC64RS; 39 } 40 41 using namespace llvm; 42 43 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 44 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 45 TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 46 47 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 48 /// this target when scheduling the DAG. 49 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer( 50 const TargetMachine *TM, 51 const ScheduleDAG *DAG) const { 52 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective(); 53 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2) { 54 const InstrItineraryData *II = TM->getInstrItineraryData(); 55 return new PPCScoreboardHazardRecognizer(II, DAG); 56 } 57 58 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 59 } 60 61 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer 62 /// to use for this target when scheduling the DAG. 63 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer( 64 const InstrItineraryData *II, 65 const ScheduleDAG *DAG) const { 66 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective(); 67 68 // Most subtargets use a PPC970 recognizer. 69 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2) { 70 const TargetInstrInfo *TII = TM.getInstrInfo(); 71 assert(TII && "No InstrInfo?"); 72 73 return new PPCHazardRecognizer970(*TII); 74 } 75 76 return new PPCScoreboardHazardRecognizer(II, DAG); 77 } 78 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 79 int &FrameIndex) const { 80 switch (MI->getOpcode()) { 81 default: break; 82 case PPC::LD: 83 case PPC::LWZ: 84 case PPC::LFS: 85 case PPC::LFD: 86 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 87 MI->getOperand(2).isFI()) { 88 FrameIndex = MI->getOperand(2).getIndex(); 89 return MI->getOperand(0).getReg(); 90 } 91 break; 92 } 93 return 0; 94 } 95 96 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 97 int &FrameIndex) const { 98 switch (MI->getOpcode()) { 99 default: break; 100 case PPC::STD: 101 case PPC::STW: 102 case PPC::STFS: 103 case PPC::STFD: 104 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 105 MI->getOperand(2).isFI()) { 106 FrameIndex = MI->getOperand(2).getIndex(); 107 return MI->getOperand(0).getReg(); 108 } 109 break; 110 } 111 return 0; 112 } 113 114 // commuteInstruction - We can commute rlwimi instructions, but only if the 115 // rotate amt is zero. We also have to munge the immediates a bit. 116 MachineInstr * 117 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 118 MachineFunction &MF = *MI->getParent()->getParent(); 119 120 // Normal instructions can be commuted the obvious way. 121 if (MI->getOpcode() != PPC::RLWIMI) 122 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 123 124 // Cannot commute if it has a non-zero rotate count. 125 if (MI->getOperand(3).getImm() != 0) 126 return 0; 127 128 // If we have a zero rotate count, we have: 129 // M = mask(MB,ME) 130 // Op0 = (Op1 & ~M) | (Op2 & M) 131 // Change this to: 132 // M = mask((ME+1)&31, (MB-1)&31) 133 // Op0 = (Op2 & ~M) | (Op1 & M) 134 135 // Swap op1/op2 136 unsigned Reg0 = MI->getOperand(0).getReg(); 137 unsigned Reg1 = MI->getOperand(1).getReg(); 138 unsigned Reg2 = MI->getOperand(2).getReg(); 139 bool Reg1IsKill = MI->getOperand(1).isKill(); 140 bool Reg2IsKill = MI->getOperand(2).isKill(); 141 bool ChangeReg0 = false; 142 // If machine instrs are no longer in two-address forms, update 143 // destination register as well. 144 if (Reg0 == Reg1) { 145 // Must be two address instruction! 146 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 147 "Expecting a two-address instruction!"); 148 Reg2IsKill = false; 149 ChangeReg0 = true; 150 } 151 152 // Masks. 153 unsigned MB = MI->getOperand(4).getImm(); 154 unsigned ME = MI->getOperand(5).getImm(); 155 156 if (NewMI) { 157 // Create a new instruction. 158 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 159 bool Reg0IsDead = MI->getOperand(0).isDead(); 160 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 161 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 162 .addReg(Reg2, getKillRegState(Reg2IsKill)) 163 .addReg(Reg1, getKillRegState(Reg1IsKill)) 164 .addImm((ME+1) & 31) 165 .addImm((MB-1) & 31); 166 } 167 168 if (ChangeReg0) 169 MI->getOperand(0).setReg(Reg2); 170 MI->getOperand(2).setReg(Reg1); 171 MI->getOperand(1).setReg(Reg2); 172 MI->getOperand(2).setIsKill(Reg1IsKill); 173 MI->getOperand(1).setIsKill(Reg2IsKill); 174 175 // Swap the mask around. 176 MI->getOperand(4).setImm((ME+1) & 31); 177 MI->getOperand(5).setImm((MB-1) & 31); 178 return MI; 179 } 180 181 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 182 MachineBasicBlock::iterator MI) const { 183 DebugLoc DL; 184 BuildMI(MBB, MI, DL, get(PPC::NOP)); 185 } 186 187 188 // Branch analysis. 189 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 190 MachineBasicBlock *&FBB, 191 SmallVectorImpl<MachineOperand> &Cond, 192 bool AllowModify) const { 193 // If the block has no terminators, it just falls into the block after it. 194 MachineBasicBlock::iterator I = MBB.end(); 195 if (I == MBB.begin()) 196 return false; 197 --I; 198 while (I->isDebugValue()) { 199 if (I == MBB.begin()) 200 return false; 201 --I; 202 } 203 if (!isUnpredicatedTerminator(I)) 204 return false; 205 206 // Get the last instruction in the block. 207 MachineInstr *LastInst = I; 208 209 // If there is only one terminator instruction, process it. 210 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 211 if (LastInst->getOpcode() == PPC::B) { 212 if (!LastInst->getOperand(0).isMBB()) 213 return true; 214 TBB = LastInst->getOperand(0).getMBB(); 215 return false; 216 } else if (LastInst->getOpcode() == PPC::BCC) { 217 if (!LastInst->getOperand(2).isMBB()) 218 return true; 219 // Block ends with fall-through condbranch. 220 TBB = LastInst->getOperand(2).getMBB(); 221 Cond.push_back(LastInst->getOperand(0)); 222 Cond.push_back(LastInst->getOperand(1)); 223 return false; 224 } 225 // Otherwise, don't know what this is. 226 return true; 227 } 228 229 // Get the instruction before it if it's a terminator. 230 MachineInstr *SecondLastInst = I; 231 232 // If there are three terminators, we don't know what sort of block this is. 233 if (SecondLastInst && I != MBB.begin() && 234 isUnpredicatedTerminator(--I)) 235 return true; 236 237 // If the block ends with PPC::B and PPC:BCC, handle it. 238 if (SecondLastInst->getOpcode() == PPC::BCC && 239 LastInst->getOpcode() == PPC::B) { 240 if (!SecondLastInst->getOperand(2).isMBB() || 241 !LastInst->getOperand(0).isMBB()) 242 return true; 243 TBB = SecondLastInst->getOperand(2).getMBB(); 244 Cond.push_back(SecondLastInst->getOperand(0)); 245 Cond.push_back(SecondLastInst->getOperand(1)); 246 FBB = LastInst->getOperand(0).getMBB(); 247 return false; 248 } 249 250 // If the block ends with two PPC:Bs, handle it. The second one is not 251 // executed, so remove it. 252 if (SecondLastInst->getOpcode() == PPC::B && 253 LastInst->getOpcode() == PPC::B) { 254 if (!SecondLastInst->getOperand(0).isMBB()) 255 return true; 256 TBB = SecondLastInst->getOperand(0).getMBB(); 257 I = LastInst; 258 if (AllowModify) 259 I->eraseFromParent(); 260 return false; 261 } 262 263 // Otherwise, can't handle this. 264 return true; 265 } 266 267 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 268 MachineBasicBlock::iterator I = MBB.end(); 269 if (I == MBB.begin()) return 0; 270 --I; 271 while (I->isDebugValue()) { 272 if (I == MBB.begin()) 273 return 0; 274 --I; 275 } 276 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 277 return 0; 278 279 // Remove the branch. 280 I->eraseFromParent(); 281 282 I = MBB.end(); 283 284 if (I == MBB.begin()) return 1; 285 --I; 286 if (I->getOpcode() != PPC::BCC) 287 return 1; 288 289 // Remove the branch. 290 I->eraseFromParent(); 291 return 2; 292 } 293 294 unsigned 295 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 296 MachineBasicBlock *FBB, 297 const SmallVectorImpl<MachineOperand> &Cond, 298 DebugLoc DL) const { 299 // Shouldn't be a fall through. 300 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 301 assert((Cond.size() == 2 || Cond.size() == 0) && 302 "PPC branch conditions have two components!"); 303 304 // One-way branch. 305 if (FBB == 0) { 306 if (Cond.empty()) // Unconditional branch 307 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 308 else // Conditional branch 309 BuildMI(&MBB, DL, get(PPC::BCC)) 310 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 311 return 1; 312 } 313 314 // Two-way Conditional Branch. 315 BuildMI(&MBB, DL, get(PPC::BCC)) 316 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 317 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 318 return 2; 319 } 320 321 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 322 MachineBasicBlock::iterator I, DebugLoc DL, 323 unsigned DestReg, unsigned SrcReg, 324 bool KillSrc) const { 325 unsigned Opc; 326 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 327 Opc = PPC::OR; 328 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 329 Opc = PPC::OR8; 330 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 331 Opc = PPC::FMR; 332 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 333 Opc = PPC::MCRF; 334 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 335 Opc = PPC::VOR; 336 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 337 Opc = PPC::CROR; 338 else 339 llvm_unreachable("Impossible reg-to-reg copy"); 340 341 const MCInstrDesc &MCID = get(Opc); 342 if (MCID.getNumOperands() == 3) 343 BuildMI(MBB, I, DL, MCID, DestReg) 344 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 345 else 346 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 347 } 348 349 // This function returns true if a CR spill is necessary and false otherwise. 350 bool 351 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 352 unsigned SrcReg, bool isKill, 353 int FrameIdx, 354 const TargetRegisterClass *RC, 355 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 356 DebugLoc DL; 357 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { 358 if (SrcReg != PPC::LR) { 359 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 360 .addReg(SrcReg, 361 getKillRegState(isKill)), 362 FrameIdx)); 363 } else { 364 // FIXME: this spills LR immediately to memory in one step. To do this, 365 // we use R11, which we know cannot be used in the prolog/epilog. This is 366 // a hack. 367 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 368 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 369 .addReg(PPC::R11, 370 getKillRegState(isKill)), 371 FrameIdx)); 372 } 373 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { 374 if (SrcReg != PPC::LR8) { 375 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 376 .addReg(SrcReg, 377 getKillRegState(isKill)), 378 FrameIdx)); 379 } else { 380 // FIXME: this spills LR immediately to memory in one step. To do this, 381 // we use X11, which we know cannot be used in the prolog/epilog. This is 382 // a hack. 383 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); 384 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 385 .addReg(PPC::X11, 386 getKillRegState(isKill)), 387 FrameIdx)); 388 } 389 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { 390 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 391 .addReg(SrcReg, 392 getKillRegState(isKill)), 393 FrameIdx)); 394 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) { 395 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 396 .addReg(SrcReg, 397 getKillRegState(isKill)), 398 FrameIdx)); 399 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { 400 if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 401 (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { 402 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 403 .addReg(SrcReg, 404 getKillRegState(isKill)), 405 FrameIdx)); 406 return true; 407 } else { 408 // FIXME: We need a scatch reg here. The trouble with using R0 is that 409 // it's possible for the stack frame to be so big the save location is 410 // out of range of immediate offsets, necessitating another register. 411 // We hack this on Darwin by reserving R2. It's probably broken on Linux 412 // at the moment. 413 414 bool is64Bit = TM.getSubtargetImpl()->isPPC64(); 415 // We need to store the CR in the low 4-bits of the saved value. First, 416 // issue a MFCR to save all of the CRBits. 417 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 418 (is64Bit ? PPC::X2 : PPC::R2) : 419 (is64Bit ? PPC::X0 : PPC::R0); 420 NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::MFCR8pseud : 421 PPC::MFCRpseud), ScratchReg) 422 .addReg(SrcReg, getKillRegState(isKill))); 423 424 // If the saved register wasn't CR0, shift the bits left so that they are 425 // in CR0's slot. 426 if (SrcReg != PPC::CR0) { 427 unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4; 428 // rlwinm scratch, scratch, ShiftBits, 0, 31. 429 NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::RLWINM8 : 430 PPC::RLWINM), ScratchReg) 431 .addReg(ScratchReg).addImm(ShiftBits) 432 .addImm(0).addImm(31)); 433 } 434 435 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(is64Bit ? 436 PPC::STW8 : PPC::STW)) 437 .addReg(ScratchReg, 438 getKillRegState(isKill)), 439 FrameIdx)); 440 } 441 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { 442 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 443 // backend currently only uses CR1EQ as an individual bit, this should 444 // not cause any bug. If we need other uses of CR bits, the following 445 // code may be invalid. 446 unsigned Reg = 0; 447 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 448 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 449 Reg = PPC::CR0; 450 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 451 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 452 Reg = PPC::CR1; 453 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 454 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 455 Reg = PPC::CR2; 456 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 457 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 458 Reg = PPC::CR3; 459 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 460 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 461 Reg = PPC::CR4; 462 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 463 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 464 Reg = PPC::CR5; 465 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 466 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 467 Reg = PPC::CR6; 468 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 469 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 470 Reg = PPC::CR7; 471 472 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 473 PPC::CRRCRegisterClass, NewMIs); 474 475 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) { 476 // We don't have indexed addressing for vector loads. Emit: 477 // R0 = ADDI FI# 478 // STVX VAL, 0, R0 479 // 480 // FIXME: We use R0 here, because it isn't available for RA. 481 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 482 FrameIdx, 0, 0)); 483 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) 484 .addReg(SrcReg, getKillRegState(isKill)) 485 .addReg(PPC::R0) 486 .addReg(PPC::R0)); 487 } else { 488 llvm_unreachable("Unknown regclass!"); 489 } 490 491 return false; 492 } 493 494 void 495 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 496 MachineBasicBlock::iterator MI, 497 unsigned SrcReg, bool isKill, int FrameIdx, 498 const TargetRegisterClass *RC, 499 const TargetRegisterInfo *TRI) const { 500 MachineFunction &MF = *MBB.getParent(); 501 SmallVector<MachineInstr*, 4> NewMIs; 502 503 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) { 504 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 505 FuncInfo->setSpillsCR(); 506 } 507 508 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 509 MBB.insert(MI, NewMIs[i]); 510 511 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 512 MachineMemOperand *MMO = 513 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 514 MachineMemOperand::MOStore, 515 MFI.getObjectSize(FrameIdx), 516 MFI.getObjectAlignment(FrameIdx)); 517 NewMIs.back()->addMemOperand(MF, MMO); 518 } 519 520 bool 521 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 522 unsigned DestReg, int FrameIdx, 523 const TargetRegisterClass *RC, 524 SmallVectorImpl<MachineInstr*> &NewMIs)const{ 525 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { 526 if (DestReg != PPC::LR) { 527 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 528 DestReg), FrameIdx)); 529 } else { 530 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 531 PPC::R11), FrameIdx)); 532 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); 533 } 534 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { 535 if (DestReg != PPC::LR8) { 536 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 537 FrameIdx)); 538 } else { 539 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), 540 PPC::X11), FrameIdx)); 541 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11)); 542 } 543 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { 544 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 545 FrameIdx)); 546 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) { 547 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 548 FrameIdx)); 549 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { 550 if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 551 (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { 552 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, 553 get(PPC::RESTORE_CR), DestReg) 554 , FrameIdx)); 555 return true; 556 } else { 557 // FIXME: We need a scatch reg here. The trouble with using R0 is that 558 // it's possible for the stack frame to be so big the save location is 559 // out of range of immediate offsets, necessitating another register. 560 // We hack this on Darwin by reserving R2. It's probably broken on Linux 561 // at the moment. 562 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 563 PPC::R2 : PPC::R0; 564 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 565 ScratchReg), FrameIdx)); 566 567 // If the reloaded register isn't CR0, shift the bits right so that they are 568 // in the right CR's slot. 569 if (DestReg != PPC::CR0) { 570 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 571 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 572 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 573 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) 574 .addImm(31)); 575 } 576 577 NewMIs.push_back(BuildMI(MF, DL, get(TM.getSubtargetImpl()->isPPC64() ? 578 PPC::MTCRF8 : PPC::MTCRF), DestReg) 579 .addReg(ScratchReg)); 580 } 581 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { 582 583 unsigned Reg = 0; 584 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 585 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 586 Reg = PPC::CR0; 587 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 588 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 589 Reg = PPC::CR1; 590 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 591 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 592 Reg = PPC::CR2; 593 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 594 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 595 Reg = PPC::CR3; 596 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 597 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 598 Reg = PPC::CR4; 599 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 600 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 601 Reg = PPC::CR5; 602 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 603 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 604 Reg = PPC::CR6; 605 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 606 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 607 Reg = PPC::CR7; 608 609 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 610 PPC::CRRCRegisterClass, NewMIs); 611 612 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) { 613 // We don't have indexed addressing for vector loads. Emit: 614 // R0 = ADDI FI# 615 // Dest = LVX 0, R0 616 // 617 // FIXME: We use R0 here, because it isn't available for RA. 618 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 619 FrameIdx, 0, 0)); 620 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) 621 .addReg(PPC::R0)); 622 } else { 623 llvm_unreachable("Unknown regclass!"); 624 } 625 626 return false; 627 } 628 629 void 630 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 631 MachineBasicBlock::iterator MI, 632 unsigned DestReg, int FrameIdx, 633 const TargetRegisterClass *RC, 634 const TargetRegisterInfo *TRI) const { 635 MachineFunction &MF = *MBB.getParent(); 636 SmallVector<MachineInstr*, 4> NewMIs; 637 DebugLoc DL; 638 if (MI != MBB.end()) DL = MI->getDebugLoc(); 639 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs)) { 640 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 641 FuncInfo->setSpillsCR(); 642 } 643 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 644 MBB.insert(MI, NewMIs[i]); 645 646 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 647 MachineMemOperand *MMO = 648 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 649 MachineMemOperand::MOLoad, 650 MFI.getObjectSize(FrameIdx), 651 MFI.getObjectAlignment(FrameIdx)); 652 NewMIs.back()->addMemOperand(MF, MMO); 653 } 654 655 MachineInstr* 656 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 657 int FrameIx, uint64_t Offset, 658 const MDNode *MDPtr, 659 DebugLoc DL) const { 660 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); 661 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr); 662 return &*MIB; 663 } 664 665 bool PPCInstrInfo:: 666 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 667 assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 668 // Leave the CR# the same, but invert the condition. 669 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 670 return false; 671 } 672 673 /// GetInstSize - Return the number of bytes of code the specified 674 /// instruction may be. This returns the maximum number of bytes. 675 /// 676 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 677 switch (MI->getOpcode()) { 678 case PPC::INLINEASM: { // Inline Asm: Variable size. 679 const MachineFunction *MF = MI->getParent()->getParent(); 680 const char *AsmStr = MI->getOperand(0).getSymbolName(); 681 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 682 } 683 case PPC::PROLOG_LABEL: 684 case PPC::EH_LABEL: 685 case PPC::GC_LABEL: 686 case PPC::DBG_VALUE: 687 return 0; 688 case PPC::BL8_NOP_ELF: 689 case PPC::BLA8_NOP_ELF: 690 return 8; 691 default: 692 return 4; // PowerPC instructions are all 4 bytes 693 } 694 } 695
