1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes an abstract interface used to get information about a 11 // target machines register file. This information is used for a variety of 12 // purposed, especially register allocation. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17 #define LLVM_TARGET_TARGETREGISTERINFO_H 18 19 #include "llvm/MC/MCRegisterInfo.h" 20 #include "llvm/CodeGen/MachineBasicBlock.h" 21 #include "llvm/CodeGen/ValueTypes.h" 22 #include "llvm/ADT/ArrayRef.h" 23 #include "llvm/CallingConv.h" 24 #include <cassert> 25 #include <functional> 26 27 namespace llvm { 28 29 class BitVector; 30 class MachineFunction; 31 class RegScavenger; 32 template<class T> class SmallVectorImpl; 33 class raw_ostream; 34 35 class TargetRegisterClass { 36 public: 37 typedef const uint16_t* iterator; 38 typedef const uint16_t* const_iterator; 39 typedef const MVT::SimpleValueType* vt_iterator; 40 typedef const TargetRegisterClass* const * sc_iterator; 41 42 // Instance variables filled by tablegen, do not use! 43 const MCRegisterClass *MC; 44 const vt_iterator VTs; 45 const unsigned *SubClassMask; 46 const sc_iterator SuperClasses; 47 const sc_iterator SuperRegClasses; 48 ArrayRef<uint16_t> (*OrderFunc)(const MachineFunction&); 49 50 /// getID() - Return the register class ID number. 51 /// 52 unsigned getID() const { return MC->getID(); } 53 54 /// getName() - Return the register class name for debugging. 55 /// 56 const char *getName() const { return MC->getName(); } 57 58 /// begin/end - Return all of the registers in this class. 59 /// 60 iterator begin() const { return MC->begin(); } 61 iterator end() const { return MC->end(); } 62 63 /// getNumRegs - Return the number of registers in this class. 64 /// 65 unsigned getNumRegs() const { return MC->getNumRegs(); } 66 67 /// getRegister - Return the specified register in the class. 68 /// 69 unsigned getRegister(unsigned i) const { 70 return MC->getRegister(i); 71 } 72 73 /// contains - Return true if the specified register is included in this 74 /// register class. This does not include virtual registers. 75 bool contains(unsigned Reg) const { 76 return MC->contains(Reg); 77 } 78 79 /// contains - Return true if both registers are in this class. 80 bool contains(unsigned Reg1, unsigned Reg2) const { 81 return MC->contains(Reg1, Reg2); 82 } 83 84 /// getSize - Return the size of the register in bytes, which is also the size 85 /// of a stack slot allocated to hold a spilled copy of this register. 86 unsigned getSize() const { return MC->getSize(); } 87 88 /// getAlignment - Return the minimum required alignment for a register of 89 /// this class. 90 unsigned getAlignment() const { return MC->getAlignment(); } 91 92 /// getCopyCost - Return the cost of copying a value between two registers in 93 /// this class. A negative number means the register class is very expensive 94 /// to copy e.g. status flag register classes. 95 int getCopyCost() const { return MC->getCopyCost(); } 96 97 /// isAllocatable - Return true if this register class may be used to create 98 /// virtual registers. 99 bool isAllocatable() const { return MC->isAllocatable(); } 100 101 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 102 /// 103 bool hasType(EVT vt) const { 104 for(int i = 0; VTs[i] != MVT::Other; ++i) 105 if (EVT(VTs[i]) == vt) 106 return true; 107 return false; 108 } 109 110 /// vt_begin / vt_end - Loop over all of the value types that can be 111 /// represented by values in this register class. 112 vt_iterator vt_begin() const { 113 return VTs; 114 } 115 116 vt_iterator vt_end() const { 117 vt_iterator I = VTs; 118 while (*I != MVT::Other) ++I; 119 return I; 120 } 121 122 /// superregclasses_begin / superregclasses_end - Loop over all of 123 /// the superreg register classes of this register class. 124 sc_iterator superregclasses_begin() const { 125 return SuperRegClasses; 126 } 127 128 sc_iterator superregclasses_end() const { 129 sc_iterator I = SuperRegClasses; 130 while (*I != NULL) ++I; 131 return I; 132 } 133 134 /// hasSubClass - return true if the specified TargetRegisterClass 135 /// is a proper sub-class of this TargetRegisterClass. 136 bool hasSubClass(const TargetRegisterClass *RC) const { 137 return RC != this && hasSubClassEq(RC); 138 } 139 140 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 141 /// class. 142 bool hasSubClassEq(const TargetRegisterClass *RC) const { 143 unsigned ID = RC->getID(); 144 return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 145 } 146 147 /// hasSuperClass - return true if the specified TargetRegisterClass is a 148 /// proper super-class of this TargetRegisterClass. 149 bool hasSuperClass(const TargetRegisterClass *RC) const { 150 return RC->hasSubClass(this); 151 } 152 153 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 154 /// class. 155 bool hasSuperClassEq(const TargetRegisterClass *RC) const { 156 return RC->hasSubClassEq(this); 157 } 158 159 /// getSubClassMask - Returns a bit vector of subclasses, including this one. 160 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 161 /// use it. 162 const uint32_t *getSubClassMask() const { 163 return SubClassMask; 164 } 165 166 /// getSuperClasses - Returns a NULL terminated list of super-classes. The 167 /// classes are ordered by ID which is also a topological ordering from large 168 /// to small classes. The list does NOT include the current class. 169 sc_iterator getSuperClasses() const { 170 return SuperClasses; 171 } 172 173 /// isASubClass - return true if this TargetRegisterClass is a subset 174 /// class of at least one other TargetRegisterClass. 175 bool isASubClass() const { 176 return SuperClasses[0] != 0; 177 } 178 179 /// getRawAllocationOrder - Returns the preferred order for allocating 180 /// registers from this register class in MF. The raw order comes directly 181 /// from the .td file and may include reserved registers that are not 182 /// allocatable. Register allocators should also make sure to allocate 183 /// callee-saved registers only after all the volatiles are used. The 184 /// RegisterClassInfo class provides filtered allocation orders with 185 /// callee-saved registers moved to the end. 186 /// 187 /// The MachineFunction argument can be used to tune the allocatable 188 /// registers based on the characteristics of the function, subtarget, or 189 /// other criteria. 190 /// 191 /// By default, this method returns all registers in the class. 192 /// 193 ArrayRef<uint16_t> getRawAllocationOrder(const MachineFunction &MF) const { 194 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 195 } 196 }; 197 198 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 199 /// registers. These are used by codegen, not by MC. 200 struct TargetRegisterInfoDesc { 201 unsigned CostPerUse; // Extra cost of instructions using register. 202 bool inAllocatableClass; // Register belongs to an allocatable regclass. 203 }; 204 205 /// Each TargetRegisterClass has a per register weight, and weight 206 /// limit which must be less than the limits of its pressure sets. 207 struct RegClassWeight { 208 unsigned RegWeight; 209 unsigned WeightLimit; 210 }; 211 212 /// TargetRegisterInfo base class - We assume that the target defines a static 213 /// array of TargetRegisterDesc objects that represent all of the machine 214 /// registers that the target has. As such, we simply have to track a pointer 215 /// to this array so that we can turn register number into a register 216 /// descriptor. 217 /// 218 class TargetRegisterInfo : public MCRegisterInfo { 219 public: 220 typedef const TargetRegisterClass * const * regclass_iterator; 221 private: 222 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 223 const char *const *SubRegIndexNames; // Names of subreg indexes. 224 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 225 226 protected: 227 TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 228 regclass_iterator RegClassBegin, 229 regclass_iterator RegClassEnd, 230 const char *const *subregindexnames); 231 virtual ~TargetRegisterInfo(); 232 public: 233 234 // Register numbers can represent physical registers, virtual registers, and 235 // sometimes stack slots. The unsigned values are divided into these ranges: 236 // 237 // 0 Not a register, can be used as a sentinel. 238 // [1;2^30) Physical registers assigned by TableGen. 239 // [2^30;2^31) Stack slots. (Rarely used.) 240 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 241 // 242 // Further sentinels can be allocated from the small negative integers. 243 // DenseMapInfo<unsigned> uses -1u and -2u. 244 245 /// isStackSlot - Sometimes it is useful the be able to store a non-negative 246 /// frame index in a variable that normally holds a register. isStackSlot() 247 /// returns true if Reg is in the range used for stack slots. 248 /// 249 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 250 /// slots, so if a variable may contains a stack slot, always check 251 /// isStackSlot() first. 252 /// 253 static bool isStackSlot(unsigned Reg) { 254 return int(Reg) >= (1 << 30); 255 } 256 257 /// stackSlot2Index - Compute the frame index from a register value 258 /// representing a stack slot. 259 static int stackSlot2Index(unsigned Reg) { 260 assert(isStackSlot(Reg) && "Not a stack slot"); 261 return int(Reg - (1u << 30)); 262 } 263 264 /// index2StackSlot - Convert a non-negative frame index to a stack slot 265 /// register value. 266 static unsigned index2StackSlot(int FI) { 267 assert(FI >= 0 && "Cannot hold a negative frame index."); 268 return FI + (1u << 30); 269 } 270 271 /// isPhysicalRegister - Return true if the specified register number is in 272 /// the physical register namespace. 273 static bool isPhysicalRegister(unsigned Reg) { 274 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 275 return int(Reg) > 0; 276 } 277 278 /// isVirtualRegister - Return true if the specified register number is in 279 /// the virtual register namespace. 280 static bool isVirtualRegister(unsigned Reg) { 281 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 282 return int(Reg) < 0; 283 } 284 285 /// virtReg2Index - Convert a virtual register number to a 0-based index. 286 /// The first virtual register in a function will get the index 0. 287 static unsigned virtReg2Index(unsigned Reg) { 288 assert(isVirtualRegister(Reg) && "Not a virtual register"); 289 return Reg & ~(1u << 31); 290 } 291 292 /// index2VirtReg - Convert a 0-based index to a virtual register number. 293 /// This is the inverse operation of VirtReg2IndexFunctor below. 294 static unsigned index2VirtReg(unsigned Index) { 295 return Index | (1u << 31); 296 } 297 298 /// getMinimalPhysRegClass - Returns the Register Class of a physical 299 /// register of the given type, picking the most sub register class of 300 /// the right type that contains this physreg. 301 const TargetRegisterClass * 302 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 303 304 /// getAllocatableSet - Returns a bitset indexed by register number 305 /// indicating if a register is allocatable or not. If a register class is 306 /// specified, returns the subset for the class. 307 BitVector getAllocatableSet(const MachineFunction &MF, 308 const TargetRegisterClass *RC = NULL) const; 309 310 /// getCostPerUse - Return the additional cost of using this register instead 311 /// of other registers in its class. 312 unsigned getCostPerUse(unsigned RegNo) const { 313 return InfoDesc[RegNo].CostPerUse; 314 } 315 316 /// isInAllocatableClass - Return true if the register is in the allocation 317 /// of any register class. 318 bool isInAllocatableClass(unsigned RegNo) const { 319 return InfoDesc[RegNo].inAllocatableClass; 320 } 321 322 /// getSubRegIndexName - Return the human-readable symbolic target-specific 323 /// name for the specified SubRegIndex. 324 const char *getSubRegIndexName(unsigned SubIdx) const { 325 assert(SubIdx && "This is not a subregister index"); 326 return SubRegIndexNames[SubIdx-1]; 327 } 328 329 /// regsOverlap - Returns true if the two registers are equal or alias each 330 /// other. The registers may be virtual register. 331 bool regsOverlap(unsigned regA, unsigned regB) const { 332 if (regA == regB) return true; 333 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 334 return false; 335 for (const uint16_t *regList = getOverlaps(regA)+1; *regList; ++regList) { 336 if (*regList == regB) return true; 337 } 338 return false; 339 } 340 341 /// isSubRegister - Returns true if regB is a sub-register of regA. 342 /// 343 bool isSubRegister(unsigned regA, unsigned regB) const { 344 return isSuperRegister(regB, regA); 345 } 346 347 /// isSuperRegister - Returns true if regB is a super-register of regA. 348 /// 349 bool isSuperRegister(unsigned regA, unsigned regB) const { 350 for (const uint16_t *regList = getSuperRegisters(regA); *regList;++regList){ 351 if (*regList == regB) return true; 352 } 353 return false; 354 } 355 356 /// getCalleeSavedRegs - Return a null-terminated list of all of the 357 /// callee saved registers on this target. The register should be in the 358 /// order of desired callee-save stack frame offset. The first register is 359 /// closest to the incoming stack pointer if stack grows down, and vice versa. 360 /// 361 virtual const uint16_t* getCalleeSavedRegs(const MachineFunction *MF = 0) 362 const = 0; 363 364 /// getCallPreservedMask - Return a mask of call-preserved registers for the 365 /// given calling convention on the current sub-target. The mask should 366 /// include all call-preserved aliases. This is used by the register 367 /// allocator to determine which registers can be live across a call. 368 /// 369 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 370 /// A set bit indicates that all bits of the corresponding register are 371 /// preserved across the function call. The bit mask is expected to be 372 /// sub-register complete, i.e. if A is preserved, so are all its 373 /// sub-registers. 374 /// 375 /// Bits are numbered from the LSB, so the bit for physical register Reg can 376 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 377 /// 378 /// A NULL pointer means that no register mask will be used, and call 379 /// instructions should use implicit-def operands to indicate call clobbered 380 /// registers. 381 /// 382 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { 383 // The default mask clobbers everything. All targets should override. 384 return 0; 385 } 386 387 /// getReservedRegs - Returns a bitset indexed by physical register number 388 /// indicating if a register is a special register that has particular uses 389 /// and should be considered unavailable at all times, e.g. SP, RA. This is 390 /// used by register scavenger to determine what registers are free. 391 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 392 393 /// getMatchingSuperReg - Return a super-register of the specified register 394 /// Reg so its sub-register of index SubIdx is Reg. 395 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 396 const TargetRegisterClass *RC) const { 397 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 398 } 399 400 /// canCombineSubRegIndices - Given a register class and a list of 401 /// subregister indices, return true if it's possible to combine the 402 /// subregister indices into one that corresponds to a larger 403 /// subregister. Return the new subregister index by reference. Note the 404 /// new index may be zero if the given subregisters can be combined to 405 /// form the whole register. 406 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 407 SmallVectorImpl<unsigned> &SubIndices, 408 unsigned &NewSubIdx) const { 409 return 0; 410 } 411 412 /// getMatchingSuperRegClass - Return a subclass of the specified register 413 /// class A so that each register in it has a sub-register of the 414 /// specified sub-register index which is in the specified register class B. 415 /// 416 /// TableGen will synthesize missing A sub-classes. 417 virtual const TargetRegisterClass * 418 getMatchingSuperRegClass(const TargetRegisterClass *A, 419 const TargetRegisterClass *B, unsigned Idx) const =0; 420 421 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 422 /// supports the sub-register index Idx. 423 /// If no such sub-class exists, return NULL. 424 /// If all registers in RC already have an Idx sub-register, return RC. 425 /// 426 /// TableGen generates a version of this function that is good enough in most 427 /// cases. Targets can override if they have constraints that TableGen 428 /// doesn't understand. For example, the x86 sub_8bit sub-register index is 429 /// supported by the full GR32 register class in 64-bit mode, but only by the 430 /// GR32_ABCD regiister class in 32-bit mode. 431 /// 432 /// TableGen will synthesize missing RC sub-classes. 433 virtual const TargetRegisterClass * 434 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0; 435 436 /// composeSubRegIndices - Return the subregister index you get from composing 437 /// two subregister indices. 438 /// 439 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 440 /// returns c. Note that composeSubRegIndices does not tell you about illegal 441 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 442 /// b, composeSubRegIndices doesn't tell you. 443 /// 444 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 445 /// ssub_0:S0 - ssub_3:S3 subregs. 446 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 447 /// 448 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 449 // This default implementation is correct for most targets. 450 return b; 451 } 452 453 //===--------------------------------------------------------------------===// 454 // Register Class Information 455 // 456 457 /// Register class iterators 458 /// 459 regclass_iterator regclass_begin() const { return RegClassBegin; } 460 regclass_iterator regclass_end() const { return RegClassEnd; } 461 462 unsigned getNumRegClasses() const { 463 return (unsigned)(regclass_end()-regclass_begin()); 464 } 465 466 /// getRegClass - Returns the register class associated with the enumeration 467 /// value. See class MCOperandInfo. 468 const TargetRegisterClass *getRegClass(unsigned i) const { 469 assert(i < getNumRegClasses() && "Register Class ID out of range"); 470 return RegClassBegin[i]; 471 } 472 473 /// getCommonSubClass - find the largest common subclass of A and B. Return 474 /// NULL if there is no common subclass. 475 const TargetRegisterClass * 476 getCommonSubClass(const TargetRegisterClass *A, 477 const TargetRegisterClass *B) const; 478 479 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 480 /// values. If a target supports multiple different pointer register classes, 481 /// kind specifies which one is indicated. 482 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 483 llvm_unreachable("Target didn't implement getPointerRegClass!"); 484 } 485 486 /// getCrossCopyRegClass - Returns a legal register class to copy a register 487 /// in the specified class to or from. If it is possible to copy the register 488 /// directly without using a cross register class copy, return the specified 489 /// RC. Returns NULL if it is not possible to copy between a two registers of 490 /// the specified class. 491 virtual const TargetRegisterClass * 492 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 493 return RC; 494 } 495 496 /// getLargestLegalSuperClass - Returns the largest super class of RC that is 497 /// legal to use in the current sub-target and has the same spill size. 498 /// The returned register class can be used to create virtual registers which 499 /// means that all its registers can be copied and spilled. 500 virtual const TargetRegisterClass* 501 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 502 /// The default implementation is very conservative and doesn't allow the 503 /// register allocator to inflate register classes. 504 return RC; 505 } 506 507 /// getRegPressureLimit - Return the register pressure "high water mark" for 508 /// the specific register class. The scheduler is in high register pressure 509 /// mode (for the specific register class) if it goes over the limit. 510 /// 511 /// Note: this is the old register pressure model that relies on a manually 512 /// specified representative register class per value type. 513 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 514 MachineFunction &MF) const { 515 return 0; 516 } 517 518 /// Get the weight in units of pressure for this register class. 519 virtual const RegClassWeight &getRegClassWeight( 520 const TargetRegisterClass *RC) const = 0; 521 522 /// Get the number of dimensions of register pressure. 523 virtual unsigned getNumRegPressureSets() const = 0; 524 525 /// Get the register unit pressure limit for this dimension. 526 /// This limit must be adjusted dynamically for reserved registers. 527 virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0; 528 529 /// Get the dimensions of register pressure impacted by this register class. 530 /// Returns a -1 terminated array of pressure set IDs. 531 virtual const int *getRegClassPressureSets( 532 const TargetRegisterClass *RC) const = 0; 533 534 /// getRawAllocationOrder - Returns the register allocation order for a 535 /// specified register class with a target-dependent hint. The returned list 536 /// may contain reserved registers that cannot be allocated. 537 /// 538 /// Register allocators need only call this function to resolve 539 /// target-dependent hints, but it should work without hinting as well. 540 virtual ArrayRef<uint16_t> 541 getRawAllocationOrder(const TargetRegisterClass *RC, 542 unsigned HintType, unsigned HintReg, 543 const MachineFunction &MF) const { 544 return RC->getRawAllocationOrder(MF); 545 } 546 547 /// ResolveRegAllocHint - Resolves the specified register allocation hint 548 /// to a physical register. Returns the physical register if it is successful. 549 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 550 const MachineFunction &MF) const { 551 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 552 return Reg; 553 return 0; 554 } 555 556 /// avoidWriteAfterWrite - Return true if the register allocator should avoid 557 /// writing a register from RC in two consecutive instructions. 558 /// This can avoid pipeline stalls on certain architectures. 559 /// It does cause increased register pressure, though. 560 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 561 return false; 562 } 563 564 /// UpdateRegAllocHint - A callback to allow target a chance to update 565 /// register allocation hints when a register is "changed" (e.g. coalesced) 566 /// to another register. e.g. On ARM, some virtual registers should target 567 /// register pairs, if one of pair is coalesced to another register, the 568 /// allocation hint of the other half of the pair should be changed to point 569 /// to the new register. 570 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 571 MachineFunction &MF) const { 572 // Do nothing. 573 } 574 575 /// requiresRegisterScavenging - returns true if the target requires (and can 576 /// make use of) the register scavenger. 577 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 578 return false; 579 } 580 581 /// useFPForScavengingIndex - returns true if the target wants to use 582 /// frame pointer based accesses to spill to the scavenger emergency spill 583 /// slot. 584 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 585 return true; 586 } 587 588 /// requiresFrameIndexScavenging - returns true if the target requires post 589 /// PEI scavenging of registers for materializing frame index constants. 590 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 591 return false; 592 } 593 594 /// requiresVirtualBaseRegisters - Returns true if the target wants the 595 /// LocalStackAllocation pass to be run and virtual base registers 596 /// used for more efficient stack access. 597 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 598 return false; 599 } 600 601 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 602 /// the stack frame of the given function for the specified register. e.g. On 603 /// x86, if the frame register is required, the first fixed stack object is 604 /// reserved as its spill slot. This tells PEI not to create a new stack frame 605 /// object for the given register. It should be called only after 606 /// processFunctionBeforeCalleeSavedScan(). 607 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 608 int &FrameIdx) const { 609 return false; 610 } 611 612 /// needsStackRealignment - true if storage within the function requires the 613 /// stack pointer to be aligned more than the normal calling convention calls 614 /// for. 615 virtual bool needsStackRealignment(const MachineFunction &MF) const { 616 return false; 617 } 618 619 /// getFrameIndexInstrOffset - Get the offset from the referenced frame 620 /// index in the instruction, if there is one. 621 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 622 int Idx) const { 623 return 0; 624 } 625 626 /// needsFrameBaseReg - Returns true if the instruction's frame index 627 /// reference would be better served by a base register other than FP 628 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 629 /// references it should create new base registers for. 630 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 631 return false; 632 } 633 634 /// materializeFrameBaseRegister - Insert defining instruction(s) for 635 /// BaseReg to be a pointer to FrameIdx before insertion point I. 636 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 637 unsigned BaseReg, int FrameIdx, 638 int64_t Offset) const { 639 llvm_unreachable("materializeFrameBaseRegister does not exist on this " 640 "target"); 641 } 642 643 /// resolveFrameIndex - Resolve a frame index operand of an instruction 644 /// to reference the indicated base register plus offset instead. 645 virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 646 unsigned BaseReg, int64_t Offset) const { 647 llvm_unreachable("resolveFrameIndex does not exist on this target"); 648 } 649 650 /// isFrameOffsetLegal - Determine whether a given offset immediate is 651 /// encodable to resolve a frame index. 652 virtual bool isFrameOffsetLegal(const MachineInstr *MI, 653 int64_t Offset) const { 654 llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 655 } 656 657 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 658 /// code insertion to eliminate call frame setup and destroy pseudo 659 /// instructions (but only if the Target is using them). It is responsible 660 /// for eliminating these instructions, replacing them with concrete 661 /// instructions. This method need only be implemented if using call frame 662 /// setup/destroy pseudo instructions. 663 /// 664 virtual void 665 eliminateCallFramePseudoInstr(MachineFunction &MF, 666 MachineBasicBlock &MBB, 667 MachineBasicBlock::iterator MI) const { 668 llvm_unreachable("Call Frame Pseudo Instructions do not exist on this " 669 "target!"); 670 } 671 672 673 /// saveScavengerRegister - Spill the register so it can be used by the 674 /// register scavenger. Return true if the register was spilled, false 675 /// otherwise. If this function does not spill the register, the scavenger 676 /// will instead spill it to the emergency spill slot. 677 /// 678 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 679 MachineBasicBlock::iterator I, 680 MachineBasicBlock::iterator &UseMI, 681 const TargetRegisterClass *RC, 682 unsigned Reg) const { 683 return false; 684 } 685 686 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 687 /// frame indices from instructions which may use them. The instruction 688 /// referenced by the iterator contains an MO_FrameIndex operand which must be 689 /// eliminated by this method. This method may modify or replace the 690 /// specified instruction, as long as it keeps the iterator pointing at the 691 /// finished product. SPAdj is the SP adjustment due to call frame setup 692 /// instruction. 693 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 694 int SPAdj, RegScavenger *RS=NULL) const = 0; 695 696 //===--------------------------------------------------------------------===// 697 /// Debug information queries. 698 699 /// getFrameRegister - This method should return the register used as a base 700 /// for values allocated in the current stack frame. 701 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 702 703 /// getCompactUnwindRegNum - This function maps the register to the number for 704 /// compact unwind encoding. Return -1 if the register isn't valid. 705 virtual int getCompactUnwindRegNum(unsigned, bool) const { 706 return -1; 707 } 708 }; 709 710 711 // This is useful when building IndexedMaps keyed on virtual registers 712 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 713 unsigned operator()(unsigned Reg) const { 714 return TargetRegisterInfo::virtReg2Index(Reg); 715 } 716 }; 717 718 /// PrintReg - Helper class for printing registers on a raw_ostream. 719 /// Prints virtual and physical registers with or without a TRI instance. 720 /// 721 /// The format is: 722 /// %noreg - NoRegister 723 /// %vreg5 - a virtual register. 724 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 725 /// %EAX - a physical register 726 /// %physreg17 - a physical register when no TRI instance given. 727 /// 728 /// Usage: OS << PrintReg(Reg, TRI) << '\n'; 729 /// 730 class PrintReg { 731 const TargetRegisterInfo *TRI; 732 unsigned Reg; 733 unsigned SubIdx; 734 public: 735 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 736 : TRI(tri), Reg(reg), SubIdx(subidx) {} 737 void print(raw_ostream&) const; 738 }; 739 740 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 741 PR.print(OS); 742 return OS; 743 } 744 745 } // End llvm namespace 746 747 #endif 748