| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAGInfo.h | 47 /// SDValue if the target declines to use custom code and a different
56 virtual SDValue
58 SDValue Chain,
59 SDValue Op1, SDValue Op2,
60 SDValue Op3, unsigned Align, bool isVolatile,
64 return SDValue();
71 /// SDValue if the target declines to use custom code and a different
73 virtual SDValue
75 SDValue Chain
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 83 DenseMap<SDValue, SDValue> PromotedIntegers;
87 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedIntegers;
91 DenseMap<SDValue, SDValue> SoftenedFloats;
95 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedFloats
[all...] |
| InstrEmitter.h | 44 DenseMap<SDValue, unsigned> &VRBaseMap);
54 DenseMap<SDValue, unsigned> &VRBaseMap);
58 unsigned getVR(SDValue Op,
59 DenseMap<SDValue, unsigned> &VRBaseMap);
64 void AddRegisterOperand(MachineInstr *MI, SDValue Op,
67 DenseMap<SDValue, unsigned> &VRBaseMap,
74 void AddOperand(MachineInstr *MI, SDValue Op,
77 DenseMap<SDValue, unsigned> &VRBaseMap,
88 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap,
96 DenseMap<SDValue, unsigned> &VRBaseMap)
[all...] |
| LegalizeVectorOps.cpp | 43 DenseMap<SDValue, SDValue> LegalizedNodes;
46 void AddLegalizedOperand(SDValue From, SDValue To) {
54 SDValue LegalizeOp(SDValue Op);
56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
58 SDValue UnrollVSETCC(SDValue Op)
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXSelectionDAGInfo.h | 33 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
34 SDValue Chain,
35 SDValue Dst, SDValue Src,
36 SDValue Size, unsigned Align,
42 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
43 SDValue Chain,
44 SDValue Op1, SDValue Op2,
45 SDValue Op3, unsigned Align
[all...] |
| PTXISelLowering.h | 42 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
44 virtual SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
46 virtual SDValue
47 LowerFormalArguments(SDValue Chain,
53 SmallVectorImpl<SDValue> &InVals) const;
55 virtual SDValue
56 LowerReturn(SDValue Chain,
60 const SmallVectorImpl<SDValue> &OutVals
[all...] |
| PTXISelDAGToDAG.cpp | 39 bool SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2);
40 bool SelectADDRri(SDValue &Addr, SDValue &Base, SDValue &Offset);
41 bool SelectADDRii(SDValue &Addr, SDValue &Base, SDValue &Offset);
42 bool SelectADDRlocal(SDValue &Addr, SDValue &Base, SDValue &Offset)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.h | 37 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
38 SDValue Chain,
39 SDValue Dst, SDValue Src,
40 SDValue Size, unsigned Align,
45 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
46 SDValue Chain,
47 SDValue Dst, SDValue Src,
48 SDValue Size, unsigned Align
[all...] |
| X86ISelLowering.h | 403 bool isZeroNode(SDValue Elt);
434 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
475 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
480 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
484 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
496 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
513 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
521 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSelectionDAGInfo.h | 29 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
30 SDValue Chain,
31 SDValue Dst, SDValue Src,
32 SDValue Size, unsigned Align,
|
| HexagonISelLowering.h | 69 IsEligibleForTailCallOptimization(SDValue Callee,
76 const SmallVectorImpl<SDValue> &OutVals,
83 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
[all...] |
| HexagonSelectionDAGInfo.cpp | 28 SDValue
30 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain,
31 SDValue Dst, SDValue Src, SDValue Size, unsigned Align,
45 return SDValue();
|
| HexagonISelDAGToDAG.cpp | 55 bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
56 bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
57 bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
58 bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 99 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
108 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
116 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
120 SmallVectorImpl<SDValue> &InVals) const;
123 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 148 SDValue Root;
251 const SDValue &getRoot() const { return Root; }
255 SDValue getEntryNode() const {
256 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
261 const SDValue &setRoot(SDValue N) {
327 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false);
328 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false);
329 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false);
330 SDValue getIntPtrConstant(uint64_t Val, bool isTarget = false)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 235 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
256 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
257 SDValue &Offset,
264 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
270 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
275 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 87 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
92 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
111 SDValue LowerCCCArguments(SDValue Chain,
116 SmallVectorImpl<SDValue> &InVals) const;
117 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
121 const SmallVectorImpl<SDValue> &OutVals
[all...] |
| XCoreISelDAGToDAG.cpp | 54 inline SDValue getI32Imm(unsigned Imm) {
70 bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
71 bool SelectADDRdpii(SDValue Addr, SDValue &Base, SDValue &Offset);
72 bool SelectADDRcpii(SDValue Addr, SDValue &Base, SDValue &Offset)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 48 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
49 SDValue Chain,
50 SDValue Dst, SDValue Src,
51 SDValue Size, unsigned Align,
58 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
59 SDValue Chain,
60 SDValue Op1, SDValue Op2,
61 SDValue Op3, unsigned Align
[all...] |
| ARMISelLowering.h | 249 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
254 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
269 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
270 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
304 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
305 SDValue &Offset,
313 SDValue &Base, SDValue &Offset,
317 virtual void computeMaskedBitsForTargetNode(const SDValue Op
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 47 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
52 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
70 virtual SDValue
71 LowerFormalArguments(SDValue Chain,
76 SmallVectorImpl<SDValue> &InVals) const;
78 virtual SDValue
79 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
82 const SmallVectorImpl<SDValue> &OutVals
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 64 SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
66 SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
68 SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
70 SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
72 SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
74 SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
75 SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
77 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
80 SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.h | 98 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
117 SmallVectorImpl<SDValue> &InVals) const;
120 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
[all...] |
| MBlazeISelDAGToDAG.cpp | 85 bool SelectAddrRegReg(SDValue N, SDValue &Base, SDValue &Index);
86 bool SelectAddrRegImm(SDValue N, SDValue &Disp, SDValue &Base);
89 inline SDValue getI32Imm(unsigned Imm) {
112 static bool isIntS32Immediate(SDValue Op, int32_t &Imm) {
121 SelectAddrRegReg(SDValue N, SDValue &Base, SDValue &Index)
[all...] |
