/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 374 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 379 SIGN_EXTEND_INREG, [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 72 case ISD::SIGN_EXTEND_INREG: 399 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 464 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 541 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 673 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), [all...] |
LegalizeVectorOps.cpp | 220 case ISD::SIGN_EXTEND_INREG:
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SelectionDAGDumper.cpp | 216 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
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LegalizeVectorTypes.cpp | 60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 251 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), CondVT, 466 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; [all...] |
SelectionDAG.cpp | [all...] |
LegalizeDAG.cpp | 737 case ISD::SIGN_EXTEND_INREG: { [all...] |
LegalizeTypes.h | 201 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op, [all...] |
DAGCombiner.cpp | 759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, [all...] |
TargetLowering.cpp | [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | 709 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 710 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 711 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); [all...] |
/external/llvm/lib/Target/PTX/ |
PTXISelLowering.cpp | 73 // sign_extend_inreg => sign_extend 75 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); [all...] |
/external/llvm/lib/Target/MBlaze/ |
MBlazeISelLowering.cpp | 163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 182 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 248 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 249 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelDAGToDAG.cpp | 819 if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) { [all...] |
HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | 126 setOperationAction(ISD::SIGN_EXTEND_INREG, VT.getSimpleVT(), Expand); [all...] |
/external/llvm/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 363 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); [all...] |