| /external/llvm/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 98 const uint16_t* SubReg =
103 BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg);
104 BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg);
114 const uint16_t* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg);
116 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
|
| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 196 unsigned SubReg = *SubRegs; ++SubRegs) {
197 MachineInstr *Def = PhysRegDef[SubReg];
202 LastDefReg = SubReg;
220 unsigned SubReg = *SubRegs; ++SubRegs)
221 PartDefRegs.insert(SubReg);
251 unsigned SubReg = *SubRegs; ++SubRegs) {
252 if (Processed.count(SubReg))
254 if (PartDefRegs.count(SubReg))
258 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
261 PhysRegDef[SubReg] = LastPartialDef
[all...] |
| RegisterScavenging.cpp | 41 unsigned SubReg = *SubRegs; ++SubRegs)
42 RegsAvailable.reset(SubReg);
199 unsigned SubReg = *SubRegs; ++SubRegs)
200 if (isUsed(SubReg)) {
|
| MachineInstrBundle.cpp | 173 unsigned SubReg = *SubRegs; ++SubRegs) {
174 if (LocalDefSet.insert(SubReg))
175 LocalDefs.push_back(SubReg);
|
| BranchFolding.cpp | 141 unsigned SubReg = *SubRegs; ++SubRegs)
142 ImpDefRegs.insert(SubReg);
[all...] |
| MachineInstr.cpp | 185 SubReg = 0;
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 61 /// SubReg - Subregister number, only valid for MO_Register. A value of 0
62 /// indicates the MO_Register has no subReg.
63 unsigned char SubReg;
244 return (unsigned)SubReg;
319 void setSubReg(unsigned subReg) {
321 SubReg = (unsigned char)subReg;
325 /// subregister Reg:SubReg. Take any existing SubReg index into account,
326 /// using TargetRegisterInfo to compose the subreg indices if necessary
[all...] |
| MachineInstrBuilder.h | 59 unsigned SubReg = 0) const {
69 SubReg,
|
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 605 CodeGenRegister::SubRegMap::const_iterator SubReg =
607 if (SubReg != SRM.end())
608 OS << getQualifiedName(SubReg->second->TheDef);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 107 /// true, then it's expected the pre-extension value is available as a subreg
180 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 332 0/*SubReg*/, IsDebug));
426 /// EmitSubregNode - Generate machine code for subreg nodes.
584 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
585 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
668 // Handle subreg insert/extract specially
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 514 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
516 O << ARMInstPrinter::getRegisterName(SubReg);
[all...] |
