1 /* 2 * Copyright (c) 2008, Google Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _MSM7200_USB_H_ 30 #define _MSM7200_USB_H_ 31 32 #define MSM_USB_BASE 0xA0800000 33 34 35 #define USB_ID (MSM_USB_BASE + 0x0000) 36 #define USB_HWGENERAL (MSM_USB_BASE + 0x0004) 37 #define USB_HWHOST (MSM_USB_BASE + 0x0008) 38 #define USB_HWDEVICE (MSM_USB_BASE + 0x000C) 39 #define USB_HWTXBUF (MSM_USB_BASE + 0x0010) 40 #define USB_HWRXBUF (MSM_USB_BASE + 0x0014) 41 #define USB_SBUSCFG (MSM_USB_BASE + 0x0090) 42 43 #define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */ 44 #define USB_HCIVERSION (MSM_USB_BASE + 0x0102) /* 16 bit */ 45 #define USB_HCSPARAMS (MSM_USB_BASE + 0x0104) 46 #define USB_HCCPARAMS (MSM_USB_BASE + 0x0108) 47 #define USB_DCIVERSION (MSM_USB_BASE + 0x0120) /* 16 bit */ 48 #define USB_USBCMD (MSM_USB_BASE + 0x0140) 49 #define USB_USBSTS (MSM_USB_BASE + 0x0144) 50 #define USB_USBINTR (MSM_USB_BASE + 0x0148) 51 #define USB_FRINDEX (MSM_USB_BASE + 0x014C) 52 #define USB_DEVICEADDR (MSM_USB_BASE + 0x0154) 53 #define USB_ENDPOINTLISTADDR (MSM_USB_BASE + 0x0158) 54 #define USB_BURSTSIZE (MSM_USB_BASE + 0x0160) 55 #define USB_TXFILLTUNING (MSM_USB_BASE + 0x0164) 56 #define USB_ULPI_VIEWPORT (MSM_USB_BASE + 0x0170) 57 #define USB_ENDPTNAK (MSM_USB_BASE + 0x0178) 58 #define USB_ENDPTNAKEN (MSM_USB_BASE + 0x017C) 59 #define USB_PORTSC (MSM_USB_BASE + 0x0184) 60 #define USB_OTGSC (MSM_USB_BASE + 0x01A4) 61 #define USB_USBMODE (MSM_USB_BASE + 0x01A8) 62 #define USB_ENDPTSETUPSTAT (MSM_USB_BASE + 0x01AC) 63 #define USB_ENDPTPRIME (MSM_USB_BASE + 0x01B0) 64 #define USB_ENDPTFLUSH (MSM_USB_BASE + 0x01B4) 65 #define USB_ENDPTSTAT (MSM_USB_BASE + 0x01B8) 66 #define USB_ENDPTCOMPLETE (MSM_USB_BASE + 0x01BC) 67 #define USB_ENDPTCTRL(n) (MSM_USB_BASE + 0x01C0 + (4 * (n))) 68 69 70 #define USBCMD_RESET 2 71 #define USBCMD_ATTACH 1 72 73 #define USBMODE_DEVICE 2 74 #define USBMODE_HOST 3 75 76 struct ept_queue_head 77 { 78 unsigned config; 79 unsigned current; /* read-only */ 80 81 unsigned next; 82 unsigned info; 83 unsigned page0; 84 unsigned page1; 85 unsigned page2; 86 unsigned page3; 87 unsigned page4; 88 unsigned reserved_0; 89 90 unsigned char setup_data[8]; 91 92 unsigned reserved_1; 93 unsigned reserved_2; 94 unsigned reserved_3; 95 unsigned reserved_4; 96 }; 97 98 #define CONFIG_MAX_PKT(n) ((n) << 16) 99 #define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */ 100 #define CONFIG_IOS (1 << 15) /* IRQ on setup */ 101 102 struct ept_queue_item 103 { 104 unsigned next; 105 unsigned info; 106 unsigned page0; 107 unsigned page1; 108 unsigned page2; 109 unsigned page3; 110 unsigned page4; 111 unsigned reserved; 112 }; 113 114 #define TERMINATE 1 115 116 #define INFO_BYTES(n) ((n) << 16) 117 #define INFO_IOC (1 << 15) 118 #define INFO_ACTIVE (1 << 7) 119 #define INFO_HALTED (1 << 6) 120 #define INFO_BUFFER_ERROR (1 << 5) 121 #define INFO_TX_ERROR (1 << 3) 122 123 124 #define STS_NAKI (1 << 16) /* */ 125 #define STS_SLI (1 << 8) /* R/WC - suspend state entered */ 126 #define STS_SRI (1 << 7) /* R/WC - SOF recv'd */ 127 #define STS_URI (1 << 6) /* R/WC - RESET recv'd - write to clear */ 128 #define STS_FRI (1 << 3) /* R/WC - Frame List Rollover */ 129 #define STS_PCI (1 << 2) /* R/WC - Port Change Detect */ 130 #define STS_UEI (1 << 1) /* R/WC - USB Error */ 131 #define STS_UI (1 << 0) /* R/WC - USB Transaction Complete */ 132 133 134 /* bits used in all the endpoint status registers */ 135 #define EPT_TX(n) (1 << ((n) + 16)) 136 #define EPT_RX(n) (1 << (n)) 137 138 139 #define CTRL_TXE (1 << 23) 140 #define CTRL_TXR (1 << 22) 141 #define CTRL_TXI (1 << 21) 142 #define CTRL_TXD (1 << 17) 143 #define CTRL_TXS (1 << 16) 144 #define CTRL_RXE (1 << 7) 145 #define CTRL_RXR (1 << 6) 146 #define CTRL_RXI (1 << 5) 147 #define CTRL_RXD (1 << 1) 148 #define CTRL_RXS (1 << 0) 149 150 #define CTRL_TXT_CTRL (0 << 18) 151 #define CTRL_TXT_ISOCH (1 << 18) 152 #define CTRL_TXT_BULK (2 << 18) 153 #define CTRL_TXT_INT (3 << 18) 154 155 #define CTRL_RXT_CTRL (0 << 2) 156 #define CTRL_RXT_ISOCH (1 << 2) 157 #define CTRL_RXT_BULK (2 << 2) 158 #define CTRL_RXT_INT (3 << 2) 159 160 #define ULPI_WAKEUP (1 << 31) 161 #define ULPI_RUN (1 << 30) 162 #define ULPI_WRITE (1 << 29) 163 #define ULPI_READ (0 << 29) 164 #define ULPI_STATE_NORMAL (1 << 27) 165 #define ULPI_ADDR(n) (((n) & 255) << 16) 166 #define ULPI_DATA(n) ((n) & 255) 167 #define ULPI_DATA_READ(n) (((n) >> 8) & 255) 168 169 #endif 170
