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Searched
refs:VirtReg
(Results
1 - 15
of
15
) sorted by null
/external/llvm/lib/CodeGen/
LiveIntervalUnion.cpp
30
void LiveIntervalUnion::unify(LiveInterval &
VirtReg
) {
31
if (
VirtReg
.empty())
36
LiveInterval::iterator RegPos =
VirtReg
.begin();
37
LiveInterval::iterator RegEnd =
VirtReg
.end();
41
SegPos.insert(RegPos->start, RegPos->end, &
VirtReg
);
51
SegPos.insert(RegEnd->start, RegEnd->end, &
VirtReg
);
53
SegPos.insert(RegPos->start, RegPos->end, &
VirtReg
);
57
void LiveIntervalUnion::extract(LiveInterval &
VirtReg
) {
58
if (
VirtReg
.empty())
63
LiveInterval::iterator RegPos =
VirtReg
.begin()
[
all
...]
RegAllocBase.h
109
LiveIntervalUnion::Query &query(LiveInterval &
VirtReg
, unsigned PhysReg) {
110
Queries[PhysReg].init(UserTag, &
VirtReg
, &PhysReg2LiveUnion[PhysReg]);
130
/// enqueue - Add
VirtReg
to the priority queue of unassigned registers.
140
virtual unsigned selectOrSplit(LiveInterval &
VirtReg
,
149
unsigned checkPhysRegInterference(LiveInterval&
VirtReg
, unsigned PhysReg);
151
/// assign - Assign
VirtReg
to PhysReg.
153
void assign(LiveInterval &
VirtReg
, unsigned PhysReg);
155
/// unassign - Undo a previous assignment of
VirtReg
to PhysReg.
158
void unassign(LiveInterval &
VirtReg
, unsigned PhysReg);
LiveIntervalUnion.h
90
void unify(LiveInterval &
VirtReg
);
93
void extract(LiveInterval &
VirtReg
);
110
LiveInterval *
VirtReg
;
111
LiveInterval::iterator VirtRegI; // current position in
VirtReg
120
Query(): LiveUnion(),
VirtReg
(), Tag(0), UserTag(0) {}
123
LiveUnion(LIU),
VirtReg
(VReg), CheckedFirstInterference(false),
129
VirtReg
= NULL;
140
if (UserTag == UTag &&
VirtReg
== VReg &&
147
VirtReg
= VReg;
152
LiveInterval &
virtReg
() const
[
all
...]
RegAllocBase.cpp
138
LiveInterval &
VirtReg
= *I->second;
140
PhysReg2LiveUnion[RegNum].unify(
VirtReg
);
142
enqueue(&
VirtReg
);
146
void RegAllocBase::assign(LiveInterval &
VirtReg
, unsigned PhysReg) {
147
DEBUG(dbgs() << "assigning " << PrintReg(
VirtReg
.reg, TRI)
149
assert(!VRM->hasPhys(
VirtReg
.reg) && "Duplicate
VirtReg
assignment");
150
VRM->assignVirt2Phys(
VirtReg
.reg, PhysReg);
152
PhysReg2LiveUnion[PhysReg].unify(
VirtReg
);
156
void RegAllocBase::unassign(LiveInterval &
VirtReg
, unsigned PhysReg)
[
all
...]
RegAllocBasic.cpp
109
virtual unsigned selectOrSplit(LiveInterval &
VirtReg
,
118
bool spillInterferences(LiveInterval &
VirtReg
, unsigned PhysReg,
121
void spillReg(LiveInterval &
VirtReg
, unsigned PhysReg,
173
void RABasic::spillReg(LiveInterval&
VirtReg
, unsigned PhysReg,
175
LiveIntervalUnion::Query &Q = query(
VirtReg
, PhysReg);
199
// that interfere with
VirtReg
. The newly spilled or split live intervals are
201
bool RABasic::spillInterferences(LiveInterval &
VirtReg
, unsigned PhysReg,
208
LiveIntervalUnion::Query &QAlias = query(
VirtReg
, *asI);
215
" interferences with " <<
VirtReg
<< "\n");
220
spillReg(
VirtReg
, *AliasI, SplitVRegs)
[
all
...]
VirtRegMap.h
92
bool hasPhys(unsigned
virtReg
) const {
93
return getPhys(
virtReg
) != NO_PHYS_REG;
98
unsigned getPhys(unsigned
virtReg
) const {
99
assert(TargetRegisterInfo::isVirtualRegister(
virtReg
));
100
return Virt2PhysMap[
virtReg
];
105
void assignVirt2Phys(unsigned
virtReg
, unsigned physReg) {
106
assert(TargetRegisterInfo::isVirtualRegister(
virtReg
) &&
108
assert(Virt2PhysMap[
virtReg
] == NO_PHYS_REG &&
111
Virt2PhysMap[
virtReg
] = physReg;
116
void clearVirt(unsigned
virtReg
) {
[
all
...]
AllocationOrder.h
34
/// AllocationOrder - Create a new AllocationOrder for
VirtReg
.
35
/// @param
VirtReg
Virtual register to allocate for.
38
AllocationOrder(unsigned
VirtReg
,
AllocationOrder.cpp
25
AllocationOrder::AllocationOrder(unsigned
VirtReg
,
29
const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(
VirtReg
);
31
VRM.getRegInfo().getRegAllocationHint(
VirtReg
);
RegAllocFast.cpp
72
unsigned
VirtReg
; // Virtual register number.
78
: LastUse(0),
VirtReg
(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
81
return TargetRegisterInfo::virtReg2Index(
VirtReg
);
113
// PhysRegState - One of the RegState enums, or a
virtreg
.
150
int getStackSpaceFor(unsigned
VirtReg
, const TargetRegisterClass *RC);
155
void killVirtReg(unsigned
VirtReg
);
157
void spillVirtReg(MachineBasicBlock::iterator MI, unsigned
VirtReg
);
163
LiveRegMap::iterator findLiveVirtReg(unsigned
VirtReg
) {
164
return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(
VirtReg
));
166
LiveRegMap::const_iterator findLiveVirtReg(unsigned
VirtReg
) const
[
all
...]
RegAllocGreedy.cpp
138
LiveRangeStage getStage(const LiveInterval &
VirtReg
) const {
139
return ExtraRegInfo[
VirtReg
.reg].Stage;
142
void setStage(const LiveInterval &
VirtReg
, LiveRangeStage Stage) {
144
ExtraRegInfo[
VirtReg
.reg].Stage = Stage;
171
// Register mask interference. The current
VirtReg
is checked for register
362
bool RAGreedy::LRE_CanEraseVirtReg(unsigned
VirtReg
) {
363
if (unsigned PhysReg = VRM->getPhys(
VirtReg
)) {
364
unassign(LIS->getInterval(
VirtReg
), PhysReg);
367
// Unassigned
virtreg
is probably in the priority queue.
372
void RAGreedy::LRE_WillShrinkVirtReg(unsigned
VirtReg
) {
[
all
...]
LiveDebugVariables.cpp
303
/// lookupVirtReg - Find the EC leader for
VirtReg
or null.
304
UserValue *lookupVirtReg(unsigned
VirtReg
);
335
void mapVirtReg(unsigned
VirtReg
, UserValue *EC);
429
void LDVImpl::mapVirtReg(unsigned
VirtReg
, UserValue *EC) {
430
assert(TargetRegisterInfo::isVirtualRegister(
VirtReg
) && "Only map VirtRegs");
431
UserValue *&Leader = virtRegToEqClass[
VirtReg
];
435
UserValue *LDVImpl::lookupVirtReg(unsigned
VirtReg
) {
436
if (UserValue *UV = virtRegToEqClass.lookup(
VirtReg
))
885
unsigned
VirtReg
= Loc.getReg();
886
if (VRM.isAssignedReg(
VirtReg
) &
[
all
...]
VirtRegMap.cpp
78
unsigned VirtRegMap::getRegAllocPref(unsigned
virtReg
) {
79
std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(
virtReg
);
89
int VirtRegMap::assignVirt2StackSlot(unsigned
virtReg
) {
90
assert(TargetRegisterInfo::isVirtualRegister(
virtReg
));
91
assert(Virt2StackSlotMap[
virtReg
] == NO_STACK_SLOT &&
93
const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(
virtReg
);
94
return Virt2StackSlotMap[
virtReg
] = createSpillSlot(RC);
97
void VirtRegMap::assignVirt2StackSlot(unsigned
virtReg
, int SS) {
98
assert(TargetRegisterInfo::isVirtualRegister(
virtReg
));
99
assert(Virt2StackSlotMap[
virtReg
] == NO_STACK_SLOT &
[
all
...]
InlineSpiller.cpp
835
bool InlineSpiller::reMaterializeFor(LiveInterval &
VirtReg
,
838
VNInfo *ParentVNI =
VirtReg
.getVNInfoAt(UseIdx.getBaseIndex());
844
if (MO.isReg() && MO.isUse() && MO.getReg() ==
VirtReg
.reg)
860
markValueUsed(&
VirtReg
, ParentVNI);
865
// If the instruction also writes
VirtReg
.reg, it had better not require the
869
MIBundleOperands(MI).analyzeVirtReg(
VirtReg
.reg, &Ops);
871
markValueUsed(&
VirtReg
, ParentVNI);
[
all
...]
PrologEpilogInserter.cpp
821
unsigned
VirtReg
= 0;
841
if (Reg !=
VirtReg
) {
847
VirtReg
= Reg;
/external/llvm/include/llvm/CodeGen/
ScheduleDAGInstrs.h
103
unsigned
VirtReg
;
106
VReg2SUnit(unsigned reg, SUnit *su):
VirtReg
(reg), SU(su) {}
109
return TargetRegisterInfo::virtReg2Index(
VirtReg
);
325
VReg2SUnitMap::iterator findVRegDef(unsigned
VirtReg
) {
326
return VRegDefs.find(TargetRegisterInfo::virtReg2Index(
VirtReg
));
Completed in 219 milliseconds