| /external/llvm/test/CodeGen/MSP430/ |
| AddrMode-mov-rx.ll | 2 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
5 define i16 @am1(i16* %a) nounwind {
6 %1 = load i16* %a
7 ret i16 %1
12 @foo = external global i16
14 define i16 @am2() nounwind {
15 %1 = load i16* @foo
16 ret i16 %1
23 define i8 @am3(i16 %n) nounwind
[all...] |
| AddrMode-mov-xr.ll | 2 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
5 define void @am1(i16* %a, i16 %b) nounwind {
6 store i16 %b, i16* %a
12 @foo = external global i16
14 define void @am2(i16 %a) nounwind {
15 store i16 %a, i16* @foo
23 define void @am3(i16 %i, i8 %a) nounwind
[all...] |
| AddrMode-bis-xr.ll | 2 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:16"
5 define void @am1(i16* %a, i16 %x) nounwind {
6 %1 = load i16* %a
7 %2 = or i16 %x, %1
8 store i16 %2, i16* %a
14 @foo = external global i16
16 define void @am2(i16 %x) nounwind {
17 %1 = load i16* @fo
[all...] |
| AddrMode-bis-rx.ll | 2 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
5 define i16 @am1(i16 %x, i16* %a) nounwind {
6 %1 = load i16* %a
7 %2 = or i16 %1,%x
8 ret i16 %2
13 @foo = external global i16
15 define i16 @am2(i16 %x) nounwind
[all...] |
| 2009-05-19-DoubleSplit.ll | 3 define i16 @test(double %d) nounwind {
6 %call = tail call i16 @funct(double %add) nounwind
7 ret i16 %call
10 declare i16 @funct(double)
|
| /external/llvm/test/CodeGen/ARM/ |
| 2009-08-31-TwoRegShuffle.ll | 3 define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
6 %tmp1 = load <4 x i16>* %B
7 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>
8 ret <4 x i16> %tmp2
|
| 2011-09-09-OddVectorDivision.ll | 3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32"
6 @x1 = common global <3 x i16> zeroinitializer
7 @y1 = common global <3 x i16> zeroinitializer
8 @z1 = common global <3 x i16> zeroinitializer
9 @x2 = common global <4 x i16> zeroinitializer
10 @y2 = common global <4 x i16> zeroinitializer
11 @z2 = common global <4 x i16> zeroinitializer
14 %1 = load <3 x i16>* @x1
15 %2 = load <3 x i16>* @y1
16 %3 = sdiv <3 x i16> %1, %
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| vec_shuffle-34.ll | 3 define <8 x i16> @shuf2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
5 %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
6 ret <8 x i16> %tmp8
|
| 2007-10-29-ExtendSetCC.ll | 3 define signext i16 @t() {
5 %tmp180 = load i16* null, align 2 ; <i16> [#uses=3]
6 %tmp180181 = sext i16 %tmp180 to i32 ; <i32> [#uses=1]
7 %tmp185 = icmp slt i16 %tmp180, 0 ; <i1> [#uses=1]
11 %tmp195196 = trunc i16 %tmp180 to i8 ; <i8> [#uses=0]
12 ret i16 0
16 ret i16 0
|
| 2011-11-30-or.ll | 3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
13 %c.lobit.i.i.i = ashr <8 x i16> <i16 17, i16 5, i16 1, i16 15, i16 19, i16 15, i16 4, i16 1> , <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15
[all...] |
| promote-i16.ll | 3 define signext i16 @foo(i16 signext %x) nounwind {
9 %0 = xor i16 %x, 21998
10 ret i16 %0
13 define signext i16 @bar(i16 signext %x) nounwind {
19 %0 = xor i16 %x, 54766
20 ret i16 %0
|
| vec-trunc-store.ll | 5 %cti69 = trunc <8 x i32> %t to <8 x i16> ; <<8 x i16>> [#uses=1]
6 store <8 x i16> %cti69, <8 x i16>* undef
12 %cti44 = trunc <4 x i32> %t to <4 x i16> ; <<4 x i16>> [#uses=1]
13 store <4 x i16> %cti44, <4 x i16>* undef
|
| widen_arith-4.ll | 7 define void @update(<5 x i16>* %dst, <5 x i16>* %src, i32 %n) nounwind {
9 %dst.addr = alloca <5 x i16>* ; <<5 x i16>**> [#uses=2]
10 %src.addr = alloca <5 x i16>* ; <<5 x i16>**> [#uses=2]
12 %v = alloca <5 x i16>, align 16 ; <<5 x i16>*> [#uses=1]
14 store <5 x i16>* %dst, <5 x i16>** %dst.add
[all...] |
| vec_shuffle-36.ll | 3 define <8 x i16> @shuf6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
8 %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 3, i32 2, i32 0, i32 2, i32 1, i32 5, i32 6 , i32 undef >
9 ret <8 x i16> %tmp9
12 define <8 x i16> @shuf7(<8 x i16> %t0) {
14 %tmp10 = shufflevector <8 x i16> %t0, <8 x i16> undef, <8 x i32> < i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 undef, i32 undef
[all...] |
| x86-shifts.ll | 67 define <8 x i16> @shl8(<8 x i16> %A) nounwind {
73 %B = shl <8 x i16> %A, < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2
[all...] |
| vec_shuffle.ll | 30 %tmp.upgrd.1 = bitcast <2 x i64> %tmp to <8 x i16> ; <<8 x i16>> [#uses=8]
31 %tmp.upgrd.2 = extractelement <8 x i16> %tmp.upgrd.1, i32 0 ; <i16> [#uses=1]
32 %tmp1 = extractelement <8 x i16> %tmp.upgrd.1, i32 1 ; <i16> [#uses=1]
33 %tmp2 = extractelement <8 x i16> %tmp.upgrd.1, i32 2 ; <i16> [#uses=1]
34 %tmp3 = extractelement <8 x i16> %tmp.upgrd.1, i32 3 ; <i16> [#uses=1
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| 2007-06-28-BCCISelBug.ll | 3 %struct.XATest = type { float, i16, i8, i8 }
5 %struct.XBlendMode = type { i16, i16, i16, i16, %struct.GIC4, i16, i16, i8, i8, i8, i8 }
8 %struct.XCBuffer = type { i16, i16, [8 x i16] }
[all...] |
| 2008-07-15-SignExtendInreg.ll | 2 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
5 define signext i16 @t(i16* %dct) nounwind {
7 load i16* null, align 2 ; <i16>:0 [#uses=2]
8 lshr i16 %0, 11 ; <i16>:1 [#uses=0]
9 trunc i16 %0 to i8 ; <i8>:2 [#uses=1]
10 sext i8 %2 to i16 ; <i16>:3 [#uses=1
[all...] |
| fp_to_uint.ll | 3 define i16 @foo(float %a) {
5 %tmp.1 = fptoui float %a to i16 ; <i16> [#uses=1]
6 ret i16 %tmp.1
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-ldrh.ll | 3 define i16 @f1(i16* %v) {
7 %tmp = load i16* %v
8 ret i16 %tmp
11 define i16 @f2(i16* %v) {
15 %tmp2 = getelementptr i16* %v, i16 1023
16 %tmp = load i16* %tmp2
17 ret i16 %tm
[all...] |
| /external/llvm/test/Feature/ |
| casttest.ll | 5 define i16 @FunFunc(i64 %x, i8 %z) {
7 %cast110 = sext i8 %z to i16 ; <i16> [#uses=1]
8 %cast10 = trunc i64 %x to i16 ; <i16> [#uses=1]
9 %reg109 = add i16 %cast110, %cast10 ; <i16> [#uses=1]
10 ret i16 %reg109
|
| newcasts.ll | 5 define void @"NewCasts" (i16 %x) {
6 %a = zext i16 %x to i32
7 %b = sext i16 %x to i32
8 %c = trunc i16 %x to i8
9 %d = uitofp i16 %x to float
10 %e = sitofp i16 %x to double
11 %f = fptoui float %d to i16
12 %g = fptosi double %e to i16
16 %l = inttoptr i16 %x to i32*
27 define i16 @"ZExtConst" ()
[all...] |
| /external/llvm/test/Analysis/ScalarEvolution/ |
| 2008-08-04-LongAddRec.ll | 10 add i16 %x17.0, 1 ; <i16>:0 [#uses=2]
11 add i16 %0, %x16.0 ; <i16>:1 [#uses=2]
12 add i16 %1, %x15.0 ; <i16>:2 [#uses=2]
13 add i16 %2, %x14.0 ; <i16>:3 [#uses=2]
14 add i16 %3, %x13.0 ; <i16>:4 [#uses=2
[all...] |
| /external/clang/test/CodeGen/ |
| pascal-wchar-string.c | 32 // CHECK: [i16 3, i16 98, i16 97, i16 114, i16 0]
33 // CHECK: [i16 4, i16 103, i16 111, i16 114, i16 102, i16 0
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_TransformResidual4x4_s.S | 18 VMOV.I16 d4,#0
19 VADD.I16 d5,d0,d2
20 VSUB.I16 d6,d0,d2
23 VSUB.I16 d7,d7,d3
24 VADD.I16 d8,d1,d8
25 VADD.I16 d0,d5,d8
26 VADD.I16 d1,d6,d7
27 VSUB.I16 d2,d6,d7
28 VSUB.I16 d3,d5,d8
32 VADD.I16 d5,d0,d
[all...] |
