| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 24 FIRST_NUMBER = ISD::BUILTIN_OP_END,
74 const SmallVectorImpl<ISD::InputArg> &Ins,
81 const SmallVectorImpl<ISD::OutputArg> &Outs,
83 const SmallVectorImpl<ISD::InputArg> &Ins,
90 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| SparcISelDAGToDAG.cpp | 80 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
81 Addr.getOpcode() == ISD::TargetGlobalAddress)
84 if (Addr.getOpcode() == ISD::ADD) {
115 if (Addr.getOpcode() == ISD::FrameIndex) return false;
116 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
117 Addr.getOpcode() == ISD::TargetGlobalAddress)
120 if (Addr.getOpcode() == ISD::ADD) {
147 case ISD::SDIV:
148 case ISD::UDIV: {
155 if (N->getOpcode() == ISD::SDIV)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 86 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
87 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
88 setOperationAction(ISD::ADDC, MVT::i32, Expand);
89 setOperationAction(ISD::ADDE, MVT::i32, Expand);
90 setOperationAction(ISD::SUBC, MVT::i32, Expand);
91 setOperationAction(ISD::SUBE, MVT::i32, Expand);
94 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
97 setOperationAction(ISD::ADD, MVT::i64, Custom);
98 setOperationAction(ISD::SUB, MVT::i64, Custom);
99 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom)
[all...] |
| XCoreISelLowering.h | 31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
114 const SmallVectorImpl<ISD::InputArg> &Ins,
120 const SmallVectorImpl<ISD::OutputArg> &Outs,
122 const SmallVectorImpl<ISD::InputArg> &Ins,
127 const SmallVectorImpl<ISD::InputArg> &Ins,
172 const SmallVectorImpl<ISD::InputArg> &Ins,
179 const SmallVectorImpl<ISD::OutputArg> &Outs,
181 const SmallVectorImpl<ISD::InputArg> &Ins,
188 const SmallVectorImpl<ISD::OutputArg> &Outs,
195 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
75 SmallVectorImpl<ISD::OutputArg> &Outs,
77 const SmallVectorImpl<ISD::InputArg> &Ins,
92 const SmallVectorImpl<ISD::InputArg> &Ins,
100 const SmallVectorImpl<ISD::OutputArg> &Outs,
102 const SmallVectorImpl<ISD::InputArg> &Ins,
108 const SmallVectorImpl<ISD::InputArg> &Ins,
122 const SmallVectorImpl<ISD::OutputArg> &Outs,
137 ISD::MemIndexedMode &AM,
|
| HexagonCallingConvLower.cpp | 44 ISD::ArgFlagsTy ArgFlags) {
66 /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
69 Hexagon_CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg>
85 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
94 /// AnalyzeReturn - Analyze the returned values of an ISD::RET node,
97 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
121 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
131 /// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info
134 Hexagon_CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg>
151 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags
[all...] |
| HexagonISelDAGToDAG.cpp | 303 ISD::isNormalLoad(LD)) {
495 bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
523 LD->getExtensionType() == ISD::ZEXTLOAD) {
527 LD->getExtensionType() == ISD::SEXTLOAD) {
581 ISD::MemIndexedMode AM = LD->getAddressingMode();
584 if (AM != ISD::UNINDEXED) {
678 if (Base.getOpcode() == ISD::TargetGlobalAddress) {
720 ISD::MemIndexedMode AM = ST->getAddressingMode();
723 if (AM != ISD::UNINDEXED) {
752 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND)
[all...] |
| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 45 ISD::ArgFlagsTy ArgFlags) {
69 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
75 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
88 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
93 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
102 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
107 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
120 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
125 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
139 SmallVectorImpl<ISD::ArgFlagsTy> &Flags
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 95 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
96 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
99 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
106 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
107 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
108 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Custom);
112 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom)
[all...] |
| ARMSelectionDAGInfo.cpp | 67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
106 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
115 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
129 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
136 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
171 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
173 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src)
[all...] |
| ARMISelLowering.h | 34 FIRST_NUMBER = ISD::BUILTIN_OP_END,
198 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
259 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
306 ISD::MemIndexedMode &AM,
314 ISD::MemIndexedMode &AM,
403 ISD::ArgFlagsTy Flags) const;
413 ISD::ArgFlagsTy Flags) const;
446 const SmallVectorImpl<ISD::InputArg> &Ins,
453 const SmallVectorImpl<ISD::InputArg> &Ins,
468 const SmallVectorImpl<ISD::OutputArg> &Outs
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
96 /// (ISD::AssertSext).
100 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo)
[all...] |
| LegalizeTypesGeneric.cpp | 54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
55 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
61 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
62 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
74 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
75 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
82 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
84 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp
[all...] |
| FastISel.cpp | 170 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
183 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
202 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
280 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
285 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE,
337 /// which has an opcode which directly corresponds to the given ISD opcode.
353 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
354 ISDOpcode == ISD::XOR))
391 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXSelectionDAGInfo.cpp | 70 DAG.getNode(ISD::ADD, dl, PointerType, Src,
77 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
82 DAG.getNode(ISD::ADD, dl, PointerType, Dst,
88 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
109 DAG.getNode(ISD::ADD, dl, PointerType, Src,
118 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
132 DAG.getNode(ISD::ADD, dl, PointerType, Dst,
139 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
|
| PTXISelLowering.cpp | 61 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
62 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
63 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
67 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
75 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
79 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
83 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
84 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
85 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
91 setOperationAction(ISD::ConstantFP, MVT::f32, Legal)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 102 if (Opc != ISD::Constant)
122 if (N.getOpcode() == ISD::FrameIndex) return false;
123 if (N.getOpcode() == ISD::TargetExternalSymbol ||
124 N.getOpcode() == ISD::TargetGlobalAddress)
128 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
132 if (N.getOperand(0).getOpcode() == ISD::TargetJumpTable ||
133 N.getOperand(1).getOpcode() == ISD::TargetJumpTable)
153 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR)
[all...] |
| MBlazeISelLowering.h | 63 // Start the numbering from where ISD NodeType finishes.
64 FIRST_NUMBER = ISD::BUILTIN_OP_END,
104 /// getSetCCResultType - get the ISD::SETCC result ValueType
115 const SmallVectorImpl<ISD::InputArg> &Ins,
130 const SmallVectorImpl<ISD::InputArg> &Ins,
138 const SmallVectorImpl<ISD::OutputArg> &Outs,
140 const SmallVectorImpl<ISD::InputArg> &Ins,
147 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
178 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
250 /// getSetCCResultType - Return the ISD::SETCC ValueType
258 ISD::MemIndexedMode &AM,
377 const SmallVectorImpl<ISD::InputArg> &Ins,
420 const SmallVectorImpl<ISD::InputArg> &Ins,
431 const SmallVectorImpl<ISD::InputArg> &Ins,
437 const SmallVectorImpl<ISD::InputArg> &Ins,
444 const SmallVectorImpl<ISD::OutputArg> &Outs,
446 const SmallVectorImpl<ISD::InputArg> &Ins
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
105 /// getSetCCResultType - get the ISD::SETCC result ValueType
118 const SmallVectorImpl<ISD::InputArg> &Ins,
142 const SmallVectorImpl<ISD::InputArg> &Ins,
150 const SmallVectorImpl<ISD::OutputArg> &Outs,
152 const SmallVectorImpl<ISD::InputArg> &Ins,
159 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| MipsISelDAGToDAG.cpp | 286 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
287 Addr.getOpcode() == ISD::TargetGlobalAddress))
309 if (Addr.getOpcode() == ISD::ADD) {
386 case ISD::SUBE:
387 case ISD::ADDE: {
390 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
391 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
395 if (Opcode == ISD::ADDE)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 136 ISD::ArgFlagsTy ArgFlags, CCState &State);
143 ISD::ArgFlagsTy &ArgFlags, CCState &State);
196 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
201 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
207 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
212 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
218 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
223 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
305 int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 121 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
136 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
309 \arg Op The ISD instruction operand
323 case ISD::Constant:
328 case ISD::ConstantPool:
329 case ISD::GlobalAddress:
333 case ISD::TargetConstant:
334 case ISD::TargetGlobalAddress:
335 case ISD::TargetJumpTable:
346 case ISD::TargetConstantPool
[all...] |
| SPUISelLowering.h | 26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
109 /// getSetCCResultType - Return the ValueType for ISD::SETCC
157 const SmallVectorImpl<ISD::InputArg> &Ins,
165 const SmallVectorImpl<ISD::OutputArg> &Outs,
167 const SmallVectorImpl<ISD::InputArg> &Ins,
174 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 189 case ISD::Constant: {
200 case ISD::FrameIndex:
209 case ISD::ADD: {
223 case ISD::OR:
303 ISD::MemIndexedMode AM = LD->getAddressingMode();
304 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
356 if (N1.getOpcode() == ISD::LOAD &&
403 case ISD::FrameIndex: {
413 case ISD::LOAD
[all...] |
