| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | 523 if (N->getOperand(i).getValueType() == MVT::Other)
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| SelectionDAG.cpp | 65 case MVT::f16: return &APFloat::IEEEhalf;
66 case MVT::f32: return &APFloat::IEEEsingle;
67 case MVT::f64: return &APFloat::IEEEdouble;
68 case MVT::f80: return &APFloat::x87DoubleExtended;
69 case MVT::f128: return &APFloat::IEEEquad;
70 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
93 if (VT == MVT::ppcf128 ||
507 if (N->getValueType(0) == MVT::Glue)
519 if (N->getValueType(i) == MVT::Glue)
671 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Glue &
[all...] |
| InstrEmitter.cpp | 44 while (N && Node->getValueType(N - 1) == MVT::Glue)
46 if (N && Node->getValueType(N - 1) == MVT::Other)
57 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
59 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
111 if (VT == MVT::Other || VT == MVT::Glue)
278 assert(Op.getValueType() != MVT::Other &&
279 Op.getValueType() != MVT::Glue &&
394 assert(Op.getValueType() != MVT::Other &&
395 Op.getValueType() != MVT::Glue &
[all...] |
| SelectionDAGPrinter.cpp | 95 if (VT == MVT::Glue)
97 else if (VT == MVT::Other)
|
| ScheduleDAGSDNodes.cpp | 142 if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return;
148 VTs.push_back(MVT::Glue);
176 /// offsets are not far apart (target specific), it add MVT::Glue inputs and
182 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
238 // Cluster loads by adding MVT::Glue outputs and inputs. This also
322 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
332 while (N->getValueType(N->getNumValues()-1) == MVT::Glue) {
433 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
434 bool isChain = OpVT == MVT::Other;
|
| ScheduleDAGFast.cpp | 219 if (VT == MVT::Glue)
221 else if (VT == MVT::Other)
227 if (VT == MVT::Glue)
483 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 105 addLoc(CCValAssign::getReg(0, MVT::i32, Reg, MVT::i32,
111 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
|
| HexagonISelLowering.h | 132 return MVT::i1;
|
| HexagonInstrInfo.h | 108 unsigned createVR(MachineFunction* MF, MVT VT) const;
|
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 241 MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
242 ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
374 Reg = getX86SubSuperRegister(Reg, MVT::i8);
377 Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
380 Reg = getX86SubSuperRegister(Reg, MVT::i16);
383 Reg = getX86SubSuperRegister(Reg, MVT::i32);
386 Reg = getX86SubSuperRegister(Reg, MVT::i64);
|
| X86ISelLowering.h | 425 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
609 return !X86ScalarSSEf64 || VT == MVT::f80;
619 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
620 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
632 return isTargetFTOL() && VT == MVT::i64;
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenDAGPatterns.cpp | 32 static inline bool isInteger(MVT::SimpleValueType VT) {
35 static inline bool isFloatingPoint(MVT::SimpleValueType VT) {
38 static inline bool isVector(MVT::SimpleValueType VT) {
41 static inline bool isScalar(MVT::SimpleValueType VT) {
45 EEVT::TypeSet::TypeSet(MVT::SimpleValueType VT, TreePattern &TP) {
46 if (VT == MVT::iAny)
48 else if (VT == MVT::fAny)
50 else if (VT == MVT::vAny)
53 assert((VT < MVT::LAST_VALUETYPE || VT == MVT::iPTR |
[all...] |
| DAGISelMatcherGen.cpp | 23 /// have different associated types, return MVT::Other.
24 static MVT::SimpleValueType getRegisterValueType(Record *R,
27 MVT::SimpleValueType VT = MVT::Other;
604 AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
612 AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
768 SmallVector<MVT::SimpleValueType, 4> ResultVTs;
781 if (II.HasOneImplicitDefWithKnownVT(CGT) != MVT::Other)
[all...] |
| FastISelEmitter.cpp | 170 MVT::SimpleValueType VT,
358 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
359 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
487 MVT::SimpleValueType RetVT = MVT::isVoid;
489 MVT::SimpleValueType VT = RetVT;
595 MVT::SimpleValueType VT = TI->first;
600 MVT::SimpleValueType RetVT = RI->first;
668 OS << "(MVT RetVT";
675 MVT::SimpleValueType RetVT = RI->first
[all...] |
| CodeGenRegisters.h | 195 std::vector<MVT::SimpleValueType> VTs;
210 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
213 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
|
| DAGISelMatcherOpt.cpp | 132 const SmallVectorImpl<MVT::SimpleValueType> &VTs = EN->getVTList();
426 CTM->getType() == MVT::iPTR ||
461 SmallVector<std::pair<MVT::SimpleValueType, Matcher*>, 8> Cases;
467 MVT::SimpleValueType CTMTy = CTM->getType();
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 112 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 76 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 94 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 39 typedef const MVT::SimpleValueType* vt_iterator;
104 for(int i = 0; VTs[i] != MVT::Other; ++i)
118 while (*I != MVT::Other) ++I;
302 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
|
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 262 assert((!N.getNode() || N.getValueType() == MVT::Other) &&
403 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
412 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
420 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
426 SDVTList VTs = getVTList(VT, MVT::Other);
436 SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);
479 SDVTList VTs = getVTList(MVT::Other, MVT::Glue)
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 319 SDValue predReg = DAG->getRegister(PTX::NoRegister, MVT::i1);
320 SDValue predOp = DAG->getTargetConstant(PTXPredicate::None, MVT::i32);
328 SDValue predReg = DAG->getRegister(PTX::NoRegister, MVT::i1);
329 SDValue predOp = DAG->getTargetConstant(PTXPredicate::None, MVT::i32);
|
| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 61 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 84 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
|
