1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Hexagon implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef HexagonINSTRUCTIONINFO_H 15 #define HexagonINSTRUCTIONINFO_H 16 17 #include "HexagonRegisterInfo.h" 18 #include "MCTargetDesc/HexagonBaseInfo.h" 19 #include "llvm/Target/TargetInstrInfo.h" 20 #include "llvm/Target/TargetFrameLowering.h" 21 22 23 #define GET_INSTRINFO_HEADER 24 #include "HexagonGenInstrInfo.inc" 25 26 namespace llvm { 27 28 class HexagonInstrInfo : public HexagonGenInstrInfo { 29 const HexagonRegisterInfo RI; 30 const HexagonSubtarget& Subtarget; 31 public: 32 explicit HexagonInstrInfo(HexagonSubtarget &ST); 33 34 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 35 /// such, whenever a client has an instance of instruction info, it should 36 /// always be able to get register info as well (through this method). 37 /// 38 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; } 39 40 /// isLoadFromStackSlot - If the specified machine instruction is a direct 41 /// load from a stack slot, return the virtual or physical register number of 42 /// the destination along with the FrameIndex of the loaded stack slot. If 43 /// not, return 0. This predicate must return 0 if the instruction has 44 /// any side effects other than loading from the stack slot. 45 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 46 int &FrameIndex) const; 47 48 /// isStoreToStackSlot - If the specified machine instruction is a direct 49 /// store to a stack slot, return the virtual or physical register number of 50 /// the source reg along with the FrameIndex of the loaded stack slot. If 51 /// not, return 0. This predicate must return 0 if the instruction has 52 /// any side effects other than storing to the stack slot. 53 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 54 int &FrameIndex) const; 55 56 57 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 58 MachineBasicBlock *&FBB, 59 SmallVectorImpl<MachineOperand> &Cond, 60 bool AllowModify) const; 61 62 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 63 64 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 65 MachineBasicBlock *FBB, 66 const SmallVectorImpl<MachineOperand> &Cond, 67 DebugLoc DL) const; 68 69 virtual void copyPhysReg(MachineBasicBlock &MBB, 70 MachineBasicBlock::iterator I, DebugLoc DL, 71 unsigned DestReg, unsigned SrcReg, 72 bool KillSrc) const; 73 74 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 75 MachineBasicBlock::iterator MBBI, 76 unsigned SrcReg, bool isKill, int FrameIndex, 77 const TargetRegisterClass *RC, 78 const TargetRegisterInfo *TRI) const; 79 80 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 81 SmallVectorImpl<MachineOperand> &Addr, 82 const TargetRegisterClass *RC, 83 SmallVectorImpl<MachineInstr*> &NewMIs) const; 84 85 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 86 MachineBasicBlock::iterator MBBI, 87 unsigned DestReg, int FrameIndex, 88 const TargetRegisterClass *RC, 89 const TargetRegisterInfo *TRI) const; 90 91 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 92 SmallVectorImpl<MachineOperand> &Addr, 93 const TargetRegisterClass *RC, 94 SmallVectorImpl<MachineInstr*> &NewMIs) const; 95 96 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 97 MachineInstr* MI, 98 const SmallVectorImpl<unsigned> &Ops, 99 int FrameIndex) const; 100 101 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 102 MachineInstr* MI, 103 const SmallVectorImpl<unsigned> &Ops, 104 MachineInstr* LoadMI) const { 105 return 0; 106 } 107 108 unsigned createVR(MachineFunction* MF, MVT VT) const; 109 110 virtual bool isPredicable(MachineInstr *MI) const; 111 virtual bool 112 PredicateInstruction(MachineInstr *MI, 113 const SmallVectorImpl<MachineOperand> &Cond) const; 114 115 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 116 unsigned ExtraPredCycles, 117 const BranchProbability &Probability) const; 118 119 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 120 unsigned NumTCycles, unsigned ExtraTCycles, 121 MachineBasicBlock &FMBB, 122 unsigned NumFCycles, unsigned ExtraFCycles, 123 const BranchProbability &Probability) const; 124 125 virtual bool isPredicated(const MachineInstr *MI) const; 126 virtual bool DefinesPredicate(MachineInstr *MI, 127 std::vector<MachineOperand> &Pred) const; 128 virtual bool 129 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 130 const SmallVectorImpl<MachineOperand> &Pred2) const; 131 132 virtual bool 133 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 134 135 virtual bool 136 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles, 137 const BranchProbability &Probability) const; 138 139 virtual DFAPacketizer* 140 CreateTargetScheduleState(const TargetMachine *TM, 141 const ScheduleDAG *DAG) const; 142 143 virtual bool isSchedulingBoundary(const MachineInstr *MI, 144 const MachineBasicBlock *MBB, 145 const MachineFunction &MF) const; 146 bool isValidOffset(const int Opcode, const int Offset) const; 147 bool isValidAutoIncImm(const EVT VT, const int Offset) const; 148 bool isMemOp(const MachineInstr *MI) const; 149 bool isSpillPredRegOp(const MachineInstr *MI) const; 150 bool isU6_3Immediate(const int value) const; 151 bool isU6_2Immediate(const int value) const; 152 bool isU6_1Immediate(const int value) const; 153 bool isU6_0Immediate(const int value) const; 154 bool isS4_3Immediate(const int value) const; 155 bool isS4_2Immediate(const int value) const; 156 bool isS4_1Immediate(const int value) const; 157 bool isS4_0Immediate(const int value) const; 158 bool isS12_Immediate(const int value) const; 159 bool isU6_Immediate(const int value) const; 160 bool isS8_Immediate(const int value) const; 161 bool isS6_Immediate(const int value) const; 162 163 bool isConditionalALU32 (const MachineInstr* MI) const; 164 bool isConditionalLoad (const MachineInstr* MI) const; 165 bool isDeallocRet(const MachineInstr *MI) const; 166 unsigned getInvertedPredicatedOpcode(const int Opc) const; 167 168 private: 169 int getMatchingCondBranchOpcode(int Opc, bool sense) const; 170 171 }; 172 173 } 174 175 #endif 176
