/external/llvm/lib/Target/PTX/ |
PTXMachineFunctionInfo.h | 52 RegisterInfoMap RegInfo; 84 if (!RegInfo.count(Reg)) { 92 for(RegisterInfoMap::const_iterator i = RegInfo.begin(), 93 e = RegInfo.end(); i != e; ++i) { 103 RegInfo[Reg] = Info; 116 for(RegisterInfoMap::const_iterator i = RegInfo.begin(), e = RegInfo.end(); 127 return RegInfo.lookup(Reg).Encoded; 145 if (RegInfo.count(Reg)) { 146 const RegisterInfo& RI = RegInfo.lookup(Reg) [all...] |
/external/llvm/lib/Target/ARM/ |
Thumb1FrameLowering.cpp | 51 const Thumb1RegisterInfo *RegInfo = 60 unsigned FramePtr = RegInfo->getFrameRegister(MF); 61 unsigned BasePtr = RegInfo->getBaseRegister(); 73 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize, 78 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 146 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 159 if (RegInfo->needsStackRealignment(MF)) 166 if (RegInfo->hasBasePointer(MF)) 209 const Thumb1RegisterInfo *RegInfo = 216 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs() [all...] |
ARMFrameLowering.cpp | 42 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 52 RegInfo->needsStackRealignment(MF) || 135 const ARMBaseRegisterInfo *RegInfo = 146 unsigned FramePtr = RegInfo->getFrameRegister(MF); 285 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) { 319 if (RegInfo->hasBasePointer(MF)) { 322 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) 327 RegInfo->getBaseRegister()) 346 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 355 unsigned FramePtr = RegInfo->getFrameRegister(MF) [all...] |
/external/llvm/lib/CodeGen/ |
MachineFunction.cpp | 57 RegInfo = new (Allocator) MachineRegisterInfo(*TM.getRegisterInfo()); 59 RegInfo = 0; 79 if (RegInfo) { 80 RegInfo->~MachineRegisterInfo(); 81 Allocator.Deallocate(RegInfo); 289 if (RegInfo) { 290 OS << (RegInfo->isSSA() ? "SSA" : "Post SSA"); 291 if (!RegInfo->tracksLiveness()) 308 if (RegInfo && !RegInfo->livein_empty()) [all...] |
MachineInstr.cpp | 53 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 56 // If the reginfo pointer is null, just explicitly null out or next/prev 58 if (RegInfo == 0) { 65 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 618 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 621 Operands[i].AddRegOperandToRegInfo(&RegInfo); 633 MachineRegisterInfo *RegInfo = getRegInfo(); 636 // be removed and re-added to RegInfo. It is storing pointers to operands. 637 bool Reallocate = RegInfo && 644 // Remove all the implicit operands from RegInfo if they need to be shifted [all...] |
PrologEpilogInserter.cpp | 153 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); 200 RegInfo->eliminateCallFramePseudoInstr(Fn, *I->getParent(), I); 208 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); 213 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&Fn); 248 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); 251 if (RegInfo->hasReservedSpillSlot(Fn, Reg, FrameIdx)) { 560 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); 561 if (RS && TFI.hasFP(Fn) && RegInfo->useFPForScavengingIndex(Fn) && 562 !RegInfo->needsStackRealignment(Fn)) { 644 if (RS && (!TFI.hasFP(Fn) || RegInfo->needsStackRealignment(Fn) | [all...] |
MachineInstrBundle.cpp | 251 MachineOperandIteratorBase::RegInfo 254 RegInfo RI = { false, false, false };
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/external/llvm/include/llvm/CodeGen/ |
MachineInstrBundle.h | 133 /// RegInfo - Information about a virtual register used by a set of operands. 135 struct RegInfo { 156 /// @returns A filled-in RegInfo struct. 157 RegInfo analyzeVirtReg(unsigned Reg,
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MachineInstr.h | 780 const TargetRegisterInfo &RegInfo); [all...] |
MachineFunction.h | 81 // RegInfo - Information about each register in use in the function. 82 MachineRegisterInfo *RegInfo; 156 MachineRegisterInfo &getRegInfo() { return *RegInfo; } 157 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
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FunctionLoweringInfo.h | 59 MachineRegisterInfo *RegInfo;
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SelectionDAGISel.h | 49 MachineRegisterInfo *RegInfo;
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/external/llvm/lib/Target/X86/ |
X86FrameLowering.cpp | 497 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 498 unsigned FramePtr = RegInfo->getFrameRegister(MF); 499 unsigned StackPtr = RegInfo->getStackRegister(); 637 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 650 unsigned SlotSize = RegInfo->getSlotSize(); 651 unsigned FramePtr = RegInfo->getFrameRegister(MF); 652 unsigned StackPtr = RegInfo->getStackRegister(); 677 !RegInfo->needsStackRealignment(MF) && 724 if (RegInfo->needsStackRealignment(MF)) 786 if (RegInfo->needsStackRealignment(MF)) [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | [all...] |
MipsISelDAGToDAG.cpp | 125 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 139 V0 = RegInfo.createVirtualRegister(RC); 140 V1 = RegInfo.createVirtualRegister(RC);
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MipsFrameLowering.cpp | 133 const MipsRegisterInfo *RegInfo = 221 const uint16_t *SubRegs = RegInfo->getSubRegisters(Reg);
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/external/llvm/lib/Target/MBlaze/ |
MBlazeInstrInfo.cpp | 287 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 290 GlobalBaseReg = RegInfo.createVirtualRegister(MBlaze::GPRRegisterClass); 293 RegInfo.addLiveIn(MBlaze::R20);
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/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | 174 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) { 176 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { 195 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 196 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 241 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass); 245 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass); [all...] |
PPCISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcInstrInfo.cpp | 347 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 349 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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/external/llvm/lib/Target/XCore/ |
XCoreFrameLowering.cpp | 342 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 361 if (RegInfo->requiresRegisterScavenging(MF)) {
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/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGISel.cpp | 350 RegInfo = &MF->getRegInfo(); 375 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 379 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 380 E = RegInfo->livein_end(); LI != E; ++LI) 391 MachineInstr *Def = RegInfo->getVRegDef(Reg); 400 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 416 UI = RegInfo->use_begin(LDI->second); [all...] |
FunctionLoweringInfo.cpp | 65 RegInfo = &MF->getRegInfo(); 212 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
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/external/llvm/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 635 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 636 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | 806 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 842 RegInfo.createVirtualRegister(Hexagon::IntRegsRegisterClass); 843 RegInfo.addLiveIn(VA.getLocReg(), VReg); 847 RegInfo.createVirtualRegister(Hexagon::DoubleRegsRegisterClass); 848 RegInfo.addLiveIn(VA.getLocReg(), VReg); [all...] |