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    Searched refs:addReg (Results 26 - 50 of 78) sorted by null

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  /external/llvm/lib/Target/ARM/
ARMFastISel.cpp 305 .addReg(Op0, Op0IsKill * RegState::Kill));
308 .addReg(Op0, Op0IsKill * RegState::Kill));
311 .addReg(II.ImplicitDefs[0]));
325 .addReg(Op0, Op0IsKill * RegState::Kill)
326 .addReg(Op1, Op1IsKill * RegState::Kill));
329 .addReg(Op0, Op0IsKill * RegState::Kill)
330 .addReg(Op1, Op1IsKill * RegState::Kill));
333 .addReg(II.ImplicitDefs[0]));
348 .addReg(Op0, Op0IsKill * RegState::Kill)
349 .addReg(Op1, Op1IsKill * RegState::Kill
    [all...]
Thumb1RegisterInfo.cpp 78 .addReg(DestReg, getDefRegState(true), SubIdx)
79 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
122 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags);
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
247 .addReg(BaseReg, RegState::Kill))
263 MIB.addReg(DestReg).addImm(ThisVal)
    [all...]
Thumb1InstrInfo.cpp 46 .addReg(SrcReg, getKillRegState(KillSrc)));
74 .addReg(SrcReg, getKillRegState(isKill))
Thumb1FrameLowering.cpp 168 .addReg(ARM::SP));
249 .addReg(ARM::R4));
253 .addReg(FramePtr));
276 .addReg(ARM::R3, RegState::Define);
282 .addReg(ARM::R3, RegState::Kill);
323 MIB.addReg(Reg, getKillRegState(isKill));
358 MIB.addReg(Reg, getDefRegState(true));
ARMBaseInstrInfo.cpp 170 .addReg(BaseReg).addImm(Amt)
171 .addImm(Pred).addReg(0).addReg(0);
177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
178 .addImm(Pred).addReg(0).addReg(0);
182 .addReg(BaseReg).addReg(OffReg
    [all...]
ARMBaseInstrInfo.h 303 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
308 return MIB.addReg(0);
314 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
319 return MIB.addReg(0);
  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.cpp 68 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
104 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
105 .addReg(SP::I6);
SparcInstrInfo.cpp 285 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
286 .addReg(SrcReg, getKillRegState(KillSrc));
289 .addReg(SrcReg, getKillRegState(KillSrc));
292 .addReg(SrcReg, getKillRegState(KillSrc));
308 .addReg(SrcReg, getKillRegState(isKill));
311 .addReg(SrcReg, getKillRegState(isKill));
314 .addReg(SrcReg, getKillRegState(isKill));
  /external/llvm/lib/Target/MBlaze/
MBlazeInstrInfo.cpp 89 .addReg(SrcReg, getKillRegState(KillSrc)).addReg(MBlaze::R0);
98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
292 GlobalBaseReg).addReg(MBlaze::R20);
MBlazeRegisterInfo.cpp 108 .addReg(MBlaze::R1).addImm(-Amount);
112 .addReg(MBlaze::R1).addImm(Amount);
  /external/llvm/lib/Target/Mips/
MipsRegisterInfo.cpp 244 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
249 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
252 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(ATReg);
MipsISelDAGToDAG.cpp 153 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0).addReg(Mips::T9_64);
154 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
163 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
176 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
177 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
183 .addReg(Mips::T9);
  /external/llvm/lib/Target/MSP430/
MSP430InstrInfo.cpp 53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
101 .addReg(SrcReg, getKillRegState(KillSrc));
  /external/llvm/lib/Target/XCore/
XCoreInstrInfo.cpp 291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
343 .addReg(SrcReg, getKillRegState(KillSrc))
355 .addReg(SrcReg, getKillRegState(KillSrc));
371 .addReg(SrcReg, getKillRegState(isKill))
  /external/llvm/lib/Target/PTX/
PTXInstrInfo.cpp 60 addReg(SrcReg, getKillRegState(KillSrc));
81 MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg).addReg(SrcReg);
282 .addMBB(TBB).addReg(Cond[0].getReg()).addImm(Cond[1].getImm());
284 .addMBB(FBB).addReg(PTX::NoRegister).addImm(PTXPredicate::None);
288 .addMBB(TBB).addReg(Cond[0].getReg()).addImm(Cond[1].getImm());
292 .addMBB(TBB).addReg(PTX::NoRegister).addImm(PTXPredicate::None);
  /external/llvm/lib/Target/X86/
X86FastISel.cpp 245 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
276 DL, TII.get(Opc)), AM).addReg(Val);
804 DstReg).addReg(SrcReg);
890 .addReg(Op0Reg)
902 .addReg(Op0Reg)
903 .addReg(Op1Reg);
929 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
942 .addReg(PReg).addReg(NEReg)
    [all...]
  /external/llvm/include/llvm/CodeGen/
MachineInstrBuilder.h 13 // M = BuildMI(X86::ADDrr8, 2).addReg(argVal1).addReg(argVal2);
55 /// addReg - Add a new virtual register operand...
58 MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
61 "Passing in 'true' to addReg is forbidden! Use enums instead.");
201 .addReg(DestReg, RegState::Define);
215 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
225 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
  /external/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp     [all...]
PPCBranchSelector.cpp 152 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 158 VRBase).addReg(SrcReg);
302 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
422 .addReg(VReg);
469 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
484 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
554 NewVReg).addReg(VReg);
633 MIB.addReg(0U); // undef
649 MIB.addReg(0U);
653 MIB.addReg(0U);
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonHardwareLoops.cpp 486 TII->get(TargetOpcode::COPY), CountReg).addReg(TripCount->getReg());
491 TII->get(Hexagon::NEG), CountReg).addReg(CountReg1);
496 TII->get(Hexagon::LOOP0_r)).addMBB(LoopStart).addReg(CountReg);
632 .addReg(MII->getOperand(1).getReg());
638 .addReg(Scratch);
643 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::SA0).addReg(Scratch);
  /external/llvm/lib/Target/CellSPU/
SPUInstrInfo.cpp 135 .addReg(SrcReg, getKillRegState(KillSrc));
170 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
389 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
406 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
  /external/llvm/lib/CodeGen/
StrongPHIElimination.cpp 92 void addReg(unsigned);
97 /// addReg(r2);
244 addReg(DestReg);
250 addReg(SrcReg);
288 addReg(DestReg);
292 addReg(SrcReg);
406 void StrongPHIElimination::addReg(unsigned Reg) {
699 CopyReg).addReg(SrcReg, 0, SrcSubReg);
708 addReg(CopyReg);
768 DestReg).addReg(CopyReg)
    [all...]
MachineInstrBundle.cpp 190 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
199 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
TargetInstrInfoImpl.cpp 106 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead), SubReg0)
107 .addReg(Reg2, getKillRegState(Reg2IsKill), SubReg2)
108 .addReg(Reg1, getKillRegState(Reg1IsKill), SubReg1);
111 .addReg(Reg2, getKillRegState(Reg2IsKill), SubReg2)
112 .addReg(Reg1, getKillRegState(Reg1IsKill), SubReg1);

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12 3 4