| /external/llvm/test/CodeGen/X86/ |
| rot64.ll | 5 ; RUN: grep shrd %t | count 2
|
| /external/llvm/lib/Target/X86/ |
| X86InstrShiftRotate.td | [all...] |
| X86ISelLowering.h | 39 /// SHLD, SHRD - Double shift instructions. These correspond to
42 SHRD,
[all...] |
| X86InstrInfo.td | 123 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
[all...] |
| /external/icu4c/test/cintltst/ |
| cucdapi.c | 324 "Afak", "Jurc", "Mroo", "Nshu", "Shrd", "Sora", "Takr", "Tang", "Wole",
344 "Afak", "Jurc", "Mroo", "Nshu", "Shrd", "Sora", "Takr", "Tang", "Wole",
|
| /external/openssl/crypto/modes/asm/ |
| ghash-x86.pl | 144 # shrd practically kills P4, 2.5x deterioration, but P4 has
145 # MMX code-path to execute. shrd runs tad faster [than twice
156 &shrd ($Zll,$Zlh,4);
158 &shrd ($Zlh,$Zhl,4);
159 &shrd ($Zhl,$Zhh,4);
187 &shrd ($Zll,$Zlh,4);
189 &shrd ($Zlh,$Zhl,4);
190 &shrd ($Zhl,$Zhh,4);
[all...] |
| /external/v8/test/cctest/ |
| test-disasm-ia32.cc | 127 __ shrd(edx, ecx);
209 __ shrd(edx, Operand(ebx, ecx, times_4, 10000));
|
| test-disasm-x64.cc | 121 __ shrd(rdx, rcx);
197 __ shrd(rdx, rbx);
|
| /external/llvm/test/MC/X86/ |
| x86-64.s | 362 shrd %bx, %dx label
363 shrd %cl, %bx, %dx label
364 shrd $1, %bx, %dx label
365 shrd %bx, (%rax) label
366 shrd %cl, %bx, (%rax) label
|
| /external/libvpx/examples/includes/geshi/geshi/ |
| asm.php | 76 'setpe','setpo','sets','setz','shld','shrd','stosd','bswap','cmpxchg','invd','invlpg','wbinvd','xadd','lock',
|
| /external/v8/src/ia32/ |
| assembler-ia32.h | 819 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
820 void shrd(Register dst, const Operand& src);
[all...] |
| disasm-ia32.cc | 870 case 0xAD: return "shrd";
1054 // shrd, shld, bts
[all...] |
| /external/icu4c/common/unicode/ |
| uscript.h | 375 USCRIPT_SHARADA = 151,/* Shrd */
|
| /external/qemu/distrib/sdl-1.2.12/src/stdlib/ |
| SDL_stdlib.c | 602 shrd eax,edx,cl
|
| /external/llvm/test/Instrumentation/AddressSanitizer/X86/ |
| bug_11395.ll | 63 %2 = call { i32*, i32*, i32* } asm sideeffect "1: \0A\09xor %esi, %esi\0A\09xor %ecx, %ecx\0A\09jmp *$5 \0A\09ff_mlp_firorder_8: \0A\09mov 0x1c+0($0), %eax\0A\09imull 0x1c+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_7: \0A\09mov 0x18+0($0), %eax\0A\09imull 0x18+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_6: \0A\09mov 0x14+0($0), %eax\0A\09imull 0x14+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_5: \0A\09mov 0x10+0($0), %eax\0A\09imull 0x10+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_4: \0A\09mov 0x0c+0($0), %eax\0A\09imull 0x0c+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_3: \0A\09mov 0x08+0($0), %eax\0A\09imull 0x08+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_2: \0A\09mov 0x04+0($0), %eax\0A\09imull 0x04+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_1: \0A\09mov 0x00+0($0), %eax\0A\09imull 0x00+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_0:\0A\09jmp *$6 \0A\09ff_mlp_iirorder_4: \0A\09mov 0x0c+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x0c+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_3: \0A\09mov 0x08+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x08+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_2: \0A\09mov 0x04+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x04+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_1: \0A\09mov 0x00+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x00+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_0:\0A\09mov %ecx, %edx\0A\09mov %esi, %eax\0A\09movzbl $7 , %ecx\0A\09shrd %cl, %edx, %eax\0A\09mov %eax ,%edx \0A\09add ($2) ,%eax \0A\09and $4 ,%eax \0A\09sub $$4 , $0 \0A\09mov %eax, ($0) \0A\09mov %eax, ($2) \0A\09add $$4* 8 , $2 \0A\09sub %edx ,%eax \0A\09mov %eax,4*(8 + (40 * 4))($0) \0A\09incl $3 \0A\09js 1b \0A\09", "=r,=r,=r,=*m,*m,*m,*m,*m,0,1,2,*m,~{eax},~{edx},~{esi},~{ecx},~{dirflag},~{fpsr},~{flags}"(i32* %blocksize.addr, i32* %mask.addr, i8** %firjump, i8** %iirjump, i32* %filter_shift.addr, i32* %state, i32* %coeff, i32* %sample_buffer, i32* %blocksize.addr) nounwind, !srcloc !4
|
| /external/qemu/ |
| Changelog | 529 - fixed shrd, shld, idivl and divl on PowerPC.
|
| /external/valgrind/main/VEX/priv/ |
| host_amd64_defs.h | 473 //.. /* shld/shrd. op may only be Xsh_SHL or Xsh_SHR */
|
| host_x86_defs.h | 430 /* shld/shrd. op may only be Xsh_SHL or Xsh_SHR */
|
| /external/elfutils/libcpu/defs/ |
| i386 | 519 00001111,10101100,{mod}{reg}{r_m},{imm8}:shrd {imm8},{reg},{mod}{r_m}
520 00001111,10101101,{mod}{reg}{r_m}:shrd %cl,{reg},{mod}{r_m}
[all...] |
| /external/v8/src/x64/ |
| disasm-x64.cc | [all...] |
| /external/quake/quake/src/QW/scitech/include/ |
| mgraph.h | [all...] |
| /external/quake/quake/src/WinQuake/scitech/INCLUDE/ |
| MGRAPH.H | [all...] |
| /external/icu4c/data/unidata/ |
| changes.txt | 38 Shrd 319 Sharada, ??rad?
[all...] |
| /external/openssl/crypto/aes/asm/ |
| aesni-sha1-x86_64.pl | 645 my $_ror=sub { &shrd(@_[0],@_) };
|
| /external/openssl/crypto/sha/asm/ |
| sha1-586.pl | 865 my $_ror=sub { &shrd(@_[0],@_) };
[all...] |
