1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 instruction set, defining the instructions, and 11 // properties of the instructions which are needed for code generation, machine 12 // code emission, and analysis. 13 // 14 //===----------------------------------------------------------------------===// 15 16 //===----------------------------------------------------------------------===// 17 // X86 specific DAG Nodes. 18 // 19 20 def SDTIntShiftDOp: SDTypeProfile<1, 3, 21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 22 SDTCisInt<0>, SDTCisInt<3>]>; 23 24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; 25 26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 28 29 def SDTX86Cmov : SDTypeProfile<1, 4, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 32 33 // Unary and binary operator instructions that set EFLAGS as a side-effect. 34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 35 [SDTCisInt<0>, SDTCisVT<1, i32>]>; 36 37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 38 [SDTCisSameAs<0, 2>, 39 SDTCisSameAs<0, 3>, 40 SDTCisInt<0>, SDTCisVT<1, i32>]>; 41 42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 44 [SDTCisSameAs<0, 2>, 45 SDTCisSameAs<0, 3>, 46 SDTCisInt<0>, 47 SDTCisVT<1, i32>, 48 SDTCisVT<4, i32>]>; 49 // RES1, RES2, FLAGS = op LHS, RHS 50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 51 [SDTCisSameAs<0, 1>, 52 SDTCisSameAs<0, 2>, 53 SDTCisSameAs<0, 3>, 54 SDTCisInt<0>, SDTCisVT<1, i32>]>; 55 def SDTX86BrCond : SDTypeProfile<0, 3, 56 [SDTCisVT<0, OtherVT>, 57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 58 59 def SDTX86SetCC : SDTypeProfile<1, 2, 60 [SDTCisVT<0, i8>, 61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 62 def SDTX86SetCC_C : SDTypeProfile<1, 2, 63 [SDTCisInt<0>, 64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 65 66 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 67 SDTCisVT<2, i8>]>; 68 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 69 70 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, 71 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; 72 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; 73 74 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 75 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 76 SDTCisVT<1, i32>]>; 77 78 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 79 80 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 81 SDTCisVT<1, iPTR>, 82 SDTCisVT<2, iPTR>]>; 83 84 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 85 SDTCisPtrTy<1>, 86 SDTCisVT<2, i32>, 87 SDTCisVT<3, i8>, 88 SDTCisVT<4, i32>]>; 89 90 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 91 92 def SDTX86Void : SDTypeProfile<0, 0, []>; 93 94 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 95 96 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 97 98 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 99 100 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 101 102 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 103 104 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 105 106 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 107 108 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 109 110 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 111 [SDNPHasChain]>; 112 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 113 [SDNPHasChain]>; 114 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, 115 [SDNPHasChain]>; 116 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, 117 [SDNPHasChain]>; 118 119 120 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 121 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 122 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; 123 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; 124 125 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 126 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 127 128 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 129 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 130 [SDNPHasChain]>; 131 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 132 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 133 134 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 135 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 136 SDNPMayLoad, SDNPMemOperand]>; 137 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, 138 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 139 SDNPMayLoad, SDNPMemOperand]>; 140 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, 141 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 142 SDNPMayLoad, SDNPMemOperand]>; 143 144 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary, 145 [SDNPHasChain, SDNPMayStore, 146 SDNPMayLoad, SDNPMemOperand]>; 147 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary, 148 [SDNPHasChain, SDNPMayStore, 149 SDNPMayLoad, SDNPMemOperand]>; 150 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary, 151 [SDNPHasChain, SDNPMayStore, 152 SDNPMayLoad, SDNPMemOperand]>; 153 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary, 154 [SDNPHasChain, SDNPMayStore, 155 SDNPMayLoad, SDNPMemOperand]>; 156 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary, 157 [SDNPHasChain, SDNPMayStore, 158 SDNPMayLoad, SDNPMemOperand]>; 159 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary, 160 [SDNPHasChain, SDNPMayStore, 161 SDNPMayLoad, SDNPMemOperand]>; 162 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary, 163 [SDNPHasChain, SDNPMayStore, 164 SDNPMayLoad, SDNPMemOperand]>; 165 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 166 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 167 168 def X86vastart_save_xmm_regs : 169 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 170 SDT_X86VASTART_SAVE_XMM_REGS, 171 [SDNPHasChain, SDNPVariadic]>; 172 def X86vaarg64 : 173 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 174 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 175 SDNPMemOperand]>; 176 def X86callseq_start : 177 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 178 [SDNPHasChain, SDNPOutGlue]>; 179 def X86callseq_end : 180 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 181 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 182 183 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 184 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 185 SDNPVariadic]>; 186 187 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 188 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 189 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 190 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 191 SDNPMayLoad]>; 192 193 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, 194 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 195 196 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 197 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 198 199 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 200 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 201 202 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 203 [SDNPHasChain]>; 204 205 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 206 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 207 208 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 209 [SDNPCommutative]>; 210 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 211 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 212 [SDNPCommutative]>; 213 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 214 [SDNPCommutative]>; 215 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 216 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 217 218 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; 219 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; 220 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 221 [SDNPCommutative]>; 222 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 223 [SDNPCommutative]>; 224 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 225 [SDNPCommutative]>; 226 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>; 227 228 def X86blsi_flag : SDNode<"X86ISD::BLSI", SDTUnaryArithWithFlags>; 229 def X86blsmsk_flag : SDNode<"X86ISD::BLSMSK", SDTUnaryArithWithFlags>; 230 def X86blsr_flag : SDNode<"X86ISD::BLSR", SDTUnaryArithWithFlags>; 231 232 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 233 234 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void, 235 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 236 237 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 238 [SDNPHasChain]>; 239 240 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 241 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 242 243 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL, 244 [SDNPHasChain, SDNPOutGlue]>; 245 246 //===----------------------------------------------------------------------===// 247 // X86 Operand Definitions. 248 // 249 250 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 251 // the index operand of an address, to conform to x86 encoding restrictions. 252 def ptr_rc_nosp : PointerLikeRegClass<1>; 253 254 // *mem - Operand definitions for the funky X86 addressing mode operands. 255 // 256 def X86MemAsmOperand : AsmOperandClass { 257 let Name = "Mem"; let PredicateMethod = "isMem"; 258 } 259 def X86Mem8AsmOperand : AsmOperandClass { 260 let Name = "Mem8"; let PredicateMethod = "isMem8"; 261 } 262 def X86Mem16AsmOperand : AsmOperandClass { 263 let Name = "Mem16"; let PredicateMethod = "isMem16"; 264 } 265 def X86Mem32AsmOperand : AsmOperandClass { 266 let Name = "Mem32"; let PredicateMethod = "isMem32"; 267 } 268 def X86Mem64AsmOperand : AsmOperandClass { 269 let Name = "Mem64"; let PredicateMethod = "isMem64"; 270 } 271 def X86Mem80AsmOperand : AsmOperandClass { 272 let Name = "Mem80"; let PredicateMethod = "isMem80"; 273 } 274 def X86Mem128AsmOperand : AsmOperandClass { 275 let Name = "Mem128"; let PredicateMethod = "isMem128"; 276 } 277 def X86Mem256AsmOperand : AsmOperandClass { 278 let Name = "Mem256"; let PredicateMethod = "isMem256"; 279 } 280 281 def X86AbsMemAsmOperand : AsmOperandClass { 282 let Name = "AbsMem"; 283 let SuperClasses = [X86MemAsmOperand]; 284 } 285 class X86MemOperand<string printMethod> : Operand<iPTR> { 286 let PrintMethod = printMethod; 287 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 288 let ParserMatchClass = X86MemAsmOperand; 289 } 290 291 let OperandType = "OPERAND_MEMORY" in { 292 def opaque32mem : X86MemOperand<"printopaquemem">; 293 def opaque48mem : X86MemOperand<"printopaquemem">; 294 def opaque80mem : X86MemOperand<"printopaquemem">; 295 def opaque512mem : X86MemOperand<"printopaquemem">; 296 297 def i8mem : X86MemOperand<"printi8mem"> { 298 let ParserMatchClass = X86Mem8AsmOperand; } 299 def i16mem : X86MemOperand<"printi16mem"> { 300 let ParserMatchClass = X86Mem16AsmOperand; } 301 def i32mem : X86MemOperand<"printi32mem"> { 302 let ParserMatchClass = X86Mem32AsmOperand; } 303 def i64mem : X86MemOperand<"printi64mem"> { 304 let ParserMatchClass = X86Mem64AsmOperand; } 305 def i128mem : X86MemOperand<"printi128mem"> { 306 let ParserMatchClass = X86Mem128AsmOperand; } 307 def i256mem : X86MemOperand<"printi256mem"> { 308 let ParserMatchClass = X86Mem256AsmOperand; } 309 def f32mem : X86MemOperand<"printf32mem"> { 310 let ParserMatchClass = X86Mem32AsmOperand; } 311 def f64mem : X86MemOperand<"printf64mem"> { 312 let ParserMatchClass = X86Mem64AsmOperand; } 313 def f80mem : X86MemOperand<"printf80mem"> { 314 let ParserMatchClass = X86Mem80AsmOperand; } 315 def f128mem : X86MemOperand<"printf128mem"> { 316 let ParserMatchClass = X86Mem128AsmOperand; } 317 def f256mem : X86MemOperand<"printf256mem">{ 318 let ParserMatchClass = X86Mem256AsmOperand; } 319 } 320 321 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of 322 // plain GR64, so that it doesn't potentially require a REX prefix. 323 def i8mem_NOREX : Operand<i64> { 324 let PrintMethod = "printi8mem"; 325 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); 326 let ParserMatchClass = X86Mem8AsmOperand; 327 let OperandType = "OPERAND_MEMORY"; 328 } 329 330 // GPRs available for tailcall. 331 // It represents GR64_TC or GR64_TCW64. 332 def ptr_rc_tailcall : PointerLikeRegClass<2>; 333 334 // Special i32mem for addresses of load folding tail calls. These are not 335 // allowed to use callee-saved registers since they must be scheduled 336 // after callee-saved register are popped. 337 def i32mem_TC : Operand<i32> { 338 let PrintMethod = "printi32mem"; 339 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm); 340 let ParserMatchClass = X86Mem32AsmOperand; 341 let OperandType = "OPERAND_MEMORY"; 342 } 343 344 // Special i64mem for addresses of load folding tail calls. These are not 345 // allowed to use callee-saved registers since they must be scheduled 346 // after callee-saved register are popped. 347 def i64mem_TC : Operand<i64> { 348 let PrintMethod = "printi64mem"; 349 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 350 ptr_rc_tailcall, i32imm, i8imm); 351 let ParserMatchClass = X86Mem64AsmOperand; 352 let OperandType = "OPERAND_MEMORY"; 353 } 354 355 let OperandType = "OPERAND_PCREL", 356 ParserMatchClass = X86AbsMemAsmOperand, 357 PrintMethod = "print_pcrel_imm" in { 358 def i32imm_pcrel : Operand<i32>; 359 def i16imm_pcrel : Operand<i16>; 360 361 def offset8 : Operand<i64>; 362 def offset16 : Operand<i64>; 363 def offset32 : Operand<i64>; 364 def offset64 : Operand<i64>; 365 366 // Branch targets have OtherVT type and print as pc-relative values. 367 def brtarget : Operand<OtherVT>; 368 def brtarget8 : Operand<OtherVT>; 369 370 } 371 372 def SSECC : Operand<i8> { 373 let PrintMethod = "printSSECC"; 374 let OperandType = "OPERAND_IMMEDIATE"; 375 } 376 377 def AVXCC : Operand<i8> { 378 let PrintMethod = "printSSECC"; 379 let OperandType = "OPERAND_IMMEDIATE"; 380 } 381 382 class ImmSExtAsmOperandClass : AsmOperandClass { 383 let SuperClasses = [ImmAsmOperand]; 384 let RenderMethod = "addImmOperands"; 385 } 386 387 class ImmZExtAsmOperandClass : AsmOperandClass { 388 let SuperClasses = [ImmAsmOperand]; 389 let RenderMethod = "addImmOperands"; 390 } 391 392 // Sign-extended immediate classes. We don't need to define the full lattice 393 // here because there is no instruction with an ambiguity between ImmSExti64i32 394 // and ImmSExti32i8. 395 // 396 // The strange ranges come from the fact that the assembler always works with 397 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 398 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 399 400 // [0, 0x7FFFFFFF] | 401 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 402 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 403 let Name = "ImmSExti64i32"; 404 } 405 406 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 407 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 408 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 409 let Name = "ImmSExti16i8"; 410 let SuperClasses = [ImmSExti64i32AsmOperand]; 411 } 412 413 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 414 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 415 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 416 let Name = "ImmSExti32i8"; 417 } 418 419 // [0, 0x000000FF] 420 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass { 421 let Name = "ImmZExtu32u8"; 422 } 423 424 425 // [0, 0x0000007F] | 426 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 427 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 428 let Name = "ImmSExti64i8"; 429 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 430 ImmSExti64i32AsmOperand]; 431 } 432 433 // A couple of more descriptive operand definitions. 434 // 16-bits but only 8 bits are significant. 435 def i16i8imm : Operand<i16> { 436 let ParserMatchClass = ImmSExti16i8AsmOperand; 437 let OperandType = "OPERAND_IMMEDIATE"; 438 } 439 // 32-bits but only 8 bits are significant. 440 def i32i8imm : Operand<i32> { 441 let ParserMatchClass = ImmSExti32i8AsmOperand; 442 let OperandType = "OPERAND_IMMEDIATE"; 443 } 444 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned. 445 def u32u8imm : Operand<i32> { 446 let ParserMatchClass = ImmZExtu32u8AsmOperand; 447 let OperandType = "OPERAND_IMMEDIATE"; 448 } 449 450 // 64-bits but only 32 bits are significant. 451 def i64i32imm : Operand<i64> { 452 let ParserMatchClass = ImmSExti64i32AsmOperand; 453 let OperandType = "OPERAND_IMMEDIATE"; 454 } 455 456 // 64-bits but only 32 bits are significant, and those bits are treated as being 457 // pc relative. 458 def i64i32imm_pcrel : Operand<i64> { 459 let PrintMethod = "print_pcrel_imm"; 460 let ParserMatchClass = X86AbsMemAsmOperand; 461 let OperandType = "OPERAND_PCREL"; 462 } 463 464 // 64-bits but only 8 bits are significant. 465 def i64i8imm : Operand<i64> { 466 let ParserMatchClass = ImmSExti64i8AsmOperand; 467 let OperandType = "OPERAND_IMMEDIATE"; 468 } 469 470 def lea64_32mem : Operand<i32> { 471 let PrintMethod = "printi32mem"; 472 let AsmOperandLowerMethod = "lower_lea64_32mem"; 473 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm); 474 let ParserMatchClass = X86MemAsmOperand; 475 } 476 477 478 //===----------------------------------------------------------------------===// 479 // X86 Complex Pattern Definitions. 480 // 481 482 // Define X86 specific addressing mode. 483 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>; 484 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr", 485 [add, sub, mul, X86mul_imm, shl, or, frameindex], 486 []>; 487 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 488 [tglobaltlsaddr], []>; 489 490 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr", 491 [add, sub, mul, X86mul_imm, shl, or, frameindex, 492 X86WrapperRIP], []>; 493 494 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 495 [tglobaltlsaddr], []>; 496 497 //===----------------------------------------------------------------------===// 498 // X86 Instruction Predicate Definitions. 499 def HasCMov : Predicate<"Subtarget->hasCMov()">; 500 def NoCMov : Predicate<"!Subtarget->hasCMov()">; 501 502 def HasMMX : Predicate<"Subtarget->hasMMX()">; 503 def Has3DNow : Predicate<"Subtarget->has3DNow()">; 504 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 505 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 506 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 507 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 508 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 509 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 510 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 511 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 512 def HasAVX : Predicate<"Subtarget->hasAVX()">; 513 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 514 515 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 516 def HasAES : Predicate<"Subtarget->hasAES()">; 517 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">; 518 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">; 519 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 520 def HasXOP : Predicate<"Subtarget->hasXOP()">; 521 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 522 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 523 def HasF16C : Predicate<"Subtarget->hasF16C()">; 524 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 525 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 526 def HasBMI : Predicate<"Subtarget->hasBMI()">; 527 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 528 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 529 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 530 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; 531 def In32BitMode : Predicate<"!Subtarget->is64Bit()">, 532 AssemblerPredicate<"!Mode64Bit">; 533 def In64BitMode : Predicate<"Subtarget->is64Bit()">, 534 AssemblerPredicate<"Mode64Bit">; 535 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 536 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 537 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 538 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 539 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 540 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" 541 "TM.getCodeModel() != CodeModel::Kernel">; 542 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 543 "TM.getCodeModel() == CodeModel::Kernel">; 544 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; 545 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; 546 def OptForSize : Predicate<"OptForSize">; 547 def OptForSpeed : Predicate<"!OptForSize">; 548 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; 549 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; 550 551 //===----------------------------------------------------------------------===// 552 // X86 Instruction Format Definitions. 553 // 554 555 include "X86InstrFormats.td" 556 557 //===----------------------------------------------------------------------===// 558 // Pattern fragments. 559 // 560 561 // X86 specific condition code. These correspond to CondCode in 562 // X86InstrInfo.h. They must be kept in synch. 563 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE 564 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC 565 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 566 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA 567 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 568 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE 569 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL 570 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE 571 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG 572 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ 573 def X86_COND_NO : PatLeaf<(i8 10)>; 574 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 575 def X86_COND_NS : PatLeaf<(i8 12)>; 576 def X86_COND_O : PatLeaf<(i8 13)>; 577 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE 578 def X86_COND_S : PatLeaf<(i8 15)>; 579 580 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs. 581 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>; 582 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>; 583 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>; 584 } 585 586 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>; 587 588 589 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 590 // unsigned field. 591 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>; 592 593 def i64immZExt32SExt8 : ImmLeaf<i64, [{ 594 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm; 595 }]>; 596 597 // Helper fragments for loads. 598 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is 599 // known to be 32-bit aligned or better. Ditto for i8 to i16. 600 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 601 LoadSDNode *LD = cast<LoadSDNode>(N); 602 ISD::LoadExtType ExtType = LD->getExtensionType(); 603 if (ExtType == ISD::NON_EXTLOAD) 604 return true; 605 if (ExtType == ISD::EXTLOAD) 606 return LD->getAlignment() >= 2 && !LD->isVolatile(); 607 return false; 608 }]>; 609 610 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ 611 LoadSDNode *LD = cast<LoadSDNode>(N); 612 ISD::LoadExtType ExtType = LD->getExtensionType(); 613 if (ExtType == ISD::EXTLOAD) 614 return LD->getAlignment() >= 2 && !LD->isVolatile(); 615 return false; 616 }]>; 617 618 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 619 LoadSDNode *LD = cast<LoadSDNode>(N); 620 ISD::LoadExtType ExtType = LD->getExtensionType(); 621 if (ExtType == ISD::NON_EXTLOAD) 622 return true; 623 if (ExtType == ISD::EXTLOAD) 624 return LD->getAlignment() >= 4 && !LD->isVolatile(); 625 return false; 626 }]>; 627 628 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; 629 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 630 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 631 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 632 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 633 634 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 635 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 636 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 637 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 638 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 639 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 640 641 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 642 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 643 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 644 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 645 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 646 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 647 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 648 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 649 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 650 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 651 652 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 653 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 654 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 655 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 656 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 657 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 658 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 659 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 660 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 661 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 662 663 664 // An 'and' node with a single use. 665 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 666 return N->hasOneUse(); 667 }]>; 668 // An 'srl' node with a single use. 669 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 670 return N->hasOneUse(); 671 }]>; 672 // An 'trunc' node with a single use. 673 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 674 return N->hasOneUse(); 675 }]>; 676 677 //===----------------------------------------------------------------------===// 678 // Instruction list. 679 // 680 681 // Nop 682 let neverHasSideEffects = 1 in { 683 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; 684 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero), 685 "nop{w}\t$zero", []>, TB, OpSize; 686 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero), 687 "nop{l}\t$zero", []>, TB; 688 } 689 690 691 // Constructing a stack frame. 692 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 693 "enter\t$len, $lvl", []>; 694 695 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in 696 def LEAVE : I<0xC9, RawFrm, 697 (outs), (ins), "leave", []>, Requires<[In32BitMode]>; 698 699 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in 700 def LEAVE64 : I<0xC9, RawFrm, 701 (outs), (ins), "leave", []>, Requires<[In64BitMode]>; 702 703 //===----------------------------------------------------------------------===// 704 // Miscellaneous Instructions. 705 // 706 707 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { 708 let mayLoad = 1 in { 709 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 710 OpSize; 711 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; 712 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 713 OpSize; 714 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>, 715 OpSize; 716 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; 717 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>; 718 719 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize; 720 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, 721 Requires<[In32BitMode]>; 722 } 723 724 let mayStore = 1 in { 725 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 726 OpSize; 727 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; 728 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 729 OpSize; 730 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>, 731 OpSize; 732 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; 733 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>; 734 735 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 736 "push{l}\t$imm", []>; 737 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 738 "push{w}\t$imm", []>, OpSize; 739 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 740 "push{l}\t$imm", []>; 741 742 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize; 743 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, 744 Requires<[In32BitMode]>; 745 746 } 747 } 748 749 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in { 750 let mayLoad = 1 in { 751 def POP64r : I<0x58, AddRegFrm, 752 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>; 753 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>; 754 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>; 755 } 756 let mayStore = 1 in { 757 def PUSH64r : I<0x50, AddRegFrm, 758 (outs), (ins GR64:$reg), "push{q}\t$reg", []>; 759 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>; 760 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>; 761 } 762 } 763 764 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in { 765 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 766 "push{q}\t$imm", []>; 767 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 768 "push{q}\t$imm", []>; 769 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 770 "push{q}\t$imm", []>; 771 } 772 773 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in 774 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, 775 Requires<[In64BitMode]>; 776 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in 777 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, 778 Requires<[In64BitMode]>; 779 780 781 782 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 783 mayLoad=1, neverHasSideEffects=1 in { 784 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>, 785 Requires<[In32BitMode]>; 786 } 787 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 788 mayStore=1, neverHasSideEffects=1 in { 789 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>, 790 Requires<[In32BitMode]>; 791 } 792 793 let Constraints = "$src = $dst" in { // GR32 = bswap GR32 794 def BSWAP32r : I<0xC8, AddRegFrm, 795 (outs GR32:$dst), (ins GR32:$src), 796 "bswap{l}\t$dst", 797 [(set GR32:$dst, (bswap GR32:$src))]>, TB; 798 799 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 800 "bswap{q}\t$dst", 801 [(set GR64:$dst, (bswap GR64:$src))]>, TB; 802 } // Constraints = "$src = $dst" 803 804 // Bit scan instructions. 805 let Defs = [EFLAGS] in { 806 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 807 "bsf{w}\t{$src, $dst|$dst, $src}", 808 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize; 809 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 810 "bsf{w}\t{$src, $dst|$dst, $src}", 811 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB, 812 OpSize; 813 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 814 "bsf{l}\t{$src, $dst|$dst, $src}", 815 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB; 816 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 817 "bsf{l}\t{$src, $dst|$dst, $src}", 818 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB; 819 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 820 "bsf{q}\t{$src, $dst|$dst, $src}", 821 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB; 822 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 823 "bsf{q}\t{$src, $dst|$dst, $src}", 824 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB; 825 826 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 827 "bsr{w}\t{$src, $dst|$dst, $src}", 828 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize; 829 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 830 "bsr{w}\t{$src, $dst|$dst, $src}", 831 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB, 832 OpSize; 833 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 834 "bsr{l}\t{$src, $dst|$dst, $src}", 835 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB; 836 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 837 "bsr{l}\t{$src, $dst|$dst, $src}", 838 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB; 839 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 840 "bsr{q}\t{$src, $dst|$dst, $src}", 841 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB; 842 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 843 "bsr{q}\t{$src, $dst|$dst, $src}", 844 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB; 845 } // Defs = [EFLAGS] 846 847 848 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 849 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { 850 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", []>; 851 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", []>, OpSize; 852 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", []>; 853 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>; 854 } 855 856 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 857 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in 858 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", []>; 859 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in 860 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", []>, OpSize; 861 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in 862 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", []>; 863 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in 864 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>; 865 866 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", []>; 867 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", []>, OpSize; 868 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", []>; 869 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>; 870 871 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", []>; 872 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", []>, OpSize; 873 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", []>; 874 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>; 875 876 877 //===----------------------------------------------------------------------===// 878 // Move Instructions. 879 // 880 881 let neverHasSideEffects = 1 in { 882 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 883 "mov{b}\t{$src, $dst|$dst, $src}", []>; 884 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 885 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; 886 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 887 "mov{l}\t{$src, $dst|$dst, $src}", []>; 888 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 889 "mov{q}\t{$src, $dst|$dst, $src}", []>; 890 } 891 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 892 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 893 "mov{b}\t{$src, $dst|$dst, $src}", 894 [(set GR8:$dst, imm:$src)]>; 895 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 896 "mov{w}\t{$src, $dst|$dst, $src}", 897 [(set GR16:$dst, imm:$src)]>, OpSize; 898 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 899 "mov{l}\t{$src, $dst|$dst, $src}", 900 [(set GR32:$dst, imm:$src)]>; 901 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 902 "movabs{q}\t{$src, $dst|$dst, $src}", 903 [(set GR64:$dst, imm:$src)]>; 904 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 905 "mov{q}\t{$src, $dst|$dst, $src}", 906 [(set GR64:$dst, i64immSExt32:$src)]>; 907 } 908 909 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 910 "mov{b}\t{$src, $dst|$dst, $src}", 911 [(store (i8 imm:$src), addr:$dst)]>; 912 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 913 "mov{w}\t{$src, $dst|$dst, $src}", 914 [(store (i16 imm:$src), addr:$dst)]>, OpSize; 915 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 916 "mov{l}\t{$src, $dst|$dst, $src}", 917 [(store (i32 imm:$src), addr:$dst)]>; 918 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 919 "mov{q}\t{$src, $dst|$dst, $src}", 920 [(store i64immSExt32:$src, addr:$dst)]>; 921 922 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a 923 /// 32-bit offset from the PC. These are only valid in x86-32 mode. 924 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src), 925 "mov{b}\t{$src, %al|AL, $src}", []>, 926 Requires<[In32BitMode]>; 927 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src), 928 "mov{w}\t{$src, %ax|AL, $src}", []>, OpSize, 929 Requires<[In32BitMode]>; 930 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), 931 "mov{l}\t{$src, %eax|EAX, $src}", []>, 932 Requires<[In32BitMode]>; 933 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins), 934 "mov{b}\t{%al, $dst|$dst, AL}", []>, 935 Requires<[In32BitMode]>; 936 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins), 937 "mov{w}\t{%ax, $dst|$dst, AL}", []>, OpSize, 938 Requires<[In32BitMode]>; 939 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins), 940 "mov{l}\t{%eax, $dst|$dst, EAX}", []>, 941 Requires<[In32BitMode]>; 942 943 // FIXME: These definitions are utterly broken 944 // Just leave them commented out for now because they're useless outside 945 // of the large code model, and most compilers won't generate the instructions 946 // in question. 947 /* 948 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src), 949 "mov{q}\t{$src, %rax|RAX, $src}", []>; 950 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src), 951 "mov{q}\t{$src, %rax|RAX, $src}", []>; 952 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins), 953 "mov{q}\t{%rax, $dst|$dst, RAX}", []>; 954 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins), 955 "mov{q}\t{%rax, $dst|$dst, RAX}", []>; 956 */ 957 958 959 let isCodeGenOnly = 1 in { 960 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 961 "mov{b}\t{$src, $dst|$dst, $src}", []>; 962 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 963 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; 964 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 965 "mov{l}\t{$src, $dst|$dst, $src}", []>; 966 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 967 "mov{q}\t{$src, $dst|$dst, $src}", []>; 968 } 969 970 let canFoldAsLoad = 1, isReMaterializable = 1 in { 971 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 972 "mov{b}\t{$src, $dst|$dst, $src}", 973 [(set GR8:$dst, (loadi8 addr:$src))]>; 974 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 975 "mov{w}\t{$src, $dst|$dst, $src}", 976 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize; 977 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 978 "mov{l}\t{$src, $dst|$dst, $src}", 979 [(set GR32:$dst, (loadi32 addr:$src))]>; 980 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 981 "mov{q}\t{$src, $dst|$dst, $src}", 982 [(set GR64:$dst, (load addr:$src))]>; 983 } 984 985 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 986 "mov{b}\t{$src, $dst|$dst, $src}", 987 [(store GR8:$src, addr:$dst)]>; 988 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 989 "mov{w}\t{$src, $dst|$dst, $src}", 990 [(store GR16:$src, addr:$dst)]>, OpSize; 991 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 992 "mov{l}\t{$src, $dst|$dst, $src}", 993 [(store GR32:$src, addr:$dst)]>; 994 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 995 "mov{q}\t{$src, $dst|$dst, $src}", 996 [(store GR64:$src, addr:$dst)]>; 997 998 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 999 // that they can be used for copying and storing h registers, which can't be 1000 // encoded when a REX prefix is present. 1001 let isCodeGenOnly = 1 in { 1002 let neverHasSideEffects = 1 in 1003 def MOV8rr_NOREX : I<0x88, MRMDestReg, 1004 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1005 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; 1006 let mayStore = 1 in 1007 def MOV8mr_NOREX : I<0x88, MRMDestMem, 1008 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1009 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; 1010 let mayLoad = 1, neverHasSideEffects = 1, 1011 canFoldAsLoad = 1, isReMaterializable = 1 in 1012 def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1013 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1014 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; 1015 } 1016 1017 1018 // Condition code ops, incl. set if equal/not equal/... 1019 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in 1020 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH 1021 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in 1022 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags 1023 1024 1025 //===----------------------------------------------------------------------===// 1026 // Bit tests instructions: BT, BTS, BTR, BTC. 1027 1028 let Defs = [EFLAGS] in { 1029 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1030 "bt{w}\t{$src2, $src1|$src1, $src2}", 1031 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB; 1032 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1033 "bt{l}\t{$src2, $src1|$src1, $src2}", 1034 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB; 1035 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1036 "bt{q}\t{$src2, $src1|$src1, $src2}", 1037 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB; 1038 1039 // Unlike with the register+register form, the memory+register form of the 1040 // bt instruction does not ignore the high bits of the index. From ISel's 1041 // perspective, this is pretty bizarre. Make these instructions disassembly 1042 // only for now. 1043 1044 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1045 "bt{w}\t{$src2, $src1|$src1, $src2}", 1046 // [(X86bt (loadi16 addr:$src1), GR16:$src2), 1047 // (implicit EFLAGS)] 1048 [] 1049 >, OpSize, TB, Requires<[FastBTMem]>; 1050 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1051 "bt{l}\t{$src2, $src1|$src1, $src2}", 1052 // [(X86bt (loadi32 addr:$src1), GR32:$src2), 1053 // (implicit EFLAGS)] 1054 [] 1055 >, TB, Requires<[FastBTMem]>; 1056 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1057 "bt{q}\t{$src2, $src1|$src1, $src2}", 1058 // [(X86bt (loadi64 addr:$src1), GR64:$src2), 1059 // (implicit EFLAGS)] 1060 [] 1061 >, TB; 1062 1063 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1064 "bt{w}\t{$src2, $src1|$src1, $src2}", 1065 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>, 1066 OpSize, TB; 1067 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1068 "bt{l}\t{$src2, $src1|$src1, $src2}", 1069 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB; 1070 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1071 "bt{q}\t{$src2, $src1|$src1, $src2}", 1072 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB; 1073 1074 // Note that these instructions don't need FastBTMem because that 1075 // only applies when the other operand is in a register. When it's 1076 // an immediate, bt is still fast. 1077 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1078 "bt{w}\t{$src2, $src1|$src1, $src2}", 1079 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) 1080 ]>, OpSize, TB; 1081 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1082 "bt{l}\t{$src2, $src1|$src1, $src2}", 1083 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) 1084 ]>, TB; 1085 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1086 "bt{q}\t{$src2, $src1|$src1, $src2}", 1087 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1088 i64immSExt8:$src2))]>, TB; 1089 1090 1091 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1092 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1093 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1094 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1095 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1096 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1097 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1098 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1099 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1100 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1101 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1102 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1103 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1104 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1105 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1106 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1107 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1108 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1109 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1110 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1111 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1112 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1113 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1114 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1115 1116 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1117 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1118 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1119 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1120 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1121 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1122 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1123 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1124 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1125 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1126 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1127 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1128 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1129 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1130 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1131 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1132 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1133 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1134 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1135 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1136 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1137 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1138 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1139 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1140 1141 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1142 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1143 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1144 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1145 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1146 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1147 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1148 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1149 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1150 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1151 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1152 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1153 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1154 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1155 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1156 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1157 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1158 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1159 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1160 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1161 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1162 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1163 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1164 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1165 } // Defs = [EFLAGS] 1166 1167 1168 //===----------------------------------------------------------------------===// 1169 // Atomic support 1170 // 1171 1172 1173 // Atomic swap. These are just normal xchg instructions. But since a memory 1174 // operand is referenced, the atomicity is ensured. 1175 let Constraints = "$val = $dst" in { 1176 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), 1177 "xchg{b}\t{$val, $ptr|$ptr, $val}", 1178 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>; 1179 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr), 1180 "xchg{w}\t{$val, $ptr|$ptr, $val}", 1181 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, 1182 OpSize; 1183 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr), 1184 "xchg{l}\t{$val, $ptr|$ptr, $val}", 1185 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>; 1186 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr), 1187 "xchg{q}\t{$val, $ptr|$ptr, $val}", 1188 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>; 1189 1190 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), 1191 "xchg{b}\t{$val, $src|$src, $val}", []>; 1192 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), 1193 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize; 1194 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), 1195 "xchg{l}\t{$val, $src|$src, $val}", []>; 1196 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), 1197 "xchg{q}\t{$val, $src|$src, $val}", []>; 1198 } 1199 1200 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), 1201 "xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize; 1202 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), 1203 "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In32BitMode]>; 1204 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding. 1205 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP. 1206 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src), 1207 "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In64BitMode]>; 1208 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), 1209 "xchg{q}\t{$src, %rax|RAX, $src}", []>; 1210 1211 1212 1213 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1214 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; 1215 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1216 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; 1217 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1218 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB; 1219 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1220 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB; 1221 1222 let mayLoad = 1, mayStore = 1 in { 1223 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1224 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; 1225 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1226 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; 1227 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1228 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB; 1229 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1230 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB; 1231 1232 } 1233 1234 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1235 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; 1236 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1237 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; 1238 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1239 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB; 1240 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1241 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; 1242 1243 let mayLoad = 1, mayStore = 1 in { 1244 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1245 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; 1246 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1247 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; 1248 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1249 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB; 1250 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1251 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; 1252 } 1253 1254 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 1255 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 1256 "cmpxchg8b\t$dst", []>, TB; 1257 1258 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 1259 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 1260 "cmpxchg16b\t$dst", []>, TB, Requires<[HasCmpxchg16b]>; 1261 1262 1263 1264 // Lock instruction prefix 1265 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; 1266 1267 // Rex64 instruction prefix 1268 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>; 1269 1270 // Data16 instruction prefix 1271 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; 1272 1273 // Repeat string operation instruction prefixes 1274 // These uses the DF flag in the EFLAGS register to inc or dec ECX 1275 let Defs = [ECX], Uses = [ECX,EFLAGS] in { 1276 // Repeat (used with INS, OUTS, MOVS, LODS and STOS) 1277 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; 1278 // Repeat while not equal (used with CMPS and SCAS) 1279 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; 1280 } 1281 1282 1283 // String manipulation instructions 1284 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>; 1285 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize; 1286 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>; 1287 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>; 1288 1289 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>; 1290 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize; 1291 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>; 1292 1293 1294 // Flag instructions 1295 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; 1296 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; 1297 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>; 1298 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>; 1299 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; 1300 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; 1301 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; 1302 1303 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB; 1304 1305 // Table lookup instructions 1306 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>; 1307 1308 // ASCII Adjust After Addition 1309 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1310 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>; 1311 1312 // ASCII Adjust AX Before Division 1313 // sets AL, AH and EFLAGS and uses AL and AH 1314 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 1315 "aad\t$src", []>, Requires<[In32BitMode]>; 1316 1317 // ASCII Adjust AX After Multiply 1318 // sets AL, AH and EFLAGS and uses AL 1319 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 1320 "aam\t$src", []>, Requires<[In32BitMode]>; 1321 1322 // ASCII Adjust AL After Subtraction - sets 1323 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1324 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>; 1325 1326 // Decimal Adjust AL after Addition 1327 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1328 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>; 1329 1330 // Decimal Adjust AL after Subtraction 1331 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1332 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>; 1333 1334 // Check Array Index Against Bounds 1335 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1336 "bound\t{$src, $dst|$dst, $src}", []>, OpSize, 1337 Requires<[In32BitMode]>; 1338 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1339 "bound\t{$src, $dst|$dst, $src}", []>, 1340 Requires<[In32BitMode]>; 1341 1342 // Adjust RPL Field of Segment Selector 1343 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst), 1344 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>; 1345 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst), 1346 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>; 1347 1348 //===----------------------------------------------------------------------===// 1349 // MOVBE Instructions 1350 // 1351 let Predicates = [HasMOVBE] in { 1352 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1353 "movbe{w}\t{$src, $dst|$dst, $src}", 1354 [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, OpSize, T8; 1355 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1356 "movbe{l}\t{$src, $dst|$dst, $src}", 1357 [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, T8; 1358 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1359 "movbe{q}\t{$src, $dst|$dst, $src}", 1360 [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, T8; 1361 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1362 "movbe{w}\t{$src, $dst|$dst, $src}", 1363 [(store (bswap GR16:$src), addr:$dst)]>, OpSize, T8; 1364 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1365 "movbe{l}\t{$src, $dst|$dst, $src}", 1366 [(store (bswap GR32:$src), addr:$dst)]>, T8; 1367 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1368 "movbe{q}\t{$src, $dst|$dst, $src}", 1369 [(store (bswap GR64:$src), addr:$dst)]>, T8; 1370 } 1371 1372 //===----------------------------------------------------------------------===// 1373 // RDRAND Instruction 1374 // 1375 let Predicates = [HasRDRAND], Defs = [EFLAGS] in { 1376 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 1377 "rdrand{w}\t$dst", []>, OpSize, TB; 1378 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 1379 "rdrand{l}\t$dst", []>, TB; 1380 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 1381 "rdrand{q}\t$dst", []>, TB; 1382 } 1383 1384 //===----------------------------------------------------------------------===// 1385 // LZCNT Instruction 1386 // 1387 let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 1388 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1389 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1390 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS, 1391 OpSize; 1392 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1393 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1394 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 1395 (implicit EFLAGS)]>, XS, OpSize; 1396 1397 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1398 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1399 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS; 1400 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1401 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1402 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 1403 (implicit EFLAGS)]>, XS; 1404 1405 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1406 "lzcnt{q}\t{$src, $dst|$dst, $src}", 1407 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 1408 XS; 1409 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1410 "lzcnt{q}\t{$src, $dst|$dst, $src}", 1411 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 1412 (implicit EFLAGS)]>, XS; 1413 } 1414 1415 //===----------------------------------------------------------------------===// 1416 // BMI Instructions 1417 // 1418 let Predicates = [HasBMI], Defs = [EFLAGS] in { 1419 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1420 "tzcnt{w}\t{$src, $dst|$dst, $src}", 1421 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS, 1422 OpSize; 1423 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1424 "tzcnt{w}\t{$src, $dst|$dst, $src}", 1425 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 1426 (implicit EFLAGS)]>, XS, OpSize; 1427 1428 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1429 "tzcnt{l}\t{$src, $dst|$dst, $src}", 1430 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS; 1431 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1432 "tzcnt{l}\t{$src, $dst|$dst, $src}", 1433 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 1434 (implicit EFLAGS)]>, XS; 1435 1436 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1437 "tzcnt{q}\t{$src, $dst|$dst, $src}", 1438 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 1439 XS; 1440 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1441 "tzcnt{q}\t{$src, $dst|$dst, $src}", 1442 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 1443 (implicit EFLAGS)]>, XS; 1444 } 1445 1446 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 1447 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode, 1448 PatFrag ld_frag> { 1449 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 1450 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 1451 [(set RC:$dst, EFLAGS, (OpNode RC:$src))]>, T8, VEX_4V; 1452 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 1453 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 1454 [(set RC:$dst, EFLAGS, (OpNode (ld_frag addr:$src)))]>, 1455 T8, VEX_4V; 1456 } 1457 1458 let Predicates = [HasBMI], Defs = [EFLAGS] in { 1459 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, 1460 X86blsr_flag, loadi32>; 1461 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, 1462 X86blsr_flag, loadi64>, VEX_W; 1463 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, 1464 X86blsmsk_flag, loadi32>; 1465 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, 1466 X86blsmsk_flag, loadi64>, VEX_W; 1467 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, 1468 X86blsi_flag, loadi32>; 1469 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, 1470 X86blsi_flag, loadi64>, VEX_W; 1471 } 1472 1473 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 1474 X86MemOperand x86memop, Intrinsic Int, 1475 PatFrag ld_frag> { 1476 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 1477 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1478 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 1479 T8, VEX_4VOp3; 1480 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 1481 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1482 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 1483 (implicit EFLAGS)]>, T8, VEX_4VOp3; 1484 } 1485 1486 let Predicates = [HasBMI], Defs = [EFLAGS] in { 1487 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem, 1488 int_x86_bmi_bextr_32, loadi32>; 1489 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem, 1490 int_x86_bmi_bextr_64, loadi64>, VEX_W; 1491 } 1492 1493 let Predicates = [HasBMI2], Defs = [EFLAGS] in { 1494 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 1495 int_x86_bmi_bzhi_32, loadi32>; 1496 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 1497 int_x86_bmi_bzhi_64, loadi64>, VEX_W; 1498 } 1499 1500 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 1501 X86MemOperand x86memop, Intrinsic Int, 1502 PatFrag ld_frag> { 1503 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 1504 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1505 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, 1506 VEX_4V; 1507 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 1508 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1509 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V; 1510 } 1511 1512 let Predicates = [HasBMI2] in { 1513 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 1514 int_x86_bmi_pdep_32, loadi32>, T8XD; 1515 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 1516 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; 1517 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 1518 int_x86_bmi_pext_32, loadi32>, T8XS; 1519 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 1520 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; 1521 } 1522 1523 //===----------------------------------------------------------------------===// 1524 // Subsystems. 1525 //===----------------------------------------------------------------------===// 1526 1527 include "X86InstrArithmetic.td" 1528 include "X86InstrCMovSetCC.td" 1529 include "X86InstrExtension.td" 1530 include "X86InstrControl.td" 1531 include "X86InstrShiftRotate.td" 1532 1533 // X87 Floating Point Stack. 1534 include "X86InstrFPStack.td" 1535 1536 // SIMD support (SSE, MMX and AVX) 1537 include "X86InstrFragmentsSIMD.td" 1538 1539 // FMA - Fused Multiply-Add support (requires FMA) 1540 include "X86InstrFMA.td" 1541 1542 // XOP 1543 include "X86InstrXOP.td" 1544 1545 // SSE, MMX and 3DNow! vector support. 1546 include "X86InstrSSE.td" 1547 include "X86InstrMMX.td" 1548 include "X86Instr3DNow.td" 1549 1550 include "X86InstrVMX.td" 1551 include "X86InstrSVM.td" 1552 1553 // System instructions. 1554 include "X86InstrSystem.td" 1555 1556 // Compiler Pseudo Instructions and Pat Patterns 1557 include "X86InstrCompiler.td" 1558 1559 //===----------------------------------------------------------------------===// 1560 // Assembler Mnemonic Aliases 1561 //===----------------------------------------------------------------------===// 1562 1563 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>; 1564 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>; 1565 1566 def : MnemonicAlias<"cbw", "cbtw">; 1567 def : MnemonicAlias<"cwde", "cwtl">; 1568 def : MnemonicAlias<"cwd", "cwtd">; 1569 def : MnemonicAlias<"cdq", "cltd">; 1570 def : MnemonicAlias<"cdqe", "cltq">; 1571 def : MnemonicAlias<"cqo", "cqto">; 1572 1573 // lret maps to lretl, it is not ambiguous with lretq. 1574 def : MnemonicAlias<"lret", "lretl">; 1575 1576 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>; 1577 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>; 1578 1579 def : MnemonicAlias<"loopz", "loope">; 1580 def : MnemonicAlias<"loopnz", "loopne">; 1581 1582 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; 1583 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; 1584 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>; 1585 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>; 1586 def : MnemonicAlias<"popfd", "popfl">; 1587 1588 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 1589 // all modes. However: "push (addr)" and "push $42" should default to 1590 // pushl/pushq depending on the current mode. Similar for "pop %bx" 1591 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>; 1592 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>; 1593 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 1594 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 1595 def : MnemonicAlias<"pushfd", "pushfl">; 1596 1597 def : MnemonicAlias<"repe", "rep">; 1598 def : MnemonicAlias<"repz", "rep">; 1599 def : MnemonicAlias<"repnz", "repne">; 1600 1601 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>; 1602 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>; 1603 1604 def : MnemonicAlias<"salb", "shlb">; 1605 def : MnemonicAlias<"salw", "shlw">; 1606 def : MnemonicAlias<"sall", "shll">; 1607 def : MnemonicAlias<"salq", "shlq">; 1608 1609 def : MnemonicAlias<"smovb", "movsb">; 1610 def : MnemonicAlias<"smovw", "movsw">; 1611 def : MnemonicAlias<"smovl", "movsl">; 1612 def : MnemonicAlias<"smovq", "movsq">; 1613 1614 def : MnemonicAlias<"ud2a", "ud2">; 1615 def : MnemonicAlias<"verrw", "verr">; 1616 1617 // System instruction aliases. 1618 def : MnemonicAlias<"iret", "iretl">; 1619 def : MnemonicAlias<"sysret", "sysretl">; 1620 def : MnemonicAlias<"sysexit", "sysexitl">; 1621 1622 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>; 1623 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>; 1624 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>; 1625 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>; 1626 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>; 1627 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>; 1628 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>; 1629 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>; 1630 1631 1632 // Floating point stack aliases. 1633 def : MnemonicAlias<"fcmovz", "fcmove">; 1634 def : MnemonicAlias<"fcmova", "fcmovnbe">; 1635 def : MnemonicAlias<"fcmovnae", "fcmovb">; 1636 def : MnemonicAlias<"fcmovna", "fcmovbe">; 1637 def : MnemonicAlias<"fcmovae", "fcmovnb">; 1638 def : MnemonicAlias<"fcomip", "fcompi">; 1639 def : MnemonicAlias<"fildq", "fildll">; 1640 def : MnemonicAlias<"fistpq", "fistpll">; 1641 def : MnemonicAlias<"fisttpq", "fisttpll">; 1642 def : MnemonicAlias<"fldcww", "fldcw">; 1643 def : MnemonicAlias<"fnstcww", "fnstcw">; 1644 def : MnemonicAlias<"fnstsww", "fnstsw">; 1645 def : MnemonicAlias<"fucomip", "fucompi">; 1646 def : MnemonicAlias<"fwait", "wait">; 1647 1648 1649 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond> 1650 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 1651 !strconcat(Prefix, NewCond, Suffix)>; 1652 1653 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 1654 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 1655 /// example "setz" -> "sete". 1656 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> { 1657 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb 1658 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete 1659 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe 1660 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae 1661 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae 1662 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle 1663 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge 1664 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne 1665 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp 1666 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp 1667 1668 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb 1669 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta 1670 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl 1671 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg 1672 } 1673 1674 // Aliases for set<CC> 1675 defm : IntegerCondCodeMnemonicAlias<"set", "">; 1676 // Aliases for j<CC> 1677 defm : IntegerCondCodeMnemonicAlias<"j", "">; 1678 // Aliases for cmov<CC>{w,l,q} 1679 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">; 1680 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">; 1681 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">; 1682 1683 1684 //===----------------------------------------------------------------------===// 1685 // Assembler Instruction Aliases 1686 //===----------------------------------------------------------------------===// 1687 1688 // aad/aam default to base 10 if no operand is specified. 1689 def : InstAlias<"aad", (AAD8i8 10)>; 1690 def : InstAlias<"aam", (AAM8i8 10)>; 1691 1692 // Disambiguate the mem/imm form of bt-without-a-suffix as btl. 1693 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>; 1694 1695 // clr aliases. 1696 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>; 1697 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>; 1698 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>; 1699 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; 1700 1701 // div and idiv aliases for explicit A register. 1702 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>; 1703 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>; 1704 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>; 1705 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>; 1706 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>; 1707 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>; 1708 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>; 1709 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>; 1710 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>; 1711 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>; 1712 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>; 1713 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>; 1714 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>; 1715 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>; 1716 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>; 1717 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>; 1718 1719 1720 1721 // Various unary fpstack operations default to operating on on ST1. 1722 // For example, "fxch" -> "fxch %st(1)" 1723 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 1724 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>; 1725 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>; 1726 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>; 1727 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>; 1728 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>; 1729 def : InstAlias<"fxch", (XCH_F ST1)>; 1730 def : InstAlias<"fcomi", (COM_FIr ST1)>; 1731 def : InstAlias<"fcompi", (COM_FIPr ST1)>; 1732 def : InstAlias<"fucom", (UCOM_Fr ST1)>; 1733 def : InstAlias<"fucomp", (UCOM_FPr ST1)>; 1734 def : InstAlias<"fucomi", (UCOM_FIr ST1)>; 1735 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>; 1736 1737 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 1738 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 1739 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 1740 // gas. 1741 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 1742 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"), 1743 (Inst RST:$op), EmitAlias>; 1744 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"), 1745 (Inst ST0), EmitAlias>; 1746 } 1747 1748 defm : FpUnaryAlias<"fadd", ADD_FST0r>; 1749 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 1750 defm : FpUnaryAlias<"fsub", SUB_FST0r>; 1751 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>; 1752 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; 1753 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>; 1754 defm : FpUnaryAlias<"fmul", MUL_FST0r>; 1755 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; 1756 defm : FpUnaryAlias<"fdiv", DIV_FST0r>; 1757 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>; 1758 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; 1759 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>; 1760 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 1761 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 1762 defm : FpUnaryAlias<"fcompi", COM_FIPr>; 1763 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; 1764 1765 1766 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they 1767 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 1768 // solely because gas supports it. 1769 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>; 1770 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>; 1771 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>; 1772 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>; 1773 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>; 1774 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>; 1775 1776 // We accept "fnstsw %eax" even though it only writes %ax. 1777 def : InstAlias<"fnstsw %eax", (FNSTSW8r)>; 1778 def : InstAlias<"fnstsw %al" , (FNSTSW8r)>; 1779 def : InstAlias<"fnstsw" , (FNSTSW8r)>; 1780 1781 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 1782 // this is compatible with what GAS does. 1783 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 1784 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 1785 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>; 1786 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>; 1787 1788 // "imul <imm>, B" is an alias for "imul <imm>, B, B". 1789 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>; 1790 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>; 1791 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>; 1792 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>; 1793 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>; 1794 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>; 1795 1796 // inb %dx -> inb %al, %dx 1797 def : InstAlias<"inb %dx", (IN8rr)>; 1798 def : InstAlias<"inw %dx", (IN16rr)>; 1799 def : InstAlias<"inl %dx", (IN32rr)>; 1800 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>; 1801 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>; 1802 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>; 1803 1804 1805 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 1806 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 1807 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 1808 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>; 1809 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>; 1810 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 1811 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 1812 1813 // Force mov without a suffix with a segment and mem to prefer the 'l' form of 1814 // the move. All segment/mem forms are equivalent, this has the shortest 1815 // encoding. 1816 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>; 1817 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>; 1818 1819 // Match 'movq <largeimm>, <reg>' as an alias for movabsq. 1820 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>; 1821 1822 // Match 'movq GR64, MMX' as an alias for movd. 1823 def : InstAlias<"movq $src, $dst", 1824 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 1825 def : InstAlias<"movq $src, $dst", 1826 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 1827 1828 // movsd with no operands (as opposed to the SSE scalar move of a double) is an 1829 // alias for movsl. (as in rep; movsd) 1830 def : InstAlias<"movsd", (MOVSD)>; 1831 1832 // movsx aliases 1833 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; 1834 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; 1835 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; 1836 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; 1837 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; 1838 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; 1839 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; 1840 1841 // movzx aliases 1842 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; 1843 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; 1844 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; 1845 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; 1846 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; 1847 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; 1848 // Note: No GR32->GR64 movzx form. 1849 1850 // outb %dx -> outb %al, %dx 1851 def : InstAlias<"outb %dx", (OUT8rr)>; 1852 def : InstAlias<"outw %dx", (OUT16rr)>; 1853 def : InstAlias<"outl %dx", (OUT32rr)>; 1854 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>; 1855 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>; 1856 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>; 1857 1858 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 1859 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 1860 // errors, since its encoding is the most compact. 1861 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>; 1862 1863 // shld/shrd op,op -> shld op, op, CL 1864 def : InstAlias<"shldw $r2, $r1", (SHLD16rrCL GR16:$r1, GR16:$r2)>; 1865 def : InstAlias<"shldl $r2, $r1", (SHLD32rrCL GR32:$r1, GR32:$r2)>; 1866 def : InstAlias<"shldq $r2, $r1", (SHLD64rrCL GR64:$r1, GR64:$r2)>; 1867 def : InstAlias<"shrdw $r2, $r1", (SHRD16rrCL GR16:$r1, GR16:$r2)>; 1868 def : InstAlias<"shrdl $r2, $r1", (SHRD32rrCL GR32:$r1, GR32:$r2)>; 1869 def : InstAlias<"shrdq $r2, $r1", (SHRD64rrCL GR64:$r1, GR64:$r2)>; 1870 1871 def : InstAlias<"shldw $reg, $mem", (SHLD16mrCL i16mem:$mem, GR16:$reg)>; 1872 def : InstAlias<"shldl $reg, $mem", (SHLD32mrCL i32mem:$mem, GR32:$reg)>; 1873 def : InstAlias<"shldq $reg, $mem", (SHLD64mrCL i64mem:$mem, GR64:$reg)>; 1874 def : InstAlias<"shrdw $reg, $mem", (SHRD16mrCL i16mem:$mem, GR16:$reg)>; 1875 def : InstAlias<"shrdl $reg, $mem", (SHRD32mrCL i32mem:$mem, GR32:$reg)>; 1876 def : InstAlias<"shrdq $reg, $mem", (SHRD64mrCL i64mem:$mem, GR64:$reg)>; 1877 1878 /* FIXME: This is disabled because the asm matcher is currently incapable of 1879 * matching a fixed immediate like $1. 1880 // "shl X, $1" is an alias for "shl X". 1881 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 1882 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 1883 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 1884 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 1885 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 1886 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 1887 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 1888 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 1889 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 1890 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 1891 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 1892 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 1893 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 1894 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 1895 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 1896 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 1897 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 1898 } 1899 1900 defm : ShiftRotateByOneAlias<"rcl", "RCL">; 1901 defm : ShiftRotateByOneAlias<"rcr", "RCR">; 1902 defm : ShiftRotateByOneAlias<"rol", "ROL">; 1903 defm : ShiftRotateByOneAlias<"ror", "ROR">; 1904 FIXME */ 1905 1906 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 1907 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>; 1908 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>; 1909 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>; 1910 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>; 1911 1912 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 1913 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>; 1914 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>; 1915 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>; 1916 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>; 1917 1918 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 1919 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>; 1920 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>; 1921 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>; 1922 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>; 1923
