1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef LINUX_PCI_REGS_H 20 #define LINUX_PCI_REGS_H 21 #define PCI_VENDOR_ID 0x00 22 #define PCI_DEVICE_ID 0x02 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define PCI_COMMAND 0x04 25 #define PCI_COMMAND_IO 0x1 26 #define PCI_COMMAND_MEMORY 0x2 27 #define PCI_COMMAND_MASTER 0x4 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define PCI_COMMAND_SPECIAL 0x8 30 #define PCI_COMMAND_INVALIDATE 0x10 31 #define PCI_COMMAND_VGA_PALETTE 0x20 32 #define PCI_COMMAND_PARITY 0x40 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define PCI_COMMAND_WAIT 0x80 35 #define PCI_COMMAND_SERR 0x100 36 #define PCI_COMMAND_FAST_BACK 0x200 37 #define PCI_COMMAND_INTX_DISABLE 0x400 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define PCI_STATUS 0x06 40 #define PCI_STATUS_CAP_LIST 0x10 41 #define PCI_STATUS_66MHZ 0x20 42 #define PCI_STATUS_UDF 0x40 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define PCI_STATUS_FAST_BACK 0x80 45 #define PCI_STATUS_PARITY 0x100 46 #define PCI_STATUS_DEVSEL_MASK 0x600 47 #define PCI_STATUS_DEVSEL_FAST 0x000 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 50 #define PCI_STATUS_DEVSEL_SLOW 0x400 51 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 52 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 55 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 56 #define PCI_STATUS_DETECTED_PARITY 0x8000 57 #define PCI_CLASS_REVISION 0x08 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define PCI_REVISION_ID 0x08 60 #define PCI_CLASS_PROG 0x09 61 #define PCI_CLASS_DEVICE 0x0a 62 #define PCI_CACHE_LINE_SIZE 0x0c 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define PCI_LATENCY_TIMER 0x0d 65 #define PCI_HEADER_TYPE 0x0e 66 #define PCI_HEADER_TYPE_NORMAL 0 67 #define PCI_HEADER_TYPE_BRIDGE 1 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define PCI_HEADER_TYPE_CARDBUS 2 70 #define PCI_BIST 0x0f 71 #define PCI_BIST_CODE_MASK 0x0f 72 #define PCI_BIST_START 0x40 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define PCI_BIST_CAPABLE 0x80 75 #define PCI_BASE_ADDRESS_0 0x10 76 #define PCI_BASE_ADDRESS_1 0x14 77 #define PCI_BASE_ADDRESS_2 0x18 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 #define PCI_BASE_ADDRESS_3 0x1c 80 #define PCI_BASE_ADDRESS_4 0x20 81 #define PCI_BASE_ADDRESS_5 0x24 82 #define PCI_BASE_ADDRESS_SPACE 0x01 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 85 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 86 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 87 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 90 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 91 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 92 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 95 #define PCI_CARDBUS_CIS 0x28 96 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 97 #define PCI_SUBSYSTEM_ID 0x2e 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 #define PCI_ROM_ADDRESS 0x30 100 #define PCI_ROM_ADDRESS_ENABLE 0x01 101 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 102 #define PCI_CAPABILITY_LIST 0x34 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 #define PCI_INTERRUPT_LINE 0x3c 105 #define PCI_INTERRUPT_PIN 0x3d 106 #define PCI_MIN_GNT 0x3e 107 #define PCI_MAX_LAT 0x3f 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 #define PCI_PRIMARY_BUS 0x18 110 #define PCI_SECONDARY_BUS 0x19 111 #define PCI_SUBORDINATE_BUS 0x1a 112 #define PCI_SEC_LATENCY_TIMER 0x1b 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 #define PCI_IO_BASE 0x1c 115 #define PCI_IO_LIMIT 0x1d 116 #define PCI_IO_RANGE_TYPE_MASK 0x0fUL 117 #define PCI_IO_RANGE_TYPE_16 0x00 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 #define PCI_IO_RANGE_TYPE_32 0x01 120 #define PCI_IO_RANGE_MASK (~0x0fUL) 121 #define PCI_SEC_STATUS 0x1e 122 #define PCI_MEMORY_BASE 0x20 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define PCI_MEMORY_LIMIT 0x22 125 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 126 #define PCI_MEMORY_RANGE_MASK (~0x0fUL) 127 #define PCI_PREF_MEMORY_BASE 0x24 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 #define PCI_PREF_MEMORY_LIMIT 0x26 130 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 131 #define PCI_PREF_RANGE_TYPE_32 0x00 132 #define PCI_PREF_RANGE_TYPE_64 0x01 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 #define PCI_PREF_RANGE_MASK (~0x0fUL) 135 #define PCI_PREF_BASE_UPPER32 0x28 136 #define PCI_PREF_LIMIT_UPPER32 0x2c 137 #define PCI_IO_BASE_UPPER16 0x30 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 #define PCI_IO_LIMIT_UPPER16 0x32 140 #define PCI_ROM_ADDRESS1 0x38 141 #define PCI_BRIDGE_CONTROL 0x3e 142 #define PCI_BRIDGE_CTL_PARITY 0x01 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 #define PCI_BRIDGE_CTL_SERR 0x02 145 #define PCI_BRIDGE_CTL_NO_ISA 0x04 146 #define PCI_BRIDGE_CTL_VGA 0x08 147 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 150 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 151 #define PCI_CB_CAPABILITY_LIST 0x14 152 #define PCI_CB_SEC_STATUS 0x16 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 #define PCI_CB_PRIMARY_BUS 0x18 155 #define PCI_CB_CARD_BUS 0x19 156 #define PCI_CB_SUBORDINATE_BUS 0x1a 157 #define PCI_CB_LATENCY_TIMER 0x1b 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 #define PCI_CB_MEMORY_BASE_0 0x1c 160 #define PCI_CB_MEMORY_LIMIT_0 0x20 161 #define PCI_CB_MEMORY_BASE_1 0x24 162 #define PCI_CB_MEMORY_LIMIT_1 0x28 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 #define PCI_CB_IO_BASE_0 0x2c 165 #define PCI_CB_IO_BASE_0_HI 0x2e 166 #define PCI_CB_IO_LIMIT_0 0x30 167 #define PCI_CB_IO_LIMIT_0_HI 0x32 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 #define PCI_CB_IO_BASE_1 0x34 170 #define PCI_CB_IO_BASE_1_HI 0x36 171 #define PCI_CB_IO_LIMIT_1 0x38 172 #define PCI_CB_IO_LIMIT_1_HI 0x3a 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 #define PCI_CB_IO_RANGE_MASK (~0x03UL) 175 #define PCI_CB_BRIDGE_CONTROL 0x3e 176 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 177 #define PCI_CB_BRIDGE_CTL_SERR 0x02 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 #define PCI_CB_BRIDGE_CTL_ISA 0x04 180 #define PCI_CB_BRIDGE_CTL_VGA 0x08 181 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 182 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 185 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 186 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 187 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 190 #define PCI_CB_SUBSYSTEM_ID 0x42 191 #define PCI_CB_LEGACY_MODE_BASE 0x44 192 #define PCI_CAP_LIST_ID 0 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 #define PCI_CAP_ID_PM 0x01 195 #define PCI_CAP_ID_AGP 0x02 196 #define PCI_CAP_ID_VPD 0x03 197 #define PCI_CAP_ID_SLOTID 0x04 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 #define PCI_CAP_ID_MSI 0x05 200 #define PCI_CAP_ID_CHSWP 0x06 201 #define PCI_CAP_ID_PCIX 0x07 202 #define PCI_CAP_ID_HT_IRQCONF 0x08 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 #define PCI_CAP_ID_VNDR 0x09 205 #define PCI_CAP_ID_SHPC 0x0C 206 #define PCI_CAP_ID_EXP 0x10 207 #define PCI_CAP_ID_MSIX 0x11 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 #define PCI_CAP_LIST_NEXT 1 210 #define PCI_CAP_FLAGS 2 211 #define PCI_CAP_SIZEOF 4 212 #define PCI_PM_PMC 2 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 #define PCI_PM_CAP_VER_MASK 0x0007 215 #define PCI_PM_CAP_PME_CLOCK 0x0008 216 #define PCI_PM_CAP_RESERVED 0x0010 217 #define PCI_PM_CAP_DSI 0x0020 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 #define PCI_PM_CAP_AUX_POWER 0x01C0 220 #define PCI_PM_CAP_D1 0x0200 221 #define PCI_PM_CAP_D2 0x0400 222 #define PCI_PM_CAP_PME 0x0800 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 #define PCI_PM_CAP_PME_MASK 0xF800 225 #define PCI_PM_CAP_PME_D0 0x0800 226 #define PCI_PM_CAP_PME_D1 0x1000 227 #define PCI_PM_CAP_PME_D2 0x2000 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define PCI_PM_CAP_PME_D3 0x4000 230 #define PCI_PM_CAP_PME_D3cold 0x8000 231 #define PCI_PM_CTRL 4 232 #define PCI_PM_CTRL_STATE_MASK 0x0003 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 235 #define PCI_PM_CTRL_PME_ENABLE 0x0100 236 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 237 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 #define PCI_PM_CTRL_PME_STATUS 0x8000 240 #define PCI_PM_PPB_EXTENSIONS 6 241 #define PCI_PM_PPB_B2_B3 0x40 242 #define PCI_PM_BPCC_ENABLE 0x80 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 #define PCI_PM_DATA_REGISTER 7 245 #define PCI_PM_SIZEOF 8 246 #define PCI_AGP_VERSION 2 247 #define PCI_AGP_RFU 3 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 #define PCI_AGP_STATUS 4 250 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 251 #define PCI_AGP_STATUS_SBA 0x0200 252 #define PCI_AGP_STATUS_64BIT 0x0020 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 #define PCI_AGP_STATUS_FW 0x0010 255 #define PCI_AGP_STATUS_RATE4 0x0004 256 #define PCI_AGP_STATUS_RATE2 0x0002 257 #define PCI_AGP_STATUS_RATE1 0x0001 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 #define PCI_AGP_COMMAND 8 260 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 261 #define PCI_AGP_COMMAND_SBA 0x0200 262 #define PCI_AGP_COMMAND_AGP 0x0100 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 #define PCI_AGP_COMMAND_64BIT 0x0020 265 #define PCI_AGP_COMMAND_FW 0x0010 266 #define PCI_AGP_COMMAND_RATE4 0x0004 267 #define PCI_AGP_COMMAND_RATE2 0x0002 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 #define PCI_AGP_COMMAND_RATE1 0x0001 270 #define PCI_AGP_SIZEOF 12 271 #define PCI_VPD_ADDR 2 272 #define PCI_VPD_ADDR_MASK 0x7fff 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 #define PCI_VPD_ADDR_F 0x8000 275 #define PCI_VPD_DATA 4 276 #define PCI_SID_ESR 2 277 #define PCI_SID_ESR_NSLOTS 0x1f 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 #define PCI_SID_ESR_FIC 0x20 280 #define PCI_SID_CHASSIS_NR 3 281 #define PCI_MSI_FLAGS 2 282 #define PCI_MSI_FLAGS_64BIT 0x80 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 #define PCI_MSI_FLAGS_QSIZE 0x70 285 #define PCI_MSI_FLAGS_QMASK 0x0e 286 #define PCI_MSI_FLAGS_ENABLE 0x01 287 #define PCI_MSI_FLAGS_MASKBIT 0x100 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 #define PCI_MSI_RFU 3 290 #define PCI_MSI_ADDRESS_LO 4 291 #define PCI_MSI_ADDRESS_HI 8 292 #define PCI_MSI_DATA_32 8 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 #define PCI_MSI_DATA_64 12 295 #define PCI_MSI_MASK_BIT 16 296 #define PCI_CHSWP_CSR 2 297 #define PCI_CHSWP_DHA 0x01 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 #define PCI_CHSWP_EIM 0x02 300 #define PCI_CHSWP_PIE 0x04 301 #define PCI_CHSWP_LOO 0x08 302 #define PCI_CHSWP_PI 0x30 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 #define PCI_CHSWP_EXT 0x40 305 #define PCI_CHSWP_INS 0x80 306 #define PCI_X_CMD 2 307 #define PCI_X_CMD_DPERR_E 0x0001 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 #define PCI_X_CMD_ERO 0x0002 310 #define PCI_X_CMD_MAX_READ 0x000c 311 #define PCI_X_CMD_MAX_SPLIT 0x0070 312 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 #define PCI_X_STATUS 4 315 #define PCI_X_STATUS_DEVFN 0x000000ff 316 #define PCI_X_STATUS_BUS 0x0000ff00 317 #define PCI_X_STATUS_64BIT 0x00010000 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 #define PCI_X_STATUS_133MHZ 0x00020000 320 #define PCI_X_STATUS_SPL_DISC 0x00040000 321 #define PCI_X_STATUS_UNX_SPL 0x00080000 322 #define PCI_X_STATUS_COMPLEX 0x00100000 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 #define PCI_X_STATUS_MAX_READ 0x00600000 325 #define PCI_X_STATUS_MAX_SPLIT 0x03800000 326 #define PCI_X_STATUS_MAX_CUM 0x1c000000 327 #define PCI_X_STATUS_SPL_ERR 0x20000000 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 #define PCI_X_STATUS_266MHZ 0x40000000 330 #define PCI_X_STATUS_533MHZ 0x80000000 331 #define PCI_EXP_FLAGS 2 332 #define PCI_EXP_FLAGS_VERS 0x000f 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 #define PCI_EXP_FLAGS_TYPE 0x00f0 335 #define PCI_EXP_TYPE_ENDPOINT 0x0 336 #define PCI_EXP_TYPE_LEG_END 0x1 337 #define PCI_EXP_TYPE_ROOT_PORT 0x4 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 #define PCI_EXP_TYPE_UPSTREAM 0x5 340 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 341 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 342 #define PCI_EXP_FLAGS_SLOT 0x0100 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 #define PCI_EXP_FLAGS_IRQ 0x3e00 345 #define PCI_EXP_DEVCAP 4 346 #define PCI_EXP_DEVCAP_PAYLOAD 0x07 347 #define PCI_EXP_DEVCAP_PHANTOM 0x18 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 #define PCI_EXP_DEVCAP_EXT_TAG 0x20 350 #define PCI_EXP_DEVCAP_L0S 0x1c0 351 #define PCI_EXP_DEVCAP_L1 0xe00 352 #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 #define PCI_EXP_DEVCAP_ATN_IND 0x2000 355 #define PCI_EXP_DEVCAP_PWR_IND 0x4000 356 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 357 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 #define PCI_EXP_DEVCTL 8 360 #define PCI_EXP_DEVCTL_CERE 0x0001 361 #define PCI_EXP_DEVCTL_NFERE 0x0002 362 #define PCI_EXP_DEVCTL_FERE 0x0004 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 #define PCI_EXP_DEVCTL_URRE 0x0008 365 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 366 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 367 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 #define PCI_EXP_DEVCTL_PHANTOM 0x0200 370 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 371 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 372 #define PCI_EXP_DEVCTL_READRQ 0x7000 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 #define PCI_EXP_DEVSTA 10 375 #define PCI_EXP_DEVSTA_CED 0x01 376 #define PCI_EXP_DEVSTA_NFED 0x02 377 #define PCI_EXP_DEVSTA_FED 0x04 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 #define PCI_EXP_DEVSTA_URD 0x08 380 #define PCI_EXP_DEVSTA_AUXPD 0x10 381 #define PCI_EXP_DEVSTA_TRPND 0x20 382 #define PCI_EXP_LNKCAP 12 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 #define PCI_EXP_LNKCTL 16 385 #define PCI_EXP_LNKSTA 18 386 #define PCI_EXP_SLTCAP 20 387 #define PCI_EXP_SLTCTL 24 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 #define PCI_EXP_SLTSTA 26 390 #define PCI_EXP_RTCTL 28 391 #define PCI_EXP_RTCTL_SECEE 0x01 392 #define PCI_EXP_RTCTL_SENFEE 0x02 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 #define PCI_EXP_RTCTL_SEFEE 0x04 395 #define PCI_EXP_RTCTL_PMEIE 0x08 396 #define PCI_EXP_RTCTL_CRSSVE 0x10 397 #define PCI_EXP_RTCAP 30 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 #define PCI_EXP_RTSTA 32 400 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 401 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 402 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 #define PCI_EXT_CAP_ID_ERR 1 405 #define PCI_EXT_CAP_ID_VC 2 406 #define PCI_EXT_CAP_ID_DSN 3 407 #define PCI_EXT_CAP_ID_PWR 4 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 #define PCI_ERR_UNCOR_STATUS 4 410 #define PCI_ERR_UNC_TRAIN 0x00000001 411 #define PCI_ERR_UNC_DLP 0x00000010 412 #define PCI_ERR_UNC_POISON_TLP 0x00001000 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 #define PCI_ERR_UNC_FCP 0x00002000 415 #define PCI_ERR_UNC_COMP_TIME 0x00004000 416 #define PCI_ERR_UNC_COMP_ABORT 0x00008000 417 #define PCI_ERR_UNC_UNX_COMP 0x00010000 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 #define PCI_ERR_UNC_RX_OVER 0x00020000 420 #define PCI_ERR_UNC_MALF_TLP 0x00040000 421 #define PCI_ERR_UNC_ECRC 0x00080000 422 #define PCI_ERR_UNC_UNSUP 0x00100000 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 #define PCI_ERR_UNCOR_MASK 8 425 #define PCI_ERR_UNCOR_SEVER 12 426 #define PCI_ERR_COR_STATUS 16 427 #define PCI_ERR_COR_RCVR 0x00000001 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 #define PCI_ERR_COR_BAD_TLP 0x00000040 430 #define PCI_ERR_COR_BAD_DLLP 0x00000080 431 #define PCI_ERR_COR_REP_ROLL 0x00000100 432 #define PCI_ERR_COR_REP_TIMER 0x00001000 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 #define PCI_ERR_COR_MASK 20 435 #define PCI_ERR_CAP 24 436 #define PCI_ERR_CAP_FEP(x) ((x) & 31) 437 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 440 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 441 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 442 #define PCI_ERR_HEADER_LOG 28 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 #define PCI_ERR_ROOT_COMMAND 44 445 #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 446 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 447 #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 #define PCI_ERR_ROOT_STATUS 48 450 #define PCI_ERR_ROOT_COR_RCV 0x00000001 451 #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 452 #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 455 #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 456 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 457 #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 #define PCI_ERR_ROOT_COR_SRC 52 460 #define PCI_ERR_ROOT_SRC 54 461 #define PCI_VC_PORT_REG1 4 462 #define PCI_VC_PORT_REG2 8 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 #define PCI_VC_PORT_CTRL 12 465 #define PCI_VC_PORT_STATUS 14 466 #define PCI_VC_RES_CAP 16 467 #define PCI_VC_RES_CTRL 20 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 #define PCI_VC_RES_STATUS 26 470 #define PCI_PWR_DSR 4 471 #define PCI_PWR_DATA 8 472 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 475 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 476 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 477 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 480 #define PCI_PWR_CAP 12 481 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 482 #endif 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484
