1 %default {"preinstr":"", "result0":"r0", "result1":"r1", "chkzero":"0"} 2 /* 3 * Generic 64-bit binary operation. Provide an "instr" line that 4 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5 * This could be an ARM instruction or a function call. (If the result 6 * comes back in a register other than r0, you can override "result".) 7 * 8 * If "chkzero" is set to 1, we perform a divide-by-zero check on 9 * vCC (r1). Useful for integer division and modulus. 10 * 11 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 12 * xor-long, add-double, sub-double, mul-double, div-double, 13 * rem-double 14 * 15 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 16 */ 17 /* binop vAA, vBB, vCC */ 18 FETCH(r0, 1) @ r0<- CCBB 19 mov r9, rINST, lsr #8 @ r9<- AA 20 and r2, r0, #255 @ r2<- BB 21 mov r3, r0, lsr #8 @ r3<- CC 22 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 23 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 24 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 25 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 26 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 27 .if $chkzero 28 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 29 beq common_errDivideByZero 30 .endif 31 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 32 33 $preinstr @ optional op; may set condition codes 34 $instr @ result<- op, r0-r3 changed 35 GET_INST_OPCODE(ip) @ extract opcode from rINST 36 stmia r9, {$result0,$result1} @ vAA/vAA+1<- $result0/$result1 37 GOTO_OPCODE(ip) @ jump to next instruction 38 /* 14-17 instructions */ 39
