1 // RUN: %clang -target mipsel-unknown-linux -ccc-clang-archs mipsel -S -o - -emit-llvm %s 2 3 // This checks that the frontend will accept inline asm constraints 4 // c', 'l' and 'x'. Semantic checking will happen in the 5 // llvm backend. Any bad constraint letters will cause the frontend to 6 // error out. 7 8 int main() 9 { 10 // 'c': 16 bit address register for Mips16, GPR for all others 11 // I am using 'c' to constrain both the target and one of the source 12 // registers. We are looking for syntactical correctness. 13 int __s, __v = 17; 14 int __t; 15 __asm__ __volatile__( 16 "addi %0,%1,%2 \n\t\t" 17 : "=c" (__t) 18 : "c" (__s), "I" (__v)); 19 20 // 'l': lo register 21 // We are making it clear that destination register is lo with the 22 // use of the 'l' constraint ("=l"). 23 int i_temp = 44; 24 int i_result; 25 __asm__ __volatile__( 26 "mtlo %1 \n\t\t" 27 : "=l" (i_result) 28 : "r" (i_temp) 29 : "lo"); 30 31 // 'x': Combined lo/hi registers 32 // We are specifying that destination registers are the hi/lo pair with the 33 // use of the 'x' constraint ("=x"). 34 int i_hi = 3; 35 int i_lo = 2; 36 long long ll_result = 0; 37 __asm__ __volatile__( 38 "mthi %1 \n\t\t" 39 "mtlo %2 \n\t\t" 40 : "=x" (ll_result) 41 : "r" (i_hi), "r" (i_lo) 42 : ); 43 return 0; 44 } 45
