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      1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the ARM implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "ARMInstrInfo.h"
     15 #include "ARM.h"
     16 #include "ARMMachineFunctionInfo.h"
     17 #include "MCTargetDesc/ARMAddressingModes.h"
     18 #include "llvm/ADT/STLExtras.h"
     19 #include "llvm/CodeGen/LiveVariables.h"
     20 #include "llvm/CodeGen/MachineFrameInfo.h"
     21 #include "llvm/CodeGen/MachineInstrBuilder.h"
     22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
     23 #include "llvm/MC/MCAsmInfo.h"
     24 #include "llvm/MC/MCInst.h"
     25 using namespace llvm;
     26 
     27 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
     28   : ARMBaseInstrInfo(STI), RI(*this, STI) {
     29 }
     30 
     31 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
     32 void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
     33   if (hasNOP()) {
     34     NopInst.setOpcode(ARM::NOP);
     35     NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
     36     NopInst.addOperand(MCOperand::CreateReg(0));
     37   } else {
     38     NopInst.setOpcode(ARM::MOVr);
     39     NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
     40     NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
     41     NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
     42     NopInst.addOperand(MCOperand::CreateReg(0));
     43     NopInst.addOperand(MCOperand::CreateReg(0));
     44   }
     45 }
     46 
     47 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
     48   switch (Opc) {
     49   default: break;
     50   case ARM::LDR_PRE_IMM:
     51   case ARM::LDR_PRE_REG:
     52   case ARM::LDR_POST_IMM:
     53   case ARM::LDR_POST_REG:
     54     return ARM::LDRi12;
     55   case ARM::LDRH_PRE:
     56   case ARM::LDRH_POST:
     57     return ARM::LDRH;
     58   case ARM::LDRB_PRE_IMM:
     59   case ARM::LDRB_PRE_REG:
     60   case ARM::LDRB_POST_IMM:
     61   case ARM::LDRB_POST_REG:
     62     return ARM::LDRBi12;
     63   case ARM::LDRSH_PRE:
     64   case ARM::LDRSH_POST:
     65     return ARM::LDRSH;
     66   case ARM::LDRSB_PRE:
     67   case ARM::LDRSB_POST:
     68     return ARM::LDRSB;
     69   case ARM::STR_PRE_IMM:
     70   case ARM::STR_PRE_REG:
     71   case ARM::STR_POST_IMM:
     72   case ARM::STR_POST_REG:
     73     return ARM::STRi12;
     74   case ARM::STRH_PRE:
     75   case ARM::STRH_POST:
     76     return ARM::STRH;
     77   case ARM::STRB_PRE_IMM:
     78   case ARM::STRB_PRE_REG:
     79   case ARM::STRB_POST_IMM:
     80   case ARM::STRB_POST_REG:
     81     return ARM::STRBi12;
     82   }
     83 
     84   return 0;
     85 }
     86