1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Thumb instruction set. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Thumb specific DAG Nodes. 16 // 17 18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22 def imm_sr_XFORM: SDNodeXForm<imm, [{ 23 unsigned Imm = N->getZExtValue(); 24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32); 25 }]>; 26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 28 uint64_t Imm = N->getZExtValue(); 29 return Imm > 0 && Imm <= 32; 30 }], imm_sr_XFORM> { 31 let PrintMethod = "printThumbSRImm"; 32 let ParserMatchClass = ThumbSRImmAsmOperand; 33 } 34 35 def imm_neg_XFORM : SDNodeXForm<imm, [{ 36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 37 }]>; 38 def imm_comp_XFORM : SDNodeXForm<imm, [{ 39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 40 }]>; 41 42 def imm0_7_neg : PatLeaf<(i32 imm), [{ 43 return (uint32_t)-N->getZExtValue() < 8; 44 }], imm_neg_XFORM>; 45 46 def imm0_255_comp : PatLeaf<(i32 imm), [{ 47 return ~((uint32_t)N->getZExtValue()) < 256; 48 }]>; 49 50 def imm8_255 : ImmLeaf<i32, [{ 51 return Imm >= 8 && Imm < 256; 52 }]>; 53 def imm8_255_neg : PatLeaf<(i32 imm), [{ 54 unsigned Val = -N->getZExtValue(); 55 return Val >= 8 && Val < 256; 56 }], imm_neg_XFORM>; 57 58 // Break imm's up into two pieces: an immediate + a left shift. This uses 59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 60 // to get the val/shift pieces. 61 def thumb_immshifted : PatLeaf<(imm), [{ 62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 63 }]>; 64 65 def thumb_immshifted_val : SDNodeXForm<imm, [{ 66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 67 return CurDAG->getTargetConstant(V, MVT::i32); 68 }]>; 69 70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 72 return CurDAG->getTargetConstant(V, MVT::i32); 73 }]>; 74 75 // ADR instruction labels. 76 def t_adrlabel : Operand<i32> { 77 let EncoderMethod = "getThumbAdrLabelOpValue"; 78 } 79 80 // Scaled 4 immediate. 81 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 82 def t_imm0_1020s4 : Operand<i32> { 83 let PrintMethod = "printThumbS4ImmOperand"; 84 let ParserMatchClass = t_imm0_1020s4_asmoperand; 85 let OperandType = "OPERAND_IMMEDIATE"; 86 } 87 88 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 89 def t_imm0_508s4 : Operand<i32> { 90 let PrintMethod = "printThumbS4ImmOperand"; 91 let ParserMatchClass = t_imm0_508s4_asmoperand; 92 let OperandType = "OPERAND_IMMEDIATE"; 93 } 94 // Alias use only, so no printer is necessary. 95 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 96 def t_imm0_508s4_neg : Operand<i32> { 97 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 98 let OperandType = "OPERAND_IMMEDIATE"; 99 } 100 101 // Define Thumb specific addressing modes. 102 103 let OperandType = "OPERAND_PCREL" in { 104 def t_brtarget : Operand<OtherVT> { 105 let EncoderMethod = "getThumbBRTargetOpValue"; 106 let DecoderMethod = "DecodeThumbBROperand"; 107 } 108 109 def t_bcctarget : Operand<i32> { 110 let EncoderMethod = "getThumbBCCTargetOpValue"; 111 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 112 } 113 114 def t_cbtarget : Operand<i32> { 115 let EncoderMethod = "getThumbCBTargetOpValue"; 116 let DecoderMethod = "DecodeThumbCmpBROperand"; 117 } 118 119 def t_bltarget : Operand<i32> { 120 let EncoderMethod = "getThumbBLTargetOpValue"; 121 let DecoderMethod = "DecodeThumbBLTargetOperand"; 122 } 123 124 def t_blxtarget : Operand<i32> { 125 let EncoderMethod = "getThumbBLXTargetOpValue"; 126 let DecoderMethod = "DecodeThumbBLXOffset"; 127 } 128 } 129 130 // t_addrmode_rr := reg + reg 131 // 132 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 133 def t_addrmode_rr : Operand<i32>, 134 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 135 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 136 let PrintMethod = "printThumbAddrModeRROperand"; 137 let DecoderMethod = "DecodeThumbAddrModeRR"; 138 let ParserMatchClass = t_addrmode_rr_asm_operand; 139 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 140 } 141 142 // t_addrmode_rrs := reg + reg 143 // 144 // We use separate scaled versions because the Select* functions need 145 // to explicitly check for a matching constant and return false here so that 146 // the reg+imm forms will match instead. This is a horrible way to do that, 147 // as it forces tight coupling between the methods, but it's how selectiondag 148 // currently works. 149 def t_addrmode_rrs1 : Operand<i32>, 150 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 151 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 152 let PrintMethod = "printThumbAddrModeRROperand"; 153 let DecoderMethod = "DecodeThumbAddrModeRR"; 154 let ParserMatchClass = t_addrmode_rr_asm_operand; 155 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 156 } 157 def t_addrmode_rrs2 : Operand<i32>, 158 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 159 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 160 let DecoderMethod = "DecodeThumbAddrModeRR"; 161 let PrintMethod = "printThumbAddrModeRROperand"; 162 let ParserMatchClass = t_addrmode_rr_asm_operand; 163 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 164 } 165 def t_addrmode_rrs4 : Operand<i32>, 166 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 167 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 168 let DecoderMethod = "DecodeThumbAddrModeRR"; 169 let PrintMethod = "printThumbAddrModeRROperand"; 170 let ParserMatchClass = t_addrmode_rr_asm_operand; 171 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 172 } 173 174 // t_addrmode_is4 := reg + imm5 * 4 175 // 176 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 177 def t_addrmode_is4 : Operand<i32>, 178 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 179 let EncoderMethod = "getAddrModeISOpValue"; 180 let DecoderMethod = "DecodeThumbAddrModeIS"; 181 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 182 let ParserMatchClass = t_addrmode_is4_asm_operand; 183 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 184 } 185 186 // t_addrmode_is2 := reg + imm5 * 2 187 // 188 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 189 def t_addrmode_is2 : Operand<i32>, 190 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 191 let EncoderMethod = "getAddrModeISOpValue"; 192 let DecoderMethod = "DecodeThumbAddrModeIS"; 193 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 194 let ParserMatchClass = t_addrmode_is2_asm_operand; 195 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 196 } 197 198 // t_addrmode_is1 := reg + imm5 199 // 200 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 201 def t_addrmode_is1 : Operand<i32>, 202 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 203 let EncoderMethod = "getAddrModeISOpValue"; 204 let DecoderMethod = "DecodeThumbAddrModeIS"; 205 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 206 let ParserMatchClass = t_addrmode_is1_asm_operand; 207 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 208 } 209 210 // t_addrmode_sp := sp + imm8 * 4 211 // 212 // FIXME: This really shouldn't have an explicit SP operand at all. It should 213 // be implicit, just like in the instruction encoding itself. 214 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 215 def t_addrmode_sp : Operand<i32>, 216 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 217 let EncoderMethod = "getAddrModeThumbSPOpValue"; 218 let DecoderMethod = "DecodeThumbAddrModeSP"; 219 let PrintMethod = "printThumbAddrModeSPOperand"; 220 let ParserMatchClass = t_addrmode_sp_asm_operand; 221 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 222 } 223 224 // t_addrmode_pc := <label> => pc + imm8 * 4 225 // 226 def t_addrmode_pc : Operand<i32> { 227 let EncoderMethod = "getAddrModePCOpValue"; 228 let DecoderMethod = "DecodeThumbAddrModePC"; 229 } 230 231 //===----------------------------------------------------------------------===// 232 // Miscellaneous Instructions. 233 // 234 235 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 236 // from removing one half of the matched pairs. That breaks PEI, which assumes 237 // these will always be in pairs, and asserts if it finds otherwise. Better way? 238 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 239 def tADJCALLSTACKUP : 240 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 241 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 242 Requires<[IsThumb, IsThumb1Only]>; 243 244 def tADJCALLSTACKDOWN : 245 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 246 [(ARMcallseq_start imm:$amt)]>, 247 Requires<[IsThumb, IsThumb1Only]>; 248 } 249 250 class T1SystemEncoding<bits<8> opc> 251 : T1Encoding<0b101111> { 252 let Inst{9-8} = 0b11; 253 let Inst{7-0} = opc; 254 } 255 256 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>, 257 T1SystemEncoding<0x00>, // A8.6.110 258 Requires<[IsThumb2]>; 259 260 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>, 261 T1SystemEncoding<0x10>; // A8.6.410 262 263 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>, 264 T1SystemEncoding<0x20>; // A8.6.408 265 266 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>, 267 T1SystemEncoding<0x30>; // A8.6.409 268 269 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>, 270 T1SystemEncoding<0x40>; // A8.6.157 271 272 // The imm operand $val can be used by a debugger to store more information 273 // about the breakpoint. 274 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 275 []>, 276 T1Encoding<0b101111> { 277 let Inst{9-8} = 0b10; 278 // A8.6.22 279 bits<8> val; 280 let Inst{7-0} = val; 281 } 282 283 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 284 []>, T1Encoding<0b101101> { 285 bits<1> end; 286 // A8.6.156 287 let Inst{9-5} = 0b10010; 288 let Inst{4} = 1; 289 let Inst{3} = end; 290 let Inst{2-0} = 0b000; 291 } 292 293 // Change Processor State is a system instruction -- for disassembly only. 294 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 295 NoItinerary, "cps$imod $iflags", []>, 296 T1Misc<0b0110011> { 297 // A8.6.38 & B6.1.1 298 bit imod; 299 bits<3> iflags; 300 301 let Inst{4} = imod; 302 let Inst{3} = 0; 303 let Inst{2-0} = iflags; 304 let DecoderMethod = "DecodeThumbCPS"; 305 } 306 307 // For both thumb1 and thumb2. 308 let isNotDuplicable = 1, isCodeGenOnly = 1 in 309 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 310 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 311 T1Special<{0,0,?,?}> { 312 // A8.6.6 313 bits<3> dst; 314 let Inst{6-3} = 0b1111; // Rm = pc 315 let Inst{2-0} = dst; 316 } 317 318 // ADD <Rd>, sp, #<imm8> 319 // FIXME: This should not be marked as having side effects, and it should be 320 // rematerializable. Clearing the side effect bit causes miscompilations, 321 // probably because the instruction can be moved around. 322 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 323 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 324 T1Encoding<{1,0,1,0,1,?}> { 325 // A6.2 & A8.6.8 326 bits<3> dst; 327 bits<8> imm; 328 let Inst{10-8} = dst; 329 let Inst{7-0} = imm; 330 let DecoderMethod = "DecodeThumbAddSpecialReg"; 331 } 332 333 // ADD sp, sp, #<imm7> 334 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 335 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 336 T1Misc<{0,0,0,0,0,?,?}> { 337 // A6.2.5 & A8.6.8 338 bits<7> imm; 339 let Inst{6-0} = imm; 340 let DecoderMethod = "DecodeThumbAddSPImm"; 341 } 342 343 // SUB sp, sp, #<imm7> 344 // FIXME: The encoding and the ASM string don't match up. 345 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 346 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 347 T1Misc<{0,0,0,0,1,?,?}> { 348 // A6.2.5 & A8.6.214 349 bits<7> imm; 350 let Inst{6-0} = imm; 351 let DecoderMethod = "DecodeThumbAddSPImm"; 352 } 353 354 def : tInstAlias<"add${p} sp, $imm", 355 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 356 def : tInstAlias<"add${p} sp, sp, $imm", 357 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 358 359 // Can optionally specify SP as a three operand instruction. 360 def : tInstAlias<"add${p} sp, sp, $imm", 361 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 362 def : tInstAlias<"sub${p} sp, sp, $imm", 363 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 364 365 // ADD <Rm>, sp 366 def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr, 367 "add", "\t$Rdn, $sp, $Rn", []>, 368 T1Special<{0,0,?,?}> { 369 // A8.6.9 Encoding T1 370 bits<4> Rdn; 371 let Inst{7} = Rdn{3}; 372 let Inst{6-3} = 0b1101; 373 let Inst{2-0} = Rdn{2-0}; 374 let DecoderMethod = "DecodeThumbAddSPReg"; 375 } 376 377 // ADD sp, <Rm> 378 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 379 "add", "\t$Rdn, $Rm", []>, 380 T1Special<{0,0,?,?}> { 381 // A8.6.9 Encoding T2 382 bits<4> Rm; 383 let Inst{7} = 1; 384 let Inst{6-3} = Rm; 385 let Inst{2-0} = 0b101; 386 let DecoderMethod = "DecodeThumbAddSPReg"; 387 } 388 389 //===----------------------------------------------------------------------===// 390 // Control Flow Instructions. 391 // 392 393 // Indirect branches 394 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 395 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 396 T1Special<{1,1,0,?}> { 397 // A6.2.3 & A8.6.25 398 bits<4> Rm; 399 let Inst{6-3} = Rm; 400 let Inst{2-0} = 0b000; 401 let Unpredictable{2-0} = 0b111; 402 } 403 } 404 405 let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 406 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 407 [(ARMretflag)], (tBX LR, pred:$p)>; 408 409 // Alternative return instruction used by vararg functions. 410 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 411 2, IIC_Br, [], 412 (tBX GPR:$Rm, pred:$p)>; 413 } 414 415 // All calls clobber the non-callee saved registers. SP is marked as a use to 416 // prevent stack-pointer assignments that appear immediately before calls from 417 // potentially appearing dead. 418 let isCall = 1, 419 Defs = [LR], Uses = [SP] in { 420 // Also used for Thumb2 421 def tBL : TIx2<0b11110, 0b11, 1, 422 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br, 423 "bl${p}\t$func", 424 [(ARMtcall tglobaladdr:$func)]>, 425 Requires<[IsThumb]> { 426 bits<22> func; 427 let Inst{26} = func{21}; 428 let Inst{25-16} = func{20-11}; 429 let Inst{13} = 1; 430 let Inst{11} = 1; 431 let Inst{10-0} = func{10-0}; 432 } 433 434 // ARMv5T and above, also used for Thumb2 435 def tBLXi : TIx2<0b11110, 0b11, 0, 436 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br, 437 "blx${p}\t$func", 438 [(ARMcall tglobaladdr:$func)]>, 439 Requires<[IsThumb, HasV5T]> { 440 bits<21> func; 441 let Inst{25-16} = func{20-11}; 442 let Inst{13} = 1; 443 let Inst{11} = 1; 444 let Inst{10-1} = func{10-1}; 445 let Inst{0} = 0; // func{0} is assumed zero 446 } 447 448 // Also used for Thumb2 449 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br, 450 "blx${p}\t$func", 451 [(ARMtcall GPR:$func)]>, 452 Requires<[IsThumb, HasV5T]>, 453 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24; 454 bits<4> func; 455 let Inst{6-3} = func; 456 let Inst{2-0} = 0b000; 457 } 458 459 // ARMv4T 460 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), 461 4, IIC_Br, 462 [(ARMcall_nolink tGPR:$func)]>, 463 Requires<[IsThumb, IsThumb1Only]>; 464 } 465 466 let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 467 let isPredicable = 1 in 468 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 469 "b", "\t$target", [(br bb:$target)]>, 470 T1Encoding<{1,1,1,0,0,?}> { 471 bits<11> target; 472 let Inst{10-0} = target; 473 } 474 475 // Far jump 476 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 477 // the clobber of LR. 478 let Defs = [LR] in 479 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), 480 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>; 481 482 def tBR_JTr : tPseudoInst<(outs), 483 (ins tGPR:$target, i32imm:$jt, i32imm:$id), 484 0, IIC_Br, 485 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> { 486 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 487 } 488 } 489 490 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 491 // a two-value operand where a dag node expects two operands. :( 492 let isBranch = 1, isTerminator = 1 in 493 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 494 "b${p}\t$target", 495 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 496 T1BranchCond<{1,1,0,1}> { 497 bits<4> p; 498 bits<8> target; 499 let Inst{11-8} = p; 500 let Inst{7-0} = target; 501 } 502 503 // Tail calls 504 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 505 // IOS versions. 506 let Uses = [SP] in { 507 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 508 4, IIC_Br, [], 509 (tBX GPR:$dst, (ops 14, zero_reg))>, 510 Requires<[IsThumb]>; 511 } 512 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls 513 // on IOS), so it's in ARMInstrThumb2.td. 514 // Non-IOS version: 515 let Uses = [SP] in { 516 def tTAILJMPdND : tPseudoExpand<(outs), 517 (ins t_brtarget:$dst, pred:$p, variable_ops), 518 4, IIC_Br, [], 519 (tB t_brtarget:$dst, pred:$p)>, 520 Requires<[IsThumb, IsNotIOS]>; 521 } 522 } 523 524 525 // A8.6.218 Supervisor Call (Software Interrupt) 526 // A8.6.16 B: Encoding T1 527 // If Inst{11-8} == 0b1111 then SEE SVC 528 let isCall = 1, Uses = [SP] in 529 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 530 "svc", "\t$imm", []>, Encoding16 { 531 bits<8> imm; 532 let Inst{15-12} = 0b1101; 533 let Inst{11-8} = 0b1111; 534 let Inst{7-0} = imm; 535 } 536 537 // The assembler uses 0xDEFE for a trap instruction. 538 let isBarrier = 1, isTerminator = 1 in 539 def tTRAP : TI<(outs), (ins), IIC_Br, 540 "trap", [(trap)]>, Encoding16 { 541 let Inst = 0xdefe; 542 } 543 544 //===----------------------------------------------------------------------===// 545 // Load Store Instructions. 546 // 547 548 // Loads: reg/reg and reg/imm5 549 let canFoldAsLoad = 1, isReMaterializable = 1 in 550 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 551 Operand AddrMode_r, Operand AddrMode_i, 552 AddrMode am, InstrItinClass itin_r, 553 InstrItinClass itin_i, string asm, 554 PatFrag opnode> { 555 def r : // reg/reg 556 T1pILdStEncode<reg_opc, 557 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 558 am, itin_r, asm, "\t$Rt, $addr", 559 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 560 def i : // reg/imm5 561 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 562 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 563 am, itin_i, asm, "\t$Rt, $addr", 564 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 565 } 566 // Stores: reg/reg and reg/imm5 567 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 568 Operand AddrMode_r, Operand AddrMode_i, 569 AddrMode am, InstrItinClass itin_r, 570 InstrItinClass itin_i, string asm, 571 PatFrag opnode> { 572 def r : // reg/reg 573 T1pILdStEncode<reg_opc, 574 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 575 am, itin_r, asm, "\t$Rt, $addr", 576 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 577 def i : // reg/imm5 578 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 579 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 580 am, itin_i, asm, "\t$Rt, $addr", 581 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 582 } 583 584 // A8.6.57 & A8.6.60 585 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4, 586 t_addrmode_is4, AddrModeT1_4, 587 IIC_iLoad_r, IIC_iLoad_i, "ldr", 588 UnOpFrag<(load node:$Src)>>; 589 590 // A8.6.64 & A8.6.61 591 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1, 592 t_addrmode_is1, AddrModeT1_1, 593 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 594 UnOpFrag<(zextloadi8 node:$Src)>>; 595 596 // A8.6.76 & A8.6.73 597 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2, 598 t_addrmode_is2, AddrModeT1_2, 599 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 600 UnOpFrag<(zextloadi16 node:$Src)>>; 601 602 let AddedComplexity = 10 in 603 def tLDRSB : // A8.6.80 604 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 605 AddrModeT1_1, IIC_iLoad_bh_r, 606 "ldrsb", "\t$Rt, $addr", 607 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 608 609 let AddedComplexity = 10 in 610 def tLDRSH : // A8.6.84 611 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 612 AddrModeT1_2, IIC_iLoad_bh_r, 613 "ldrsh", "\t$Rt, $addr", 614 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 615 616 let canFoldAsLoad = 1 in 617 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 618 "ldr", "\t$Rt, $addr", 619 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 620 T1LdStSP<{1,?,?}> { 621 bits<3> Rt; 622 bits<8> addr; 623 let Inst{10-8} = Rt; 624 let Inst{7-0} = addr; 625 } 626 627 // Load tconstpool 628 // FIXME: Use ldr.n to work around a darwin assembler bug. 629 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in 630 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 631 "ldr", ".n\t$Rt, $addr", 632 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 633 T1Encoding<{0,1,0,0,1,?}> { 634 // A6.2 & A8.6.59 635 bits<3> Rt; 636 bits<8> addr; 637 let Inst{10-8} = Rt; 638 let Inst{7-0} = addr; 639 } 640 641 // FIXME: Remove this entry when the above ldr.n workaround is fixed. 642 // For assembly/disassembly use only. 643 def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 644 "ldr", "\t$Rt, $addr", []>, 645 T1Encoding<{0,1,0,0,1,?}> { 646 // A6.2 & A8.6.59 647 bits<3> Rt; 648 bits<8> addr; 649 let Inst{10-8} = Rt; 650 let Inst{7-0} = addr; 651 } 652 653 // A8.6.194 & A8.6.192 654 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, 655 t_addrmode_is4, AddrModeT1_4, 656 IIC_iStore_r, IIC_iStore_i, "str", 657 BinOpFrag<(store node:$LHS, node:$RHS)>>; 658 659 // A8.6.197 & A8.6.195 660 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1, 661 t_addrmode_is1, AddrModeT1_1, 662 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 663 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 664 665 // A8.6.207 & A8.6.205 666 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2, 667 t_addrmode_is2, AddrModeT1_2, 668 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 669 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 670 671 672 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 673 "str", "\t$Rt, $addr", 674 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 675 T1LdStSP<{0,?,?}> { 676 bits<3> Rt; 677 bits<8> addr; 678 let Inst{10-8} = Rt; 679 let Inst{7-0} = addr; 680 } 681 682 //===----------------------------------------------------------------------===// 683 // Load / store multiple Instructions. 684 // 685 686 // These require base address to be written back or one of the loaded regs. 687 let neverHasSideEffects = 1 in { 688 689 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 690 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 691 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 692 bits<3> Rn; 693 bits<8> regs; 694 let Inst{10-8} = Rn; 695 let Inst{7-0} = regs; 696 } 697 698 // Writeback version is just a pseudo, as there's no encoding difference. 699 // Writeback happens iff the base register is not in the destination register 700 // list. 701 def tLDMIA_UPD : 702 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 703 "$Rn = $wb", IIC_iLoad_mu>, 704 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 705 let Size = 2; 706 let OutOperandList = (outs GPR:$wb); 707 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 708 let Pattern = []; 709 let isCodeGenOnly = 1; 710 let isPseudo = 1; 711 list<Predicate> Predicates = [IsThumb]; 712 } 713 714 // There is no non-writeback version of STM for Thumb. 715 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 716 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 717 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 718 AddrModeNone, 2, IIC_iStore_mu, 719 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 720 T1Encoding<{1,1,0,0,0,?}> { 721 bits<3> Rn; 722 bits<8> regs; 723 let Inst{10-8} = Rn; 724 let Inst{7-0} = regs; 725 } 726 727 } // neverHasSideEffects 728 729 def : InstAlias<"ldm${p} $Rn!, $regs", 730 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, 731 Requires<[IsThumb, IsThumb1Only]>; 732 733 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 734 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 735 IIC_iPop, 736 "pop${p}\t$regs", []>, 737 T1Misc<{1,1,0,?,?,?,?}> { 738 bits<16> regs; 739 let Inst{8} = regs{15}; 740 let Inst{7-0} = regs{7-0}; 741 } 742 743 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 744 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 745 IIC_iStore_m, 746 "push${p}\t$regs", []>, 747 T1Misc<{0,1,0,?,?,?,?}> { 748 bits<16> regs; 749 let Inst{8} = regs{14}; 750 let Inst{7-0} = regs{7-0}; 751 } 752 753 //===----------------------------------------------------------------------===// 754 // Arithmetic Instructions. 755 // 756 757 // Helper classes for encoding T1pI patterns: 758 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 759 string opc, string asm, list<dag> pattern> 760 : T1pI<oops, iops, itin, opc, asm, pattern>, 761 T1DataProcessing<opA> { 762 bits<3> Rm; 763 bits<3> Rn; 764 let Inst{5-3} = Rm; 765 let Inst{2-0} = Rn; 766 } 767 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 768 string opc, string asm, list<dag> pattern> 769 : T1pI<oops, iops, itin, opc, asm, pattern>, 770 T1Misc<opA> { 771 bits<3> Rm; 772 bits<3> Rd; 773 let Inst{5-3} = Rm; 774 let Inst{2-0} = Rd; 775 } 776 777 // Helper classes for encoding T1sI patterns: 778 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 779 string opc, string asm, list<dag> pattern> 780 : T1sI<oops, iops, itin, opc, asm, pattern>, 781 T1DataProcessing<opA> { 782 bits<3> Rd; 783 bits<3> Rn; 784 let Inst{5-3} = Rn; 785 let Inst{2-0} = Rd; 786 } 787 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 788 string opc, string asm, list<dag> pattern> 789 : T1sI<oops, iops, itin, opc, asm, pattern>, 790 T1General<opA> { 791 bits<3> Rm; 792 bits<3> Rn; 793 bits<3> Rd; 794 let Inst{8-6} = Rm; 795 let Inst{5-3} = Rn; 796 let Inst{2-0} = Rd; 797 } 798 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 799 string opc, string asm, list<dag> pattern> 800 : T1sI<oops, iops, itin, opc, asm, pattern>, 801 T1General<opA> { 802 bits<3> Rd; 803 bits<3> Rm; 804 let Inst{5-3} = Rm; 805 let Inst{2-0} = Rd; 806 } 807 808 // Helper classes for encoding T1sIt patterns: 809 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 810 string opc, string asm, list<dag> pattern> 811 : T1sIt<oops, iops, itin, opc, asm, pattern>, 812 T1DataProcessing<opA> { 813 bits<3> Rdn; 814 bits<3> Rm; 815 let Inst{5-3} = Rm; 816 let Inst{2-0} = Rdn; 817 } 818 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 819 string opc, string asm, list<dag> pattern> 820 : T1sIt<oops, iops, itin, opc, asm, pattern>, 821 T1General<opA> { 822 bits<3> Rdn; 823 bits<8> imm8; 824 let Inst{10-8} = Rdn; 825 let Inst{7-0} = imm8; 826 } 827 828 // Add with carry register 829 let isCommutable = 1, Uses = [CPSR] in 830 def tADC : // A8.6.2 831 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 832 "adc", "\t$Rdn, $Rm", 833 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>; 834 835 // Add immediate 836 def tADDi3 : // A8.6.4 T1 837 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 838 IIC_iALUi, 839 "add", "\t$Rd, $Rm, $imm3", 840 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> { 841 bits<3> imm3; 842 let Inst{8-6} = imm3; 843 } 844 845 def tADDi8 : // A8.6.4 T2 846 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 847 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 848 "add", "\t$Rdn, $imm8", 849 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>; 850 851 // Add register 852 let isCommutable = 1 in 853 def tADDrr : // A8.6.6 T1 854 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 855 IIC_iALUr, 856 "add", "\t$Rd, $Rn, $Rm", 857 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>; 858 859 let neverHasSideEffects = 1 in 860 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 861 "add", "\t$Rdn, $Rm", []>, 862 T1Special<{0,0,?,?}> { 863 // A8.6.6 T2 864 bits<4> Rdn; 865 bits<4> Rm; 866 let Inst{7} = Rdn{3}; 867 let Inst{6-3} = Rm; 868 let Inst{2-0} = Rdn{2-0}; 869 } 870 871 // AND register 872 let isCommutable = 1 in 873 def tAND : // A8.6.12 874 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 875 IIC_iBITr, 876 "and", "\t$Rdn, $Rm", 877 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>; 878 879 // ASR immediate 880 def tASRri : // A8.6.14 881 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 882 IIC_iMOVsi, 883 "asr", "\t$Rd, $Rm, $imm5", 884 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> { 885 bits<5> imm5; 886 let Inst{10-6} = imm5; 887 } 888 889 // ASR register 890 def tASRrr : // A8.6.15 891 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 892 IIC_iMOVsr, 893 "asr", "\t$Rdn, $Rm", 894 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>; 895 896 // BIC register 897 def tBIC : // A8.6.20 898 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 899 IIC_iBITr, 900 "bic", "\t$Rdn, $Rm", 901 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>; 902 903 // CMN register 904 let isCompare = 1, Defs = [CPSR] in { 905 //FIXME: Disable CMN, as CCodes are backwards from compare expectations 906 // Compare-to-zero still works out, just not the relationals 907 //def tCMN : // A8.6.33 908 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 909 // IIC_iCMPr, 910 // "cmn", "\t$lhs, $rhs", 911 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 912 913 def tCMNz : // A8.6.33 914 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 915 IIC_iCMPr, 916 "cmn", "\t$Rn, $Rm", 917 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>; 918 919 } // isCompare = 1, Defs = [CPSR] 920 921 // CMP immediate 922 let isCompare = 1, Defs = [CPSR] in { 923 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 924 "cmp", "\t$Rn, $imm8", 925 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 926 T1General<{1,0,1,?,?}> { 927 // A8.6.35 928 bits<3> Rn; 929 bits<8> imm8; 930 let Inst{10-8} = Rn; 931 let Inst{7-0} = imm8; 932 } 933 934 // CMP register 935 def tCMPr : // A8.6.36 T1 936 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 937 IIC_iCMPr, 938 "cmp", "\t$Rn, $Rm", 939 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>; 940 941 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 942 "cmp", "\t$Rn, $Rm", []>, 943 T1Special<{0,1,?,?}> { 944 // A8.6.36 T2 945 bits<4> Rm; 946 bits<4> Rn; 947 let Inst{7} = Rn{3}; 948 let Inst{6-3} = Rm; 949 let Inst{2-0} = Rn{2-0}; 950 } 951 } // isCompare = 1, Defs = [CPSR] 952 953 954 // XOR register 955 let isCommutable = 1 in 956 def tEOR : // A8.6.45 957 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 958 IIC_iBITr, 959 "eor", "\t$Rdn, $Rm", 960 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>; 961 962 // LSL immediate 963 def tLSLri : // A8.6.88 964 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 965 IIC_iMOVsi, 966 "lsl", "\t$Rd, $Rm, $imm5", 967 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> { 968 bits<5> imm5; 969 let Inst{10-6} = imm5; 970 } 971 972 // LSL register 973 def tLSLrr : // A8.6.89 974 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 975 IIC_iMOVsr, 976 "lsl", "\t$Rdn, $Rm", 977 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>; 978 979 // LSR immediate 980 def tLSRri : // A8.6.90 981 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 982 IIC_iMOVsi, 983 "lsr", "\t$Rd, $Rm, $imm5", 984 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> { 985 bits<5> imm5; 986 let Inst{10-6} = imm5; 987 } 988 989 // LSR register 990 def tLSRrr : // A8.6.91 991 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 992 IIC_iMOVsr, 993 "lsr", "\t$Rdn, $Rm", 994 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>; 995 996 // Move register 997 let isMoveImm = 1 in 998 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 999 "mov", "\t$Rd, $imm8", 1000 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1001 T1General<{1,0,0,?,?}> { 1002 // A8.6.96 1003 bits<3> Rd; 1004 bits<8> imm8; 1005 let Inst{10-8} = Rd; 1006 let Inst{7-0} = imm8; 1007 } 1008 // Because we have an explicit tMOVSr below, we need an alias to handle 1009 // the immediate "movs" form here. Blech. 1010 def : tInstAlias <"movs $Rdn, $imm", 1011 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1012 1013 // A7-73: MOV(2) - mov setting flag. 1014 1015 let neverHasSideEffects = 1 in { 1016 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1017 2, IIC_iMOVr, 1018 "mov", "\t$Rd, $Rm", "", []>, 1019 T1Special<{1,0,?,?}> { 1020 // A8.6.97 1021 bits<4> Rd; 1022 bits<4> Rm; 1023 let Inst{7} = Rd{3}; 1024 let Inst{6-3} = Rm; 1025 let Inst{2-0} = Rd{2-0}; 1026 } 1027 let Defs = [CPSR] in 1028 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1029 "movs\t$Rd, $Rm", []>, Encoding16 { 1030 // A8.6.97 1031 bits<3> Rd; 1032 bits<3> Rm; 1033 let Inst{15-6} = 0b0000000000; 1034 let Inst{5-3} = Rm; 1035 let Inst{2-0} = Rd; 1036 } 1037 } // neverHasSideEffects 1038 1039 // Multiply register 1040 let isCommutable = 1 in 1041 def tMUL : // A8.6.105 T1 1042 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1043 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1044 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1045 T1DataProcessing<0b1101> { 1046 bits<3> Rd; 1047 bits<3> Rn; 1048 let Inst{5-3} = Rn; 1049 let Inst{2-0} = Rd; 1050 let AsmMatchConverter = "cvtThumbMultiply"; 1051 } 1052 1053 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1054 pred:$p)>; 1055 1056 // Move inverse register 1057 def tMVN : // A8.6.107 1058 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1059 "mvn", "\t$Rd, $Rn", 1060 [(set tGPR:$Rd, (not tGPR:$Rn))]>; 1061 1062 // Bitwise or register 1063 let isCommutable = 1 in 1064 def tORR : // A8.6.114 1065 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1066 IIC_iBITr, 1067 "orr", "\t$Rdn, $Rm", 1068 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>; 1069 1070 // Swaps 1071 def tREV : // A8.6.134 1072 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1073 IIC_iUNAr, 1074 "rev", "\t$Rd, $Rm", 1075 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1076 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1077 1078 def tREV16 : // A8.6.135 1079 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1080 IIC_iUNAr, 1081 "rev16", "\t$Rd, $Rm", 1082 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1083 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1084 1085 def tREVSH : // A8.6.136 1086 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1087 IIC_iUNAr, 1088 "revsh", "\t$Rd, $Rm", 1089 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1090 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1091 1092 // Rotate right register 1093 def tROR : // A8.6.139 1094 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1095 IIC_iMOVsr, 1096 "ror", "\t$Rdn, $Rm", 1097 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>; 1098 1099 // Negate register 1100 def tRSB : // A8.6.141 1101 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1102 IIC_iALUi, 1103 "rsb", "\t$Rd, $Rn, #0", 1104 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>; 1105 1106 // Subtract with carry register 1107 let Uses = [CPSR] in 1108 def tSBC : // A8.6.151 1109 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1110 IIC_iALUr, 1111 "sbc", "\t$Rdn, $Rm", 1112 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>; 1113 1114 // Subtract immediate 1115 def tSUBi3 : // A8.6.210 T1 1116 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1117 IIC_iALUi, 1118 "sub", "\t$Rd, $Rm, $imm3", 1119 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> { 1120 bits<3> imm3; 1121 let Inst{8-6} = imm3; 1122 } 1123 1124 def tSUBi8 : // A8.6.210 T2 1125 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1126 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1127 "sub", "\t$Rdn, $imm8", 1128 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>; 1129 1130 // Subtract register 1131 def tSUBrr : // A8.6.212 1132 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1133 IIC_iALUr, 1134 "sub", "\t$Rd, $Rn, $Rm", 1135 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>; 1136 1137 // Sign-extend byte 1138 def tSXTB : // A8.6.222 1139 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1140 IIC_iUNAr, 1141 "sxtb", "\t$Rd, $Rm", 1142 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1143 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1144 1145 // Sign-extend short 1146 def tSXTH : // A8.6.224 1147 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1148 IIC_iUNAr, 1149 "sxth", "\t$Rd, $Rm", 1150 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1151 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1152 1153 // Test 1154 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1155 def tTST : // A8.6.230 1156 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1157 "tst", "\t$Rn, $Rm", 1158 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>; 1159 1160 // Zero-extend byte 1161 def tUXTB : // A8.6.262 1162 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1163 IIC_iUNAr, 1164 "uxtb", "\t$Rd, $Rm", 1165 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1166 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1167 1168 // Zero-extend short 1169 def tUXTH : // A8.6.264 1170 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1171 IIC_iUNAr, 1172 "uxth", "\t$Rd, $Rm", 1173 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1174 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1175 1176 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1177 // Expanded after instruction selection into a branch sequence. 1178 let usesCustomInserter = 1 in // Expanded after instruction selection. 1179 def tMOVCCr_pseudo : 1180 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 1181 NoItinerary, 1182 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 1183 1184 // tLEApcrel - Load a pc-relative address into a register without offending the 1185 // assembler. 1186 1187 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1188 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1189 T1Encoding<{1,0,1,0,0,?}> { 1190 bits<3> Rd; 1191 bits<8> addr; 1192 let Inst{10-8} = Rd; 1193 let Inst{7-0} = addr; 1194 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1195 } 1196 1197 let neverHasSideEffects = 1, isReMaterializable = 1 in 1198 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1199 2, IIC_iALUi, []>; 1200 1201 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1202 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1203 2, IIC_iALUi, []>; 1204 1205 //===----------------------------------------------------------------------===// 1206 // TLS Instructions 1207 // 1208 1209 // __aeabi_read_tp preserves the registers r1-r3. 1210 // This is a pseudo inst so that we can get the encoding right, 1211 // complete with fixup for the aeabi_read_tp function. 1212 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1213 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1214 [(set R0, ARMthread_pointer)]>; 1215 1216 //===----------------------------------------------------------------------===// 1217 // SJLJ Exception handling intrinsics 1218 // 1219 1220 // eh_sjlj_setjmp() is an instruction sequence to store the return address and 1221 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1222 // from some other function to get here, and we're using the stack frame for the 1223 // containing function to save/restore registers, we can't keep anything live in 1224 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1225 // tromped upon when we get here from a longjmp(). We force everything out of 1226 // registers except for our own input by listing the relevant registers in 1227 // Defs. By doing so, we also cause the prologue/epilogue code to actively 1228 // preserve all of the callee-saved resgisters, which is exactly what we want. 1229 // $val is a scratch register for our use. 1230 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1231 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1232 usesCustomInserter = 1 in 1233 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1234 AddrModeNone, 0, NoItinerary, "","", 1235 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1236 1237 // FIXME: Non-IOS version(s) 1238 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1239 Defs = [ R7, LR, SP ] in 1240 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1241 AddrModeNone, 0, IndexModeNone, 1242 Pseudo, NoItinerary, "", "", 1243 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1244 Requires<[IsThumb, IsIOS]>; 1245 1246 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1247 isBarrier = 1 in 1248 def tInt_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 1249 1250 //===----------------------------------------------------------------------===// 1251 // Non-Instruction Patterns 1252 // 1253 1254 // Comparisons 1255 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1256 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1257 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1258 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1259 1260 // Add with carry 1261 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1262 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1263 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1264 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1265 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1266 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1267 1268 // Subtract with carry 1269 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1270 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1271 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1272 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1273 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1274 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1275 1276 // ConstantPool, GlobalAddress 1277 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 1278 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1279 1280 // JumpTable 1281 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1282 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 1283 1284 // Direct calls 1285 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1286 Requires<[IsThumb]>; 1287 1288 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1289 Requires<[IsThumb, HasV5T]>; 1290 1291 // Indirect calls to ARM routines 1292 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1293 Requires<[IsThumb, HasV5T]>; 1294 1295 // zextload i1 -> zextload i8 1296 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), 1297 (tLDRBr t_addrmode_rrs1:$addr)>; 1298 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1299 (tLDRBi t_addrmode_is1:$addr)>; 1300 1301 // extload -> zextload 1302 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1303 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1304 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1305 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1306 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>; 1307 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1308 1309 // If it's impossible to use [r,r] address mode for sextload, select to 1310 // ldr{b|h} + sxt{b|h} instead. 1311 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1312 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1313 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1314 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1315 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>, 1316 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1317 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1318 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1319 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1320 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1321 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>, 1322 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1323 1324 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1325 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>; 1326 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1327 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1328 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1329 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>; 1330 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1331 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1332 1333 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1334 (tLDRBi t_addrmode_is1:$src)>; 1335 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src), 1336 (tLDRBr t_addrmode_rrs1:$src)>; 1337 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1338 (tLDRHi t_addrmode_is2:$src)>; 1339 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src), 1340 (tLDRHr t_addrmode_rrs2:$src)>; 1341 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1342 (tLDRi t_addrmode_is4:$src)>; 1343 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src), 1344 (tLDRr t_addrmode_rrs4:$src)>; 1345 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1346 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1347 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val), 1348 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>; 1349 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1350 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1351 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val), 1352 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>; 1353 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1354 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1355 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val), 1356 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>; 1357 1358 // Large immediate handling. 1359 1360 // Two piece imms. 1361 def : T1Pat<(i32 thumb_immshifted:$src), 1362 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1363 (thumb_immshifted_shamt imm:$src))>; 1364 1365 def : T1Pat<(i32 imm0_255_comp:$src), 1366 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1367 1368 // Pseudo instruction that combines ldr from constpool and add pc. This should 1369 // be expanded into two instructions late to allow if-conversion and 1370 // scheduling. 1371 let isReMaterializable = 1 in 1372 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1373 NoItinerary, 1374 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1375 imm:$cp))]>, 1376 Requires<[IsThumb, IsThumb1Only]>; 1377 1378 // Pseudo-instruction for merged POP and return. 1379 // FIXME: remove when we have a way to marking a MI with these properties. 1380 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1381 hasExtraDefRegAllocReq = 1 in 1382 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1383 2, IIC_iPop_Br, [], 1384 (tPOP pred:$p, reglist:$regs)>; 1385 1386 // Indirect branch using "mov pc, $Rm" 1387 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1388 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1389 2, IIC_Br, [(brind GPR:$Rm)], 1390 (tMOVr PC, GPR:$Rm, pred:$p)>; 1391 } 1392 1393 1394 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1395 // encoding is available on ARMv6K, but we don't differentiate that finely. 1396 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>; 1397 1398 1399 // For round-trip assembly/disassembly, we have to handle a CPS instruction 1400 // without any iflags. That's not, strictly speaking, valid syntax, but it's 1401 // a useful extention and assembles to defined behaviour (the insn does 1402 // nothing). 1403 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1404 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1405 1406 // "neg" is and alias for "rsb rd, rn, #0" 1407 def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1408 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1409 1410 1411 // Implied destination operand forms for shifts. 1412 def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1413 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1414 def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1415 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1416 def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1417 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1418
