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      1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "ARMSubtarget.h"
     15 #include "ARMBaseRegisterInfo.h"
     16 #include "llvm/GlobalValue.h"
     17 #include "llvm/Target/TargetSubtargetInfo.h"
     18 #include "llvm/Support/CommandLine.h"
     19 
     20 #define GET_SUBTARGETINFO_TARGET_DESC
     21 #define GET_SUBTARGETINFO_CTOR
     22 #include "ARMGenSubtargetInfo.inc"
     23 
     24 using namespace llvm;
     25 
     26 cl::opt<bool>
     27 ReserveR9("arm-reserve-r9", cl::Hidden,
     28           cl::desc("Reserve R9, making it unavailable as GPR"));
     29 
     30 static cl::opt<bool>
     31 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
     32 
     33 static cl::opt<bool>
     34 StrictAlign("arm-strict-align", cl::Hidden,
     35             cl::desc("Disallow all unaligned memory accesses"));
     36 
     37 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
     38                            const std::string &FS)
     39   : ARMGenSubtargetInfo(TT, CPU, FS)
     40   , ARMProcFamily(Others)
     41   , HasV4TOps(false)
     42   , HasV5TOps(false)
     43   , HasV5TEOps(false)
     44   , HasV6Ops(false)
     45   , HasV6T2Ops(false)
     46   , HasV7Ops(false)
     47   , HasVFPv2(false)
     48   , HasVFPv3(false)
     49   , HasVFPv4(false)
     50   , HasNEON(false)
     51   , UseNEONForSinglePrecisionFP(false)
     52   , SlowFPVMLx(false)
     53   , HasVMLxForwarding(false)
     54   , SlowFPBrcc(false)
     55   , InThumbMode(false)
     56   , HasThumb2(false)
     57   , IsMClass(false)
     58   , NoARM(false)
     59   , PostRAScheduler(false)
     60   , IsR9Reserved(ReserveR9)
     61   , UseMovt(false)
     62   , SupportsTailCall(false)
     63   , HasFP16(false)
     64   , HasD16(false)
     65   , HasHardwareDivide(false)
     66   , HasT2ExtractPack(false)
     67   , HasDataBarrier(false)
     68   , Pref32BitThumb(false)
     69   , AvoidCPSRPartialUpdate(false)
     70   , HasMPExtension(false)
     71   , FPOnlySP(false)
     72   , AllowsUnalignedMem(false)
     73   , Thumb2DSP(false)
     74   , stackAlignment(4)
     75   , CPUString(CPU)
     76   , TargetTriple(TT)
     77   , TargetABI(ARM_ABI_APCS) {
     78   // Determine default and user specified characteristics
     79   if (CPUString.empty())
     80     CPUString = "generic";
     81 
     82   // Insert the architecture feature derived from the target triple into the
     83   // feature string. This is important for setting features that are implied
     84   // based on the architecture version.
     85   std::string ArchFS = ARM_MC::ParseARMTriple(TT);
     86   if (!FS.empty()) {
     87     if (!ArchFS.empty())
     88       ArchFS = ArchFS + "," + FS;
     89     else
     90       ArchFS = FS;
     91   }
     92   ParseSubtargetFeatures(CPUString, ArchFS);
     93 
     94   // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
     95   // ARM version or CPU and then remove this.
     96   if (!HasV6T2Ops && hasThumb2())
     97     HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
     98 
     99   // Initialize scheduling itinerary for the specified CPU.
    100   InstrItins = getInstrItineraryForCPU(CPUString);
    101 
    102   // After parsing Itineraries, set ItinData.IssueWidth.
    103   computeIssueWidth();
    104 
    105   if (TT.find("eabi") != std::string::npos)
    106     // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
    107     // Darwin-EABI conforms to AACPS but not the rest of EABI.
    108     TargetABI = ARM_ABI_AAPCS;
    109 
    110   if (isAAPCS_ABI())
    111     stackAlignment = 8;
    112 
    113   if (!isTargetIOS())
    114     UseMovt = hasV6T2Ops();
    115   else {
    116     IsR9Reserved = ReserveR9 | !HasV6Ops;
    117     UseMovt = DarwinUseMOVT && hasV6T2Ops();
    118     SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
    119   }
    120 
    121   if (!isThumb() || hasThumb2())
    122     PostRAScheduler = true;
    123 
    124   // v6+ may or may not support unaligned mem access depending on the system
    125   // configuration.
    126   if (!StrictAlign && hasV6Ops() && isTargetDarwin())
    127     AllowsUnalignedMem = true;
    128 }
    129 
    130 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
    131 bool
    132 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
    133                                  Reloc::Model RelocM) const {
    134   if (RelocM == Reloc::Static)
    135     return false;
    136 
    137   // Materializable GVs (in JIT lazy compilation mode) do not require an extra
    138   // load from stub.
    139   bool isDecl = GV->hasAvailableExternallyLinkage();
    140   if (GV->isDeclaration() && !GV->isMaterializable())
    141     isDecl = true;
    142 
    143   if (!isTargetDarwin()) {
    144     // Extra load is needed for all externally visible.
    145     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
    146       return false;
    147     return true;
    148   } else {
    149     if (RelocM == Reloc::PIC_) {
    150       // If this is a strong reference to a definition, it is definitely not
    151       // through a stub.
    152       if (!isDecl && !GV->isWeakForLinker())
    153         return false;
    154 
    155       // Unless we have a symbol with hidden visibility, we have to go through a
    156       // normal $non_lazy_ptr stub because this symbol might be resolved late.
    157       if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
    158         return true;
    159 
    160       // If symbol visibility is hidden, we have a stub for common symbol
    161       // references and external declarations.
    162       if (isDecl || GV->hasCommonLinkage())
    163         // Hidden $non_lazy_ptr reference.
    164         return true;
    165 
    166       return false;
    167     } else {
    168       // If this is a strong reference to a definition, it is definitely not
    169       // through a stub.
    170       if (!isDecl && !GV->isWeakForLinker())
    171         return false;
    172 
    173       // Unless we have a symbol with hidden visibility, we have to go through a
    174       // normal $non_lazy_ptr stub because this symbol might be resolved late.
    175       if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
    176         return true;
    177     }
    178   }
    179 
    180   return false;
    181 }
    182 
    183 unsigned ARMSubtarget::getMispredictionPenalty() const {
    184   // If we have a reasonable estimate of the pipeline depth, then we can
    185   // estimate the penalty of a misprediction based on that.
    186   if (isCortexA8())
    187     return 13;
    188   else if (isCortexA9())
    189     return 8;
    190 
    191   // Otherwise, just return a sensible default.
    192   return 10;
    193 }
    194 
    195 void ARMSubtarget::computeIssueWidth() {
    196   unsigned allStage1Units = 0;
    197   for (const InstrItinerary *itin = InstrItins.Itineraries;
    198        itin->FirstStage != ~0U; ++itin) {
    199     const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
    200     allStage1Units |= IS->getUnits();
    201   }
    202   InstrItins.IssueWidth = 0;
    203   while (allStage1Units) {
    204     ++InstrItins.IssueWidth;
    205     // clear the lowest bit
    206     allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
    207   }
    208   assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
    209 }
    210 
    211 bool ARMSubtarget::enablePostRAScheduler(
    212            CodeGenOpt::Level OptLevel,
    213            TargetSubtargetInfo::AntiDepBreakMode& Mode,
    214            RegClassVector& CriticalPathRCs) const {
    215   Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
    216   CriticalPathRCs.clear();
    217   CriticalPathRCs.push_back(&ARM::GPRRegClass);
    218   return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
    219 }
    220