1 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This is the top level entry point for the Hexagon target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Target-independent interfaces which we are implementing 16 //===----------------------------------------------------------------------===// 17 18 include "llvm/Target/Target.td" 19 20 //===----------------------------------------------------------------------===// 21 // Hexagon Subtarget features. 22 //===----------------------------------------------------------------------===// 23 24 // Hexagon Archtectures 25 def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2", 26 "Hexagon v2">; 27 def ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3", 28 "Hexagon v3">; 29 def ArchV4 : SubtargetFeature<"v4", "HexagonArchVersion", "V4", 30 "Hexagon v4">; 31 32 //===----------------------------------------------------------------------===// 33 // Register File, Calling Conv, Instruction Descriptions 34 //===----------------------------------------------------------------------===// 35 include "HexagonSchedule.td" 36 include "HexagonRegisterInfo.td" 37 include "HexagonCallingConv.td" 38 include "HexagonInstrInfo.td" 39 include "HexagonIntrinsics.td" 40 include "HexagonIntrinsicsDerived.td" 41 42 def HexagonInstrInfo : InstrInfo; 43 44 //===----------------------------------------------------------------------===// 45 // Hexagon processors supported. 46 //===----------------------------------------------------------------------===// 47 48 class Proc<string Name, ProcessorItineraries Itin, 49 list<SubtargetFeature> Features> 50 : Processor<Name, Itin, Features>; 51 52 def : Proc<"hexagonv2", HexagonItineraries, [ArchV2]>; 53 def : Proc<"hexagonv3", HexagonItineraries, [ArchV2, ArchV3]>; 54 def : Proc<"hexagonv4", HexagonItinerariesV4, [ArchV2, ArchV3, ArchV4]>; 55 56 // Hexagon Uses the MC printer for assembler output, so make sure the TableGen 57 // AsmWriter bits get associated with the correct class. 58 def HexagonAsmWriter : AsmWriter { 59 string AsmWriterClassName = "InstPrinter"; 60 bit isMCAsmWriter = 1; 61 } 62 63 //===----------------------------------------------------------------------===// 64 // Declare the target which we are implementing 65 //===----------------------------------------------------------------------===// 66 67 def Hexagon : Target { 68 // Pull in Instruction Info: 69 let InstructionSet = HexagonInstrInfo; 70 71 let AssemblyWriters = [HexagonAsmWriter]; 72 } 73
