1 //===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 // Functional Units 11 def LUNIT : FuncUnit; 12 def LSUNIT : FuncUnit; 13 def MUNIT : FuncUnit; 14 def SUNIT : FuncUnit; 15 16 17 // Itinerary classes 18 def ALU32 : InstrItinClass; 19 def ALU64 : InstrItinClass; 20 def CR : InstrItinClass; 21 def J : InstrItinClass; 22 def JR : InstrItinClass; 23 def LD : InstrItinClass; 24 def M : InstrItinClass; 25 def ST : InstrItinClass; 26 def S : InstrItinClass; 27 def PSEUDO : InstrItinClass; 28 29 30 def HexagonItineraries : 31 ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [ 32 InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>, 33 InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>, 34 InstrItinData<CR , [InstrStage<1, [SUNIT]>]>, 35 InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>, 36 InstrItinData<JR , [InstrStage<1, [MUNIT]>]>, 37 InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>, 38 InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>, 39 InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>, 40 InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>, 41 InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]> 42 ]>; 43 44 45 //===----------------------------------------------------------------------===// 46 // V4 Machine Info + 47 //===----------------------------------------------------------------------===// 48 49 include "HexagonScheduleV4.td" 50 51 //===----------------------------------------------------------------------===// 52 // V4 Machine Info - 53 //===----------------------------------------------------------------------===// 54
