1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Describe MIPS instructions format 12 // 13 // CPU INSTRUCTION FORMATS 14 // 15 // opcode - operation code. 16 // rs - src reg. 17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18 // rd - dst reg, only used on 3 regs instr. 19 // shamt - only used on shift instructions, contains the shift amount. 20 // funct - combined with opcode field give us an operation code. 21 // 22 //===----------------------------------------------------------------------===// 23 24 // Format specifies the encoding used by the instruction. This is part of the 25 // ad-hoc solution used to emit machine instruction encodings by our machine 26 // code emitter. 27 class Format<bits<4> val> { 28 bits<4> Value = val; 29 } 30 31 def Pseudo : Format<0>; 32 def FrmR : Format<1>; 33 def FrmI : Format<2>; 34 def FrmJ : Format<3>; 35 def FrmFR : Format<4>; 36 def FrmFI : Format<5>; 37 def FrmOther : Format<6>; // Instruction w/ a custom format 38 39 // Generic Mips Format 40 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 41 InstrItinClass itin, Format f>: Instruction 42 { 43 field bits<32> Inst; 44 Format Form = f; 45 46 let Namespace = "Mips"; 47 48 let Size = 4; 49 50 bits<6> Opcode = 0; 51 52 // Top 6 bits are the 'opcode' field 53 let Inst{31-26} = Opcode; 54 55 let OutOperandList = outs; 56 let InOperandList = ins; 57 58 let AsmString = asmstr; 59 let Pattern = pattern; 60 let Itinerary = itin; 61 62 // 63 // Attributes specific to Mips instructions... 64 // 65 bits<4> FormBits = Form.Value; 66 67 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 68 let TSFlags{3-0} = FormBits; 69 70 let DecoderNamespace = "Mips"; 71 72 field bits<32> SoftFail = 0; 73 } 74 75 // Mips Pseudo Instructions Format 76 class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>: 77 MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> { 78 let isCodeGenOnly = 1; 79 let isPseudo = 1; 80 } 81 82 //===----------------------------------------------------------------------===// 83 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 84 //===----------------------------------------------------------------------===// 85 86 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 87 list<dag> pattern, InstrItinClass itin>: 88 MipsInst<outs, ins, asmstr, pattern, itin, FrmR> 89 { 90 bits<5> rd; 91 bits<5> rs; 92 bits<5> rt; 93 bits<5> shamt; 94 bits<6> funct; 95 96 let Opcode = op; 97 let funct = _funct; 98 99 let Inst{25-21} = rs; 100 let Inst{20-16} = rt; 101 let Inst{15-11} = rd; 102 let Inst{10-6} = shamt; 103 let Inst{5-0} = funct; 104 } 105 106 //===----------------------------------------------------------------------===// 107 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 108 //===----------------------------------------------------------------------===// 109 110 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 111 InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin, FrmI> 112 { 113 bits<5> rt; 114 bits<5> rs; 115 bits<16> imm16; 116 117 let Opcode = op; 118 119 let Inst{25-21} = rs; 120 let Inst{20-16} = rt; 121 let Inst{15-0} = imm16; 122 } 123 124 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 125 list<dag> pattern, InstrItinClass itin>: 126 MipsInst<outs, ins, asmstr, pattern, itin, FrmI> 127 { 128 bits<5> rs; 129 bits<5> rt; 130 bits<16> imm16; 131 132 let Opcode = op; 133 134 let Inst{25-21} = rs; 135 let Inst{20-16} = rt; 136 let Inst{15-0} = imm16; 137 } 138 139 //===----------------------------------------------------------------------===// 140 // Format J instruction class in Mips : <|opcode|address|> 141 //===----------------------------------------------------------------------===// 142 143 class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 144 InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin, FrmJ> 145 { 146 bits<26> addr; 147 148 let Opcode = op; 149 150 let Inst{25-0} = addr; 151 } 152 153 //===----------------------------------------------------------------------===// 154 // 155 // FLOATING POINT INSTRUCTION FORMATS 156 // 157 // opcode - operation code. 158 // fs - src reg. 159 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 160 // fd - dst reg, only used on 3 regs instr. 161 // fmt - double or single precision. 162 // funct - combined with opcode field give us an operation code. 163 // 164 //===----------------------------------------------------------------------===// 165 166 //===----------------------------------------------------------------------===// 167 // Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|> 168 //===----------------------------------------------------------------------===// 169 170 class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins, 171 string asmstr, list<dag> pattern> : 172 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmFR> 173 { 174 bits<5> fd; 175 bits<5> fs; 176 bits<5> ft; 177 bits<5> fmt; 178 bits<6> funct; 179 180 let Opcode = op; 181 let funct = _funct; 182 let fmt = _fmt; 183 184 let Inst{25-21} = fmt; 185 let Inst{20-16} = ft; 186 let Inst{15-11} = fs; 187 let Inst{10-6} = fd; 188 let Inst{5-0} = funct; 189 } 190 191 //===----------------------------------------------------------------------===// 192 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 193 //===----------------------------------------------------------------------===// 194 195 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 196 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 197 { 198 bits<5> ft; 199 bits<5> base; 200 bits<16> imm16; 201 202 let Opcode = op; 203 204 let Inst{25-21} = base; 205 let Inst{20-16} = ft; 206 let Inst{15-0} = imm16; 207 } 208 209 //===----------------------------------------------------------------------===// 210 // Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|> 211 //===----------------------------------------------------------------------===// 212 213 class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> : 214 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 215 { 216 bits<5> fs; 217 bits<5> ft; 218 bits<4> cc; 219 bits<5> fmt; 220 221 let Opcode = 0x11; 222 let fmt = _fmt; 223 224 let Inst{25-21} = fmt; 225 let Inst{20-16} = ft; 226 let Inst{15-11} = fs; 227 let Inst{10-6} = 0; 228 let Inst{5-4} = 0b11; 229 let Inst{3-0} = cc; 230 } 231 232 233 class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr, 234 list<dag> pattern> : 235 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 236 { 237 bits<5> rd; 238 bits<5> rs; 239 bits<3> cc; 240 bits<1> tf; 241 242 let Opcode = 0; 243 let tf = _tf; 244 245 let Inst{25-21} = rs; 246 let Inst{20-18} = cc; 247 let Inst{17} = 0; 248 let Inst{16} = tf; 249 let Inst{15-11} = rd; 250 let Inst{10-6} = 0; 251 let Inst{5-0} = 1; 252 } 253 254 class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr, 255 list<dag> pattern> : 256 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 257 { 258 bits<5> fd; 259 bits<5> fs; 260 bits<3> cc; 261 bits<5> fmt; 262 bits<1> tf; 263 264 let Opcode = 17; 265 let fmt = _fmt; 266 let tf = _tf; 267 268 let Inst{25-21} = fmt; 269 let Inst{20-18} = cc; 270 let Inst{17} = 0; 271 let Inst{16} = tf; 272 let Inst{15-11} = fs; 273 let Inst{10-6} = fd; 274 let Inst{5-0} = 17; 275 } 276 277 // FP unary instructions without patterns. 278 class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr, 279 RegisterClass DstRC, RegisterClass SrcRC> : 280 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), 281 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> { 282 let ft = 0; 283 } 284 285 // FP unary instructions with patterns. 286 class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr, 287 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> : 288 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), 289 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), 290 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> { 291 let ft = 0; 292 } 293 294 class FFR2P<bits<6> funct, bits<5> fmt, string opstr, 295 string fmtstr, RegisterClass RC, SDNode OpNode> : 296 FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft), 297 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"), 298 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>; 299 300 // Floating point madd/msub/nmadd/nmsub. 301 class FFMADDSUB<bits<3> funct, bits<3> fmt, dag outs, dag ins, string asmstr, 302 list<dag> pattern> 303 : MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther> { 304 bits<5> fd; 305 bits<5> fr; 306 bits<5> fs; 307 bits<5> ft; 308 309 let Opcode = 0x13; 310 let Inst{25-21} = fr; 311 let Inst{20-16} = ft; 312 let Inst{15-11} = fs; 313 let Inst{10-6} = fd; 314 let Inst{5-3} = funct; 315 let Inst{2-0} = fmt; 316 } 317 318 // FP indexed load/store instructions. 319 class FFMemIdx<bits<6> funct, dag outs, dag ins, string asmstr, 320 list<dag> pattern> : 321 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 322 { 323 bits<5> base; 324 bits<5> index; 325 bits<5> fs; 326 bits<5> fd; 327 328 let Opcode = 0x13; 329 330 let Inst{25-21} = base; 331 let Inst{20-16} = index; 332 let Inst{15-11} = fs; 333 let Inst{10-6} = fd; 334 let Inst{5-0} = funct; 335 } 336
