1 //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to 11 // JIT-compile bitcode to native PowerPC. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCTargetMachine.h" 16 #include "PPCRelocations.h" 17 #include "PPC.h" 18 #include "llvm/Module.h" 19 #include "llvm/PassManager.h" 20 #include "llvm/CodeGen/JITCodeEmitter.h" 21 #include "llvm/CodeGen/MachineFunctionPass.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include "llvm/Target/TargetOptions.h" 27 using namespace llvm; 28 29 namespace { 30 class PPCCodeEmitter : public MachineFunctionPass { 31 TargetMachine &TM; 32 JITCodeEmitter &MCE; 33 MachineModuleInfo *MMI; 34 35 void getAnalysisUsage(AnalysisUsage &AU) const { 36 AU.addRequired<MachineModuleInfo>(); 37 MachineFunctionPass::getAnalysisUsage(AU); 38 } 39 40 static char ID; 41 42 /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record 43 /// its address in the function into this pointer. 44 void *MovePCtoLROffset; 45 public: 46 47 PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 48 : MachineFunctionPass(ID), TM(tm), MCE(mce) {} 49 50 /// getBinaryCodeForInstr - This function, generated by the 51 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 52 /// machine instructions. 53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 54 55 56 MachineRelocation GetRelocation(const MachineOperand &MO, 57 unsigned RelocID) const; 58 59 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr 60 unsigned getMachineOpValue(const MachineInstr &MI, 61 const MachineOperand &MO) const; 62 63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const; 64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const; 65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const; 66 67 unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const; 68 unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const; 69 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const; 70 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const; 71 72 const char *getPassName() const { return "PowerPC Machine Code Emitter"; } 73 74 /// runOnMachineFunction - emits the given MachineFunction to memory 75 /// 76 bool runOnMachineFunction(MachineFunction &MF); 77 78 /// emitBasicBlock - emits the given MachineBasicBlock to memory 79 /// 80 void emitBasicBlock(MachineBasicBlock &MBB); 81 }; 82 } 83 84 char PPCCodeEmitter::ID = 0; 85 86 /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code 87 /// to the specified MCE object. 88 FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM, 89 JITCodeEmitter &JCE) { 90 return new PPCCodeEmitter(TM, JCE); 91 } 92 93 bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 94 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 95 MF.getTarget().getRelocationModel() != Reloc::Static) && 96 "JIT relocation model must be set to static or default!"); 97 98 MMI = &getAnalysis<MachineModuleInfo>(); 99 MCE.setModuleInfo(MMI); 100 do { 101 MovePCtoLROffset = 0; 102 MCE.startFunction(MF); 103 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) 104 emitBasicBlock(*BB); 105 } while (MCE.finishFunction(MF)); 106 107 return false; 108 } 109 110 void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { 111 MCE.StartMachineBasicBlock(&MBB); 112 113 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ 114 const MachineInstr &MI = *I; 115 MCE.processDebugLoc(MI.getDebugLoc(), true); 116 switch (MI.getOpcode()) { 117 default: 118 MCE.emitWordBE(getBinaryCodeForInstr(MI)); 119 break; 120 case TargetOpcode::PROLOG_LABEL: 121 case TargetOpcode::EH_LABEL: 122 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 123 break; 124 case TargetOpcode::IMPLICIT_DEF: 125 case TargetOpcode::KILL: 126 break; // pseudo opcode, no side effects 127 case PPC::MovePCtoLR: 128 case PPC::MovePCtoLR8: 129 assert(TM.getRelocationModel() == Reloc::PIC_); 130 MovePCtoLROffset = (void*)MCE.getCurrentPCValue(); 131 MCE.emitWordBE(0x48000005); // bl 1 132 break; 133 } 134 MCE.processDebugLoc(MI.getDebugLoc(), false); 135 } 136 } 137 138 unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI, 139 unsigned OpNo) const { 140 const MachineOperand &MO = MI.getOperand(OpNo); 141 assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MTCRF8 || 142 MI.getOpcode() == PPC::MFOCRF) && 143 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 144 return 0x80 >> getPPCRegisterNumbering(MO.getReg()); 145 } 146 147 MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO, 148 unsigned RelocID) const { 149 // If in PIC mode, we need to encode the negated address of the 150 // 'movepctolr' into the unrelocated field. After relocation, we'll have 151 // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm 152 // field, we get &gv. This doesn't happen for branch relocations, which are 153 // always implicitly pc relative. 154 intptr_t Cst = 0; 155 if (TM.getRelocationModel() == Reloc::PIC_) { 156 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?"); 157 Cst = -(intptr_t)MovePCtoLROffset - 4; 158 } 159 160 if (MO.isGlobal()) 161 return MachineRelocation::getGV(MCE.getCurrentPCOffset(), RelocID, 162 const_cast<GlobalValue *>(MO.getGlobal()), 163 Cst, isa<Function>(MO.getGlobal())); 164 if (MO.isSymbol()) 165 return MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 166 RelocID, MO.getSymbolName(), Cst); 167 if (MO.isCPI()) 168 return MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 169 RelocID, MO.getIndex(), Cst); 170 171 if (MO.isMBB()) 172 return MachineRelocation::getBB(MCE.getCurrentPCOffset(), 173 RelocID, MO.getMBB()); 174 175 assert(MO.isJTI()); 176 return MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 177 RelocID, MO.getIndex(), Cst); 178 } 179 180 unsigned PPCCodeEmitter::getDirectBrEncoding(const MachineInstr &MI, 181 unsigned OpNo) const { 182 const MachineOperand &MO = MI.getOperand(OpNo); 183 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 184 185 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bx)); 186 return 0; 187 } 188 189 unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI, 190 unsigned OpNo) const { 191 const MachineOperand &MO = MI.getOperand(OpNo); 192 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bcx)); 193 return 0; 194 } 195 196 unsigned PPCCodeEmitter::getHA16Encoding(const MachineInstr &MI, 197 unsigned OpNo) const { 198 const MachineOperand &MO = MI.getOperand(OpNo); 199 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 200 201 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_high)); 202 return 0; 203 } 204 205 unsigned PPCCodeEmitter::getLO16Encoding(const MachineInstr &MI, 206 unsigned OpNo) const { 207 const MachineOperand &MO = MI.getOperand(OpNo); 208 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 209 210 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low)); 211 return 0; 212 } 213 214 unsigned PPCCodeEmitter::getMemRIEncoding(const MachineInstr &MI, 215 unsigned OpNo) const { 216 // Encode (imm, reg) as a memri, which has the low 16-bits as the 217 // displacement and the next 5 bits as the register #. 218 assert(MI.getOperand(OpNo+1).isReg()); 219 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16; 220 221 const MachineOperand &MO = MI.getOperand(OpNo); 222 if (MO.isImm()) 223 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits; 224 225 // Add a fixup for the displacement field. 226 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low)); 227 return RegBits; 228 } 229 230 unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI, 231 unsigned OpNo) const { 232 // Encode (imm, reg) as a memrix, which has the low 14-bits as the 233 // displacement and the next 5 bits as the register #. 234 assert(MI.getOperand(OpNo+1).isReg()); 235 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14; 236 237 const MachineOperand &MO = MI.getOperand(OpNo); 238 if (MO.isImm()) 239 return (getMachineOpValue(MI, MO) & 0x3FFF) | RegBits; 240 241 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix)); 242 return RegBits; 243 } 244 245 246 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, 247 const MachineOperand &MO) const { 248 249 if (MO.isReg()) { 250 // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. 251 // The GPR operand should come through here though. 252 assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MTCRF8 && 253 MI.getOpcode() != PPC::MFOCRF) || 254 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 255 return getPPCRegisterNumbering(MO.getReg()); 256 } 257 258 assert(MO.isImm() && 259 "Relocation required in an instruction that we cannot encode!"); 260 return MO.getImm(); 261 } 262 263 #include "PPCGenCodeEmitter.inc" 264