1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // 12 // PowerPC instruction formats 13 14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 18 bit PPC64 = 0; // Default value, override with isPPC64 19 20 let Namespace = "PPC"; 21 let Inst{0-5} = opcode; 22 let OutOperandList = OOL; 23 let InOperandList = IOL; 24 let AsmString = asmstr; 25 let Itinerary = itin; 26 27 bits<1> PPC970_First = 0; 28 bits<1> PPC970_Single = 0; 29 bits<1> PPC970_Cracked = 0; 30 bits<3> PPC970_Unit = 0; 31 32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 33 /// these must be reflected there! See comments there for what these are. 34 let TSFlags{0} = PPC970_First; 35 let TSFlags{1} = PPC970_Single; 36 let TSFlags{2} = PPC970_Cracked; 37 let TSFlags{5-3} = PPC970_Unit; 38 } 39 40 class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 41 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 42 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 43 class PPC970_MicroCode; 44 45 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 46 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 47 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 48 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 49 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 50 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 51 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 52 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 53 54 // Two joined instructions; used to emit two adjacent instructions as one. 55 // The itinerary from the first instruction is used for scheduling and 56 // classification. 57 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 58 InstrItinClass itin> 59 : Instruction { 60 field bits<64> Inst; 61 62 bit PPC64 = 0; // Default value, override with isPPC64 63 64 let Namespace = "PPC"; 65 let Inst{0-5} = opcode1; 66 let Inst{32-37} = opcode2; 67 let OutOperandList = OOL; 68 let InOperandList = IOL; 69 let AsmString = asmstr; 70 let Itinerary = itin; 71 72 bits<1> PPC970_First = 0; 73 bits<1> PPC970_Single = 0; 74 bits<1> PPC970_Cracked = 0; 75 bits<3> PPC970_Unit = 0; 76 77 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 78 /// these must be reflected there! See comments there for what these are. 79 let TSFlags{0} = PPC970_First; 80 let TSFlags{1} = PPC970_Single; 81 let TSFlags{2} = PPC970_Cracked; 82 let TSFlags{5-3} = PPC970_Unit; 83 } 84 85 // 1.7.1 I-Form 86 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 87 InstrItinClass itin, list<dag> pattern> 88 : I<opcode, OOL, IOL, asmstr, itin> { 89 let Pattern = pattern; 90 bits<24> LI; 91 92 let Inst{6-29} = LI; 93 let Inst{30} = aa; 94 let Inst{31} = lk; 95 } 96 97 // 1.7.2 B-Form 98 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 99 : I<opcode, OOL, IOL, asmstr, BrB> { 100 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 101 bits<3> CR; 102 bits<14> BD; 103 104 bits<5> BI; 105 let BI{0-1} = BIBO{5-6}; 106 let BI{2-4} = CR{0-2}; 107 108 let Inst{6-10} = BIBO{4-0}; 109 let Inst{11-15} = BI; 110 let Inst{16-29} = BD; 111 let Inst{30} = aa; 112 let Inst{31} = lk; 113 } 114 115 116 // 1.7.4 D-Form 117 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 118 InstrItinClass itin, list<dag> pattern> 119 : I<opcode, OOL, IOL, asmstr, itin> { 120 bits<5> A; 121 bits<5> B; 122 bits<16> C; 123 124 let Pattern = pattern; 125 126 let Inst{6-10} = A; 127 let Inst{11-15} = B; 128 let Inst{16-31} = C; 129 } 130 131 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 132 InstrItinClass itin, list<dag> pattern> 133 : I<opcode, OOL, IOL, asmstr, itin> { 134 bits<5> A; 135 bits<21> Addr; 136 137 let Pattern = pattern; 138 139 let Inst{6-10} = A; 140 let Inst{11-15} = Addr{20-16}; // Base Reg 141 let Inst{16-31} = Addr{15-0}; // Displacement 142 } 143 144 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 145 InstrItinClass itin, list<dag> pattern> 146 : I<opcode, OOL, IOL, asmstr, itin> { 147 bits<5> A; 148 bits<16> C; 149 bits<5> B; 150 151 let Pattern = pattern; 152 153 let Inst{6-10} = A; 154 let Inst{11-15} = B; 155 let Inst{16-31} = C; 156 } 157 158 159 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 160 InstrItinClass itin, list<dag> pattern> 161 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>; 162 163 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 164 InstrItinClass itin, list<dag> pattern> 165 : I<opcode, OOL, IOL, asmstr, itin> { 166 bits<5> A; 167 bits<16> B; 168 169 let Pattern = pattern; 170 171 let Inst{6-10} = A; 172 let Inst{11-15} = 0; 173 let Inst{16-31} = B; 174 } 175 176 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 177 InstrItinClass itin, list<dag> pattern> 178 : I<opcode, OOL, IOL, asmstr, itin> { 179 bits<5> B; 180 bits<5> A; 181 bits<16> C; 182 183 let Pattern = pattern; 184 185 let Inst{6-10} = A; 186 let Inst{11-15} = B; 187 let Inst{16-31} = C; 188 } 189 190 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 191 InstrItinClass itin, list<dag> pattern> 192 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 193 let A = 0; 194 let Addr = 0; 195 } 196 197 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 198 dag OOL, dag IOL, string asmstr, 199 InstrItinClass itin, list<dag> pattern> 200 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 201 bits<5> A; 202 bits<21> Addr; 203 204 let Pattern = pattern; 205 bits<24> LI; 206 207 let Inst{6-29} = LI; 208 let Inst{30} = aa; 209 let Inst{31} = lk; 210 211 let Inst{38-42} = A; 212 let Inst{43-47} = Addr{20-16}; // Base Reg 213 let Inst{48-63} = Addr{15-0}; // Displacement 214 } 215 216 // This is used to emit BL8+NOP. 217 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 218 dag OOL, dag IOL, string asmstr, 219 InstrItinClass itin, list<dag> pattern> 220 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 221 OOL, IOL, asmstr, itin, pattern> { 222 let A = 0; 223 let Addr = 0; 224 } 225 226 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 227 InstrItinClass itin> 228 : I<opcode, OOL, IOL, asmstr, itin> { 229 bits<3> BF; 230 bits<1> L; 231 bits<5> RA; 232 bits<16> I; 233 234 let Inst{6-8} = BF; 235 let Inst{9} = 0; 236 let Inst{10} = L; 237 let Inst{11-15} = RA; 238 let Inst{16-31} = I; 239 } 240 241 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 242 InstrItinClass itin> 243 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 244 let L = PPC64; 245 } 246 247 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 248 InstrItinClass itin> 249 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 250 251 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 252 InstrItinClass itin> 253 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 254 let L = PPC64; 255 } 256 257 258 // 1.7.5 DS-Form 259 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 260 InstrItinClass itin, list<dag> pattern> 261 : I<opcode, OOL, IOL, asmstr, itin> { 262 bits<5> RST; 263 bits<19> DS_RA; 264 265 let Pattern = pattern; 266 267 let Inst{6-10} = RST; 268 let Inst{11-15} = DS_RA{18-14}; // Register # 269 let Inst{16-29} = DS_RA{13-0}; // Displacement. 270 let Inst{30-31} = xo; 271 } 272 273 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 274 InstrItinClass itin, list<dag> pattern> 275 : I<opcode, OOL, IOL, asmstr, itin> { 276 bits<5> RST; 277 bits<14> DS; 278 bits<5> RA; 279 280 let Pattern = pattern; 281 282 let Inst{6-10} = RST; 283 let Inst{11-15} = RA; 284 let Inst{16-29} = DS; 285 let Inst{30-31} = xo; 286 } 287 288 // 1.7.6 X-Form 289 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 290 InstrItinClass itin, list<dag> pattern> 291 : I<opcode, OOL, IOL, asmstr, itin> { 292 bits<5> RST; 293 bits<5> A; 294 bits<5> B; 295 296 let Pattern = pattern; 297 298 bit RC = 0; // set by isDOT 299 300 let Inst{6-10} = RST; 301 let Inst{11-15} = A; 302 let Inst{16-20} = B; 303 let Inst{21-30} = xo; 304 let Inst{31} = RC; 305 } 306 307 // This is the same as XForm_base_r3xo, but the first two operands are swapped 308 // when code is emitted. 309 class XForm_base_r3xo_swapped 310 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 311 InstrItinClass itin> 312 : I<opcode, OOL, IOL, asmstr, itin> { 313 bits<5> A; 314 bits<5> RST; 315 bits<5> B; 316 317 bit RC = 0; // set by isDOT 318 319 let Inst{6-10} = RST; 320 let Inst{11-15} = A; 321 let Inst{16-20} = B; 322 let Inst{21-30} = xo; 323 let Inst{31} = RC; 324 } 325 326 327 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 328 InstrItinClass itin, list<dag> pattern> 329 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 330 331 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 332 InstrItinClass itin, list<dag> pattern> 333 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 334 let Pattern = pattern; 335 } 336 337 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 338 InstrItinClass itin, list<dag> pattern> 339 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 340 341 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 342 InstrItinClass itin, list<dag> pattern> 343 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 344 let Pattern = pattern; 345 } 346 347 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 348 InstrItinClass itin, list<dag> pattern> 349 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 350 let B = 0; 351 let Pattern = pattern; 352 } 353 354 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 355 InstrItinClass itin> 356 : I<opcode, OOL, IOL, asmstr, itin> { 357 bits<3> BF; 358 bits<1> L; 359 bits<5> RA; 360 bits<5> RB; 361 362 let Inst{6-8} = BF; 363 let Inst{9} = 0; 364 let Inst{10} = L; 365 let Inst{11-15} = RA; 366 let Inst{16-20} = RB; 367 let Inst{21-30} = xo; 368 let Inst{31} = 0; 369 } 370 371 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 372 InstrItinClass itin> 373 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 374 let L = PPC64; 375 } 376 377 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 378 InstrItinClass itin> 379 : I<opcode, OOL, IOL, asmstr, itin> { 380 bits<3> BF; 381 bits<5> FRA; 382 bits<5> FRB; 383 384 let Inst{6-8} = BF; 385 let Inst{9-10} = 0; 386 let Inst{11-15} = FRA; 387 let Inst{16-20} = FRB; 388 let Inst{21-30} = xo; 389 let Inst{31} = 0; 390 } 391 392 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 393 InstrItinClass itin, list<dag> pattern> 394 : I<opcode, OOL, IOL, asmstr, itin> { 395 let Pattern = pattern; 396 let Inst{6-10} = 31; 397 let Inst{11-15} = 0; 398 let Inst{16-20} = 0; 399 let Inst{21-30} = xo; 400 let Inst{31} = 0; 401 } 402 403 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 404 string asmstr, InstrItinClass itin, list<dag> pattern> 405 : I<opcode, OOL, IOL, asmstr, itin> { 406 let Pattern = pattern; 407 let Inst{6-10} = 0; 408 let Inst{11-15} = 0; 409 let Inst{16-20} = 0; 410 let Inst{21-30} = xo; 411 let Inst{31} = 0; 412 } 413 414 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 415 InstrItinClass itin, list<dag> pattern> 416 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 417 } 418 419 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 420 InstrItinClass itin, list<dag> pattern> 421 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 422 let A = 0; 423 } 424 425 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 426 InstrItinClass itin, list<dag> pattern> 427 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 428 } 429 430 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 431 // numbers presumably relates to some document, but I haven't found it. 432 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 433 InstrItinClass itin, list<dag> pattern> 434 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 435 let Pattern = pattern; 436 437 bit RC = 0; // set by isDOT 438 439 let Inst{6-10} = RST; 440 let Inst{11-20} = 0; 441 let Inst{21-30} = xo; 442 let Inst{31} = RC; 443 } 444 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 445 InstrItinClass itin, list<dag> pattern> 446 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 447 let Pattern = pattern; 448 bits<5> FM; 449 450 bit RC = 0; // set by isDOT 451 452 let Inst{6-10} = FM; 453 let Inst{11-20} = 0; 454 let Inst{21-30} = xo; 455 let Inst{31} = RC; 456 } 457 458 // DCB_Form - Form X instruction, used for dcb* instructions. 459 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 460 InstrItinClass itin, list<dag> pattern> 461 : I<31, OOL, IOL, asmstr, itin> { 462 bits<5> A; 463 bits<5> B; 464 465 let Pattern = pattern; 466 467 let Inst{6-10} = immfield; 468 let Inst{11-15} = A; 469 let Inst{16-20} = B; 470 let Inst{21-30} = xo; 471 let Inst{31} = 0; 472 } 473 474 475 // DSS_Form - Form X instruction, used for altivec dss* instructions. 476 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, 477 InstrItinClass itin, list<dag> pattern> 478 : I<31, OOL, IOL, asmstr, itin> { 479 bits<1> T; 480 bits<2> STRM; 481 bits<5> A; 482 bits<5> B; 483 484 let Pattern = pattern; 485 486 let Inst{6} = T; 487 let Inst{7-8} = 0; 488 let Inst{9-10} = STRM; 489 let Inst{11-15} = A; 490 let Inst{16-20} = B; 491 let Inst{21-30} = xo; 492 let Inst{31} = 0; 493 } 494 495 // 1.7.7 XL-Form 496 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 497 InstrItinClass itin, list<dag> pattern> 498 : I<opcode, OOL, IOL, asmstr, itin> { 499 bits<5> CRD; 500 bits<5> CRA; 501 bits<5> CRB; 502 503 let Pattern = pattern; 504 505 let Inst{6-10} = CRD; 506 let Inst{11-15} = CRA; 507 let Inst{16-20} = CRB; 508 let Inst{21-30} = xo; 509 let Inst{31} = 0; 510 } 511 512 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 513 InstrItinClass itin, list<dag> pattern> 514 : I<opcode, OOL, IOL, asmstr, itin> { 515 bits<5> CRD; 516 517 let Pattern = pattern; 518 519 let Inst{6-10} = CRD; 520 let Inst{11-15} = CRD; 521 let Inst{16-20} = CRD; 522 let Inst{21-30} = xo; 523 let Inst{31} = 0; 524 } 525 526 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 527 InstrItinClass itin, list<dag> pattern> 528 : I<opcode, OOL, IOL, asmstr, itin> { 529 bits<5> BO; 530 bits<5> BI; 531 bits<2> BH; 532 533 let Pattern = pattern; 534 535 let Inst{6-10} = BO; 536 let Inst{11-15} = BI; 537 let Inst{16-18} = 0; 538 let Inst{19-20} = BH; 539 let Inst{21-30} = xo; 540 let Inst{31} = lk; 541 } 542 543 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 544 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 545 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 546 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 547 bits<3> CR; 548 549 let BO = BIBO{2-6}; 550 let BI{0-1} = BIBO{0-1}; 551 let BI{2-4} = CR; 552 let BH = 0; 553 } 554 555 556 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 557 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 558 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 559 let BO = bo; 560 let BI = bi; 561 let BH = 0; 562 } 563 564 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 565 InstrItinClass itin> 566 : I<opcode, OOL, IOL, asmstr, itin> { 567 bits<3> BF; 568 bits<3> BFA; 569 570 let Inst{6-8} = BF; 571 let Inst{9-10} = 0; 572 let Inst{11-13} = BFA; 573 let Inst{14-15} = 0; 574 let Inst{16-20} = 0; 575 let Inst{21-30} = xo; 576 let Inst{31} = 0; 577 } 578 579 // 1.7.8 XFX-Form 580 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 581 InstrItinClass itin> 582 : I<opcode, OOL, IOL, asmstr, itin> { 583 bits<5> RT; 584 bits<10> SPR; 585 586 let Inst{6-10} = RT; 587 let Inst{11} = SPR{4}; 588 let Inst{12} = SPR{3}; 589 let Inst{13} = SPR{2}; 590 let Inst{14} = SPR{1}; 591 let Inst{15} = SPR{0}; 592 let Inst{16} = SPR{9}; 593 let Inst{17} = SPR{8}; 594 let Inst{18} = SPR{7}; 595 let Inst{19} = SPR{6}; 596 let Inst{20} = SPR{5}; 597 let Inst{21-30} = xo; 598 let Inst{31} = 0; 599 } 600 601 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 602 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 603 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 604 let SPR = spr; 605 } 606 607 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 608 InstrItinClass itin> 609 : I<opcode, OOL, IOL, asmstr, itin> { 610 bits<5> RT; 611 612 let Inst{6-10} = RT; 613 let Inst{11-20} = 0; 614 let Inst{21-30} = xo; 615 let Inst{31} = 0; 616 } 617 618 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 619 InstrItinClass itin> 620 : I<opcode, OOL, IOL, asmstr, itin> { 621 bits<8> FXM; 622 bits<5> ST; 623 624 let Inst{6-10} = ST; 625 let Inst{11} = 0; 626 let Inst{12-19} = FXM; 627 let Inst{20} = 0; 628 let Inst{21-30} = xo; 629 let Inst{31} = 0; 630 } 631 632 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 633 InstrItinClass itin> 634 : I<opcode, OOL, IOL, asmstr, itin> { 635 bits<5> ST; 636 bits<8> FXM; 637 638 let Inst{6-10} = ST; 639 let Inst{11} = 1; 640 let Inst{12-19} = FXM; 641 let Inst{20} = 0; 642 let Inst{21-30} = xo; 643 let Inst{31} = 0; 644 } 645 646 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 647 InstrItinClass itin> 648 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 649 650 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 651 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 652 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 653 let SPR = spr; 654 } 655 656 // XFL-Form - MTFSF 657 // This is probably 1.7.9, but I don't have the reference that uses this 658 // numbering scheme... 659 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 660 string cstr, InstrItinClass itin, list<dag>pattern> 661 : I<opcode, OOL, IOL, asmstr, itin> { 662 bits<8> FM; 663 bits<5> RT; 664 665 bit RC = 0; // set by isDOT 666 let Pattern = pattern; 667 let Constraints = cstr; 668 669 let Inst{6} = 0; 670 let Inst{7-14} = FM; 671 let Inst{15} = 0; 672 let Inst{16-20} = RT; 673 let Inst{21-30} = xo; 674 let Inst{31} = RC; 675 } 676 677 // 1.7.10 XS-Form - SRADI. 678 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 679 InstrItinClass itin, list<dag> pattern> 680 : I<opcode, OOL, IOL, asmstr, itin> { 681 bits<5> A; 682 bits<5> RS; 683 bits<6> SH; 684 685 bit RC = 0; // set by isDOT 686 let Pattern = pattern; 687 688 let Inst{6-10} = RS; 689 let Inst{11-15} = A; 690 let Inst{16-20} = SH{4,3,2,1,0}; 691 let Inst{21-29} = xo; 692 let Inst{30} = SH{5}; 693 let Inst{31} = RC; 694 } 695 696 // 1.7.11 XO-Form 697 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 698 InstrItinClass itin, list<dag> pattern> 699 : I<opcode, OOL, IOL, asmstr, itin> { 700 bits<5> RT; 701 bits<5> RA; 702 bits<5> RB; 703 704 let Pattern = pattern; 705 706 bit RC = 0; // set by isDOT 707 708 let Inst{6-10} = RT; 709 let Inst{11-15} = RA; 710 let Inst{16-20} = RB; 711 let Inst{21} = oe; 712 let Inst{22-30} = xo; 713 let Inst{31} = RC; 714 } 715 716 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 717 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 718 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 719 let RB = 0; 720 } 721 722 // 1.7.12 A-Form 723 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 724 InstrItinClass itin, list<dag> pattern> 725 : I<opcode, OOL, IOL, asmstr, itin> { 726 bits<5> FRT; 727 bits<5> FRA; 728 bits<5> FRC; 729 bits<5> FRB; 730 731 let Pattern = pattern; 732 733 bit RC = 0; // set by isDOT 734 735 let Inst{6-10} = FRT; 736 let Inst{11-15} = FRA; 737 let Inst{16-20} = FRB; 738 let Inst{21-25} = FRC; 739 let Inst{26-30} = xo; 740 let Inst{31} = RC; 741 } 742 743 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 744 InstrItinClass itin, list<dag> pattern> 745 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 746 let FRC = 0; 747 } 748 749 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 750 InstrItinClass itin, list<dag> pattern> 751 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 752 let FRB = 0; 753 } 754 755 // 1.7.13 M-Form 756 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 757 InstrItinClass itin, list<dag> pattern> 758 : I<opcode, OOL, IOL, asmstr, itin> { 759 bits<5> RA; 760 bits<5> RS; 761 bits<5> RB; 762 bits<5> MB; 763 bits<5> ME; 764 765 let Pattern = pattern; 766 767 bit RC = 0; // set by isDOT 768 769 let Inst{6-10} = RS; 770 let Inst{11-15} = RA; 771 let Inst{16-20} = RB; 772 let Inst{21-25} = MB; 773 let Inst{26-30} = ME; 774 let Inst{31} = RC; 775 } 776 777 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 778 InstrItinClass itin, list<dag> pattern> 779 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 780 } 781 782 // 1.7.14 MD-Form 783 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 784 InstrItinClass itin, list<dag> pattern> 785 : I<opcode, OOL, IOL, asmstr, itin> { 786 bits<5> RA; 787 bits<5> RS; 788 bits<6> SH; 789 bits<6> MBE; 790 791 let Pattern = pattern; 792 793 bit RC = 0; // set by isDOT 794 795 let Inst{6-10} = RS; 796 let Inst{11-15} = RA; 797 let Inst{16-20} = SH{4,3,2,1,0}; 798 let Inst{21-26} = MBE{4,3,2,1,0,5}; 799 let Inst{27-29} = xo; 800 let Inst{30} = SH{5}; 801 let Inst{31} = RC; 802 } 803 804 805 806 // E-1 VA-Form 807 808 // VAForm_1 - DACB ordering. 809 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 810 InstrItinClass itin, list<dag> pattern> 811 : I<4, OOL, IOL, asmstr, itin> { 812 bits<5> VD; 813 bits<5> VA; 814 bits<5> VC; 815 bits<5> VB; 816 817 let Pattern = pattern; 818 819 let Inst{6-10} = VD; 820 let Inst{11-15} = VA; 821 let Inst{16-20} = VB; 822 let Inst{21-25} = VC; 823 let Inst{26-31} = xo; 824 } 825 826 // VAForm_1a - DABC ordering. 827 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 828 InstrItinClass itin, list<dag> pattern> 829 : I<4, OOL, IOL, asmstr, itin> { 830 bits<5> VD; 831 bits<5> VA; 832 bits<5> VB; 833 bits<5> VC; 834 835 let Pattern = pattern; 836 837 let Inst{6-10} = VD; 838 let Inst{11-15} = VA; 839 let Inst{16-20} = VB; 840 let Inst{21-25} = VC; 841 let Inst{26-31} = xo; 842 } 843 844 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 845 InstrItinClass itin, list<dag> pattern> 846 : I<4, OOL, IOL, asmstr, itin> { 847 bits<5> VD; 848 bits<5> VA; 849 bits<5> VB; 850 bits<4> SH; 851 852 let Pattern = pattern; 853 854 let Inst{6-10} = VD; 855 let Inst{11-15} = VA; 856 let Inst{16-20} = VB; 857 let Inst{21} = 0; 858 let Inst{22-25} = SH; 859 let Inst{26-31} = xo; 860 } 861 862 // E-2 VX-Form 863 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 864 InstrItinClass itin, list<dag> pattern> 865 : I<4, OOL, IOL, asmstr, itin> { 866 bits<5> VD; 867 bits<5> VA; 868 bits<5> VB; 869 870 let Pattern = pattern; 871 872 let Inst{6-10} = VD; 873 let Inst{11-15} = VA; 874 let Inst{16-20} = VB; 875 let Inst{21-31} = xo; 876 } 877 878 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 879 InstrItinClass itin, list<dag> pattern> 880 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 881 let VA = VD; 882 let VB = VD; 883 } 884 885 886 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 887 InstrItinClass itin, list<dag> pattern> 888 : I<4, OOL, IOL, asmstr, itin> { 889 bits<5> VD; 890 bits<5> VB; 891 892 let Pattern = pattern; 893 894 let Inst{6-10} = VD; 895 let Inst{11-15} = 0; 896 let Inst{16-20} = VB; 897 let Inst{21-31} = xo; 898 } 899 900 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 901 InstrItinClass itin, list<dag> pattern> 902 : I<4, OOL, IOL, asmstr, itin> { 903 bits<5> VD; 904 bits<5> IMM; 905 906 let Pattern = pattern; 907 908 let Inst{6-10} = VD; 909 let Inst{11-15} = IMM; 910 let Inst{16-20} = 0; 911 let Inst{21-31} = xo; 912 } 913 914 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 915 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 916 InstrItinClass itin, list<dag> pattern> 917 : I<4, OOL, IOL, asmstr, itin> { 918 bits<5> VD; 919 920 let Pattern = pattern; 921 922 let Inst{6-10} = VD; 923 let Inst{11-15} = 0; 924 let Inst{16-20} = 0; 925 let Inst{21-31} = xo; 926 } 927 928 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 929 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 930 InstrItinClass itin, list<dag> pattern> 931 : I<4, OOL, IOL, asmstr, itin> { 932 bits<5> VB; 933 934 let Pattern = pattern; 935 936 let Inst{6-10} = 0; 937 let Inst{11-15} = 0; 938 let Inst{16-20} = VB; 939 let Inst{21-31} = xo; 940 } 941 942 // E-4 VXR-Form 943 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 944 InstrItinClass itin, list<dag> pattern> 945 : I<4, OOL, IOL, asmstr, itin> { 946 bits<5> VD; 947 bits<5> VA; 948 bits<5> VB; 949 bit RC = 0; 950 951 let Pattern = pattern; 952 953 let Inst{6-10} = VD; 954 let Inst{11-15} = VA; 955 let Inst{16-20} = VB; 956 let Inst{21} = RC; 957 let Inst{22-31} = xo; 958 } 959 960 //===----------------------------------------------------------------------===// 961 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 962 : I<0, OOL, IOL, asmstr, NoItinerary> { 963 let PPC64 = 0; 964 let Pattern = pattern; 965 let Inst{31-0} = 0; 966 } 967
