1 //===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the itinerary class data for the G4+ (7450) processor. 11 // 12 //===----------------------------------------------------------------------===// 13 14 def IU3 : FuncUnit; // integer unit 3 (7450 simple) 15 def IU4 : FuncUnit; // integer unit 4 (7450 simple) 16 17 def G4PlusItineraries : ProcessorItineraries< 18 [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [ 19 InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, 20 InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, 21 InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>, 22 InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>, 23 InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>, 24 InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>, 25 InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>, 26 InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>, 27 InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>, 28 InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, 29 InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, 30 InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, 31 InstrItinData<BrB , [InstrStage<1, [BPU]>]>, 32 InstrItinData<BrCR , [InstrStage<2, [IU2]>]>, 33 InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>, 34 InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>, 35 InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, 36 InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>, 37 InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>, 38 InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>, 39 InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>, 40 InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>, 41 InstrItinData<LdStUX , [InstrStage<3, [SLU]>]>, 42 InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>, 43 InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>, 44 InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>, 45 InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>, 46 InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>, 47 InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>, 48 InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>, 49 InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>, 50 InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>, 51 InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>, 52 InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>, 53 InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>, 54 InstrItinData<SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>, 55 InstrItinData<SprMFSR , [InstrStage<4, [IU2]>]>, 56 InstrItinData<SprMTMSR , [InstrStage<2, [IU2]>]>, 57 InstrItinData<SprMTSR , [InstrStage<2, [IU2]>]>, 58 InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>, 59 InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>, 60 InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>, 61 InstrItinData<SprMFSPR , [InstrStage<4, [IU2]>]>, 62 InstrItinData<SprMFTB , [InstrStage<5, [IU2]>]>, 63 InstrItinData<SprMTSPR , [InstrStage<2, [IU2]>]>, 64 InstrItinData<SprMTSRIN , [InstrStage<2, [IU2]>]>, 65 InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, 66 InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>, 67 InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>, 68 InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>, 69 InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>, 70 InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>, 71 InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>, 72 InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>, 73 InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>, 74 InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>, 75 InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>, 76 InstrItinData<VecComplex , [InstrStage<4, [VIU2]>]>, 77 InstrItinData<VecPerm , [InstrStage<2, [VPU]>]>, 78 InstrItinData<VecFPRound , [InstrStage<4, [VIU1]>]>, 79 InstrItinData<VecVSL , [InstrStage<2, [VPU]>]>, 80 InstrItinData<VecVSR , [InstrStage<2, [VPU]>]> 81 ]>; 82
