1 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM 2 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB 3 4 @a = global i8 1, align 1 5 @b = global i16 2, align 2 6 7 define void @t1() nounwind uwtable ssp { 8 ; ARM: t1 9 ; ARM: ldrb 10 ; ARM-NOT: uxtb 11 ; THUMB: t1 12 ; THUMB: ldrb 13 ; THUMB-NOT: uxtb 14 %1 = load i8* @a, align 1 15 call void @foo1(i8 zeroext %1) 16 ret void 17 } 18 19 define void @t2() nounwind uwtable ssp { 20 ; ARM: t2 21 ; ARM: ldrh 22 ; ARM-NOT: uxth 23 ; THUMB: t2 24 ; THUMB: ldrh 25 ; THUMB-NOT: uxth 26 %1 = load i16* @b, align 2 27 call void @foo2(i16 zeroext %1) 28 ret void 29 } 30 31 declare void @foo1(i8 zeroext) 32 declare void @foo2(i16 zeroext) 33 34 define i32 @t3() nounwind uwtable ssp { 35 ; ARM: t3 36 ; ARM: ldrb 37 ; ARM-NOT: uxtb 38 ; THUMB: t3 39 ; THUMB: ldrb 40 ; THUMB-NOT: uxtb 41 %1 = load i8* @a, align 1 42 %2 = zext i8 %1 to i32 43 ret i32 %2 44 } 45 46 define i32 @t4() nounwind uwtable ssp { 47 ; ARM: t4 48 ; ARM: ldrh 49 ; ARM-NOT: uxth 50 ; THUMB: t4 51 ; THUMB: ldrh 52 ; THUMB-NOT: uxth 53 %1 = load i16* @b, align 2 54 %2 = zext i16 %1 to i32 55 ret i32 %2 56 } 57 58 define i32 @t5() nounwind uwtable ssp { 59 ; ARM: t5 60 ; ARM: ldrsh 61 ; ARM-NOT: sxth 62 ; THUMB: t5 63 ; THUMB: ldrsh 64 ; THUMB-NOT: sxth 65 %1 = load i16* @b, align 2 66 %2 = sext i16 %1 to i32 67 ret i32 %2 68 } 69 70 define i32 @t6() nounwind uwtable ssp { 71 ; ARM: t6 72 ; ARM: ldrsb 73 ; ARM-NOT: sxtb 74 ; THUMB: t6 75 ; THUMB: ldrsb 76 ; THUMB-NOT: sxtb 77 %1 = load i8* @a, align 2 78 %2 = sext i8 %1 to i32 79 ret i32 %2 80 } 81
