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      1 ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM
      2 ; RUN: llc < %s -mtriple=thumb-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2
      3 ; rdar://8662825
      4 
      5 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
      6 ; ARM: t1:
      7 ; ARM: sub r0, r1, #-2147483647
      8 ; ARM: movgt r0, r1
      9 
     10 ; T2: t1:
     11 ; T2: mvn r0, #-2147483648
     12 ; T2: add r0, r1
     13 ; T2: movgt r0, r1
     14   %tmp1 = icmp sgt i32 %c, 10
     15   %tmp2 = select i1 %tmp1, i32 0, i32 2147483647
     16   %tmp3 = add i32 %tmp2, %b
     17   ret i32 %tmp3
     18 }
     19 
     20 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
     21 ; ARM: t2:
     22 ; ARM: sub r0, r1, #10
     23 ; ARM: movgt r0, r1
     24 
     25 ; T2: t2:
     26 ; T2: sub.w r0, r1, #10
     27 ; T2: movgt r0, r1
     28   %tmp1 = icmp sgt i32 %c, 10
     29   %tmp2 = select i1 %tmp1, i32 0, i32 10
     30   %tmp3 = sub i32 %b, %tmp2
     31   ret i32 %tmp3
     32 }
     33 
     34 define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
     35 ; ARM: t3:
     36 ; ARM: mvnlt r2, #0
     37 ; ARM: and r0, r2, r3
     38 
     39 ; T2: t3:
     40 ; T2: movlt.w r2, #-1
     41 ; T2: and.w r0, r2, r3
     42   %cond = icmp slt i32 %a, %b
     43   %z = select i1 %cond, i32 -1, i32 %x
     44   %s = and i32 %z, %y
     45  ret i32 %s
     46 }
     47 
     48 define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
     49 ; ARM: t4:
     50 ; ARM: movlt r2, #0
     51 ; ARM: orr r0, r2, r3
     52 
     53 ; T2: t4:
     54 ; T2: movlt r2, #0
     55 ; T2: orr.w r0, r2, r3
     56   %cond = icmp slt i32 %a, %b
     57   %z = select i1 %cond, i32 0, i32 %x
     58   %s = or i32 %z, %y
     59  ret i32 %s
     60 }
     61 
     62 define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
     63 entry:
     64 ; ARM: t5:
     65 ; ARM-NOT: moveq
     66 ; ARM: orreq r2, r2, #1
     67 
     68 ; T2: t5:
     69 ; T2-NOT: moveq
     70 ; T2: orreq r2, r2, #1
     71   %tmp1 = icmp eq i32 %a, %b
     72   %tmp2 = zext i1 %tmp1 to i32
     73   %tmp3 = or i32 %tmp2, %c
     74   ret i32 %tmp3
     75 }
     76 
     77 define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
     78 ; ARM: t6:
     79 ; ARM-NOT: movge
     80 ; ARM: eorlt r3, r3, r2
     81 
     82 ; T2: t6:
     83 ; T2-NOT: movge
     84 ; T2: eorlt.w r3, r3, r2
     85   %cond = icmp slt i32 %a, %b
     86   %tmp1 = select i1 %cond, i32 %c, i32 0
     87   %tmp2 = xor i32 %tmp1, %d
     88   ret i32 %tmp2
     89 }
     90 
     91 define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
     92 entry:
     93 ; ARM: t7:
     94 ; ARM-NOT: lsleq
     95 ; ARM: andeq r2, r2, r2, lsl #1
     96 
     97 ; T2: t7:
     98 ; T2-NOT: lsleq.w
     99 ; T2: andeq.w r2, r2, r2, lsl #1
    100   %tmp1 = shl i32 %c, 1
    101   %cond = icmp eq i32 %a, %b
    102   %tmp2 = select i1 %cond, i32 %tmp1, i32 -1
    103   %tmp3 = and i32 %c, %tmp2
    104   ret i32 %tmp3
    105 }
    106 
    107