1 ; RUN: opt -S -instcombine < %s | FileCheck %s 2 ; <rdar://problem/8558713> 3 4 declare void @throwAnExceptionOrWhatever() 5 6 ; CHECK: @test1 7 define i32 @test1(i32 %a, i32 %b) nounwind ssp { 8 entry: 9 ; CHECK-NOT: sext 10 %conv = sext i32 %a to i64 11 %conv2 = sext i32 %b to i64 12 %add = add nsw i64 %conv2, %conv 13 %add.off = add i64 %add, 2147483648 14 ; CHECK: llvm.sadd.with.overflow.i32 15 %0 = icmp ugt i64 %add.off, 4294967295 16 br i1 %0, label %if.then, label %if.end 17 18 if.then: 19 tail call void @throwAnExceptionOrWhatever() nounwind 20 br label %if.end 21 22 if.end: 23 ; CHECK-NOT: trunc 24 %conv9 = trunc i64 %add to i32 25 ; CHECK: ret i32 26 ret i32 %conv9 27 } 28 29 ; CHECK: @test2 30 ; This form should not be promoted for two reasons: 1) it is unprofitable to 31 ; promote it since the add.off instruction has another use, and 2) it is unsafe 32 ; because the add-with-off makes the high bits of the original add live. 33 define i32 @test2(i32 %a, i32 %b, i64* %P) nounwind ssp { 34 entry: 35 %conv = sext i32 %a to i64 36 %conv2 = sext i32 %b to i64 37 %add = add nsw i64 %conv2, %conv 38 %add.off = add i64 %add, 2147483648 39 40 store i64 %add.off, i64* %P 41 42 ; CHECK-NOT: llvm.sadd.with.overflow 43 %0 = icmp ugt i64 %add.off, 4294967295 44 br i1 %0, label %if.then, label %if.end 45 46 if.then: 47 tail call void @throwAnExceptionOrWhatever() nounwind 48 br label %if.end 49 50 if.end: 51 %conv9 = trunc i64 %add to i32 52 ; CHECK: ret i32 53 ret i32 %conv9 54 } 55 56 ; CHECK: test3 57 ; PR8816 58 ; This is illegal to transform because the high bits of the original add are 59 ; live out. 60 define i64 @test3(i32 %a, i32 %b) nounwind ssp { 61 entry: 62 %conv = sext i32 %a to i64 63 %conv2 = sext i32 %b to i64 64 %add = add nsw i64 %conv2, %conv 65 %add.off = add i64 %add, 2147483648 66 ; CHECK-NOT: llvm.sadd.with.overflow 67 %0 = icmp ugt i64 %add.off, 4294967295 68 br i1 %0, label %if.then, label %if.end 69 70 if.then: 71 tail call void @throwAnExceptionOrWhatever() nounwind 72 br label %if.end 73 74 if.end: 75 ret i64 %add 76 ; CHECK: ret i64 77 } 78 79 ; CHECK: @test4 80 ; Should be able to form an i8 sadd computed in an i32. 81 define zeroext i8 @test4(i8 signext %a, i8 signext %b) nounwind ssp { 82 entry: 83 %conv = sext i8 %a to i32 84 %conv2 = sext i8 %b to i32 85 %add = add nsw i32 %conv2, %conv 86 %add4 = add nsw i32 %add, 128 87 %cmp = icmp ugt i32 %add4, 255 88 br i1 %cmp, label %if.then, label %if.end 89 ; CHECK: llvm.sadd.with.overflow.i8 90 if.then: ; preds = %entry 91 tail call void @throwAnExceptionOrWhatever() nounwind 92 unreachable 93 94 if.end: ; preds = %entry 95 %conv7 = trunc i32 %add to i8 96 ret i8 %conv7 97 ; CHECK: ret i8 98 } 99 100 ; CHECK: @test5 101 ; CHECK: llvm.uadd.with.overflow 102 ; CHECK: ret i64 103 define i64 @test5(i64 %a, i64 %b) nounwind ssp { 104 entry: 105 %add = add i64 %b, %a 106 %cmp = icmp ult i64 %add, %a 107 %Q = select i1 %cmp, i64 %b, i64 42 108 ret i64 %Q 109 } 110 111 ; CHECK: @test6 112 ; CHECK: llvm.uadd.with.overflow 113 ; CHECK: ret i64 114 define i64 @test6(i64 %a, i64 %b) nounwind ssp { 115 entry: 116 %add = add i64 %b, %a 117 %cmp = icmp ult i64 %add, %b 118 %Q = select i1 %cmp, i64 %b, i64 42 119 ret i64 %Q 120 } 121 122 ; CHECK: @test7 123 ; CHECK: llvm.uadd.with.overflow 124 ; CHECK: ret i64 125 define i64 @test7(i64 %a, i64 %b) nounwind ssp { 126 entry: 127 %add = add i64 %b, %a 128 %cmp = icmp ugt i64 %b, %add 129 %Q = select i1 %cmp, i64 %b, i64 42 130 ret i64 %Q 131 } 132 133 ; CHECK: @test8 134 ; PR11438 135 ; This is @test1, but the operands are not sign-extended. Make sure 136 ; we don't transform this case. 137 define i32 @test8(i64 %a, i64 %b) nounwind ssp { 138 entry: 139 ; CHECK-NOT: llvm.sadd 140 ; CHECK: add i64 %a, %b 141 ; CHECK-NOT: llvm.sadd 142 ; CHECK: ret 143 %add = add i64 %a, %b 144 %add.off = add i64 %add, 2147483648 145 %0 = icmp ugt i64 %add.off, 4294967295 146 br i1 %0, label %if.then, label %if.end 147 148 if.then: 149 tail call void @throwAnExceptionOrWhatever() nounwind 150 br label %if.end 151 152 if.end: 153 %conv9 = trunc i64 %add to i32 154 ret i32 %conv9 155 } 156
