1 //===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "DisassemblerEmitter.h" 11 #include "CodeGenTarget.h" 12 #include "X86DisassemblerTables.h" 13 #include "X86RecognizableInstr.h" 14 #include "FixedLenDecoderEmitter.h" 15 #include "llvm/TableGen/Error.h" 16 #include "llvm/TableGen/Record.h" 17 18 using namespace llvm; 19 using namespace llvm::X86Disassembler; 20 21 /// DisassemblerEmitter - Contains disassembler table emitters for various 22 /// architectures. 23 24 /// X86 Disassembler Emitter 25 /// 26 /// *** IF YOU'RE HERE TO RESOLVE A "Primary decode conflict", LOOK DOWN NEAR 27 /// THE END OF THIS COMMENT! 28 /// 29 /// The X86 disassembler emitter is part of the X86 Disassembler, which is 30 /// documented in lib/Target/X86/X86Disassembler.h. 31 /// 32 /// The emitter produces the tables that the disassembler uses to translate 33 /// instructions. The emitter generates the following tables: 34 /// 35 /// - One table (CONTEXTS_SYM) that contains a mapping of attribute masks to 36 /// instruction contexts. Although for each attribute there are cases where 37 /// that attribute determines decoding, in the majority of cases decoding is 38 /// the same whether or not an attribute is present. For example, a 64-bit 39 /// instruction with an OPSIZE prefix and an XS prefix decodes the same way in 40 /// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix 41 /// may have effects on its execution, but does not change the instruction 42 /// returned.) This allows considerable space savings in other tables. 43 /// - Six tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM, 44 /// THREEBYTEA6_SYM, and THREEBYTEA7_SYM contain the hierarchy that the 45 /// decoder traverses while decoding an instruction. At the lowest level of 46 /// this hierarchy are instruction UIDs, 16-bit integers that can be used to 47 /// uniquely identify the instruction and correspond exactly to its position 48 /// in the list of CodeGenInstructions for the target. 49 /// - One table (INSTRUCTIONS_SYM) contains information about the operands of 50 /// each instruction and how to decode them. 51 /// 52 /// During table generation, there may be conflicts between instructions that 53 /// occupy the same space in the decode tables. These conflicts are resolved as 54 /// follows in setTableFields() (X86DisassemblerTables.cpp) 55 /// 56 /// - If the current context is the native context for one of the instructions 57 /// (that is, the attributes specified for it in the LLVM tables specify 58 /// precisely the current context), then it has priority. 59 /// - If the current context isn't native for either of the instructions, then 60 /// the higher-priority context wins (that is, the one that is more specific). 61 /// That hierarchy is determined by outranks() (X86DisassemblerTables.cpp) 62 /// - If the current context is native for both instructions, then the table 63 /// emitter reports a conflict and dies. 64 /// 65 /// *** RESOLUTION FOR "Primary decode conflict"S 66 /// 67 /// If two instructions collide, typically the solution is (in order of 68 /// likelihood): 69 /// 70 /// (1) to filter out one of the instructions by editing filter() 71 /// (X86RecognizableInstr.cpp). This is the most common resolution, but 72 /// check the Intel manuals first to make sure that (2) and (3) are not the 73 /// problem. 74 /// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are 75 /// accurate. Sometimes they are not. 76 /// (3) to fix the tables to reflect the actual context (for example, required 77 /// prefixes), and possibly to add a new context by editing 78 /// lib/Target/X86/X86DisassemblerDecoderCommon.h. This is unlikely to be 79 /// the cause. 80 /// 81 /// DisassemblerEmitter.cpp contains the implementation for the emitter, 82 /// which simply pulls out instructions from the CodeGenTarget and pushes them 83 /// into X86DisassemblerTables. 84 /// X86DisassemblerTables.h contains the interface for the instruction tables, 85 /// which manage and emit the structures discussed above. 86 /// X86DisassemblerTables.cpp contains the implementation for the instruction 87 /// tables. 88 /// X86ModRMFilters.h contains filters that can be used to determine which 89 /// ModR/M values are valid for a particular instruction. These are used to 90 /// populate ModRMDecisions. 91 /// X86RecognizableInstr.h contains the interface for a single instruction, 92 /// which knows how to translate itself from a CodeGenInstruction and provide 93 /// the information necessary for integration into the tables. 94 /// X86RecognizableInstr.cpp contains the implementation for a single 95 /// instruction. 96 97 void DisassemblerEmitter::run(raw_ostream &OS) { 98 CodeGenTarget Target(Records); 99 100 OS << "/*===- TableGen'erated file " 101 << "---------------------------------------*- C -*-===*\n" 102 << " *\n" 103 << " * " << Target.getName() << " Disassembler\n" 104 << " *\n" 105 << " * Automatically generated file, do not edit!\n" 106 << " *\n" 107 << " *===---------------------------------------------------------------" 108 << "-------===*/\n"; 109 110 // X86 uses a custom disassembler. 111 if (Target.getName() == "X86") { 112 DisassemblerTables Tables; 113 114 const std::vector<const CodeGenInstruction*> &numberedInstructions = 115 Target.getInstructionsByEnumValue(); 116 117 for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i) 118 RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i); 119 120 // FIXME: As long as we are using exceptions, might as well drop this to the 121 // actual conflict site. 122 if (Tables.hasConflicts()) 123 throw TGError(Target.getTargetRecord()->getLoc(), 124 "Primary decode conflict"); 125 126 Tables.emit(OS); 127 return; 128 } 129 130 // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses. 131 if (Target.getName() == "ARM" || 132 Target.getName() == "Thumb") { 133 FixedLenDecoderEmitter(Records, 134 "ARM", 135 "if (!Check(S, ", ")) return MCDisassembler::Fail;", 136 "S", "MCDisassembler::Fail", 137 " MCDisassembler::DecodeStatus S = MCDisassembler::Success;\n(void)S;").run(OS); 138 return; 139 } 140 141 FixedLenDecoderEmitter(Records, Target.getName()).run(OS); 142 } 143
