1 //===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "pseudo-lowering" 11 #include "CodeGenInstruction.h" 12 #include "PseudoLoweringEmitter.h" 13 #include "llvm/TableGen/Error.h" 14 #include "llvm/TableGen/Record.h" 15 #include "llvm/ADT/IndexedMap.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/Support/ErrorHandling.h" 18 #include "llvm/Support/Debug.h" 19 #include <vector> 20 using namespace llvm; 21 22 // FIXME: This pass currently can only expand a pseudo to a single instruction. 23 // The pseudo expansion really should take a list of dags, not just 24 // a single dag, so we can do fancier things. 25 26 unsigned PseudoLoweringEmitter:: 27 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, 28 IndexedMap<OpData> &OperandMap, unsigned BaseIdx) { 29 unsigned OpsAdded = 0; 30 for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) { 31 if (DefInit *DI = dynamic_cast<DefInit*>(Dag->getArg(i))) { 32 // Physical register reference. Explicit check for the special case 33 // "zero_reg" definition. 34 if (DI->getDef()->isSubClassOf("Register") || 35 DI->getDef()->getName() == "zero_reg") { 36 OperandMap[BaseIdx + i].Kind = OpData::Reg; 37 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); 38 ++OpsAdded; 39 continue; 40 } 41 42 // Normal operands should always have the same type, or we have a 43 // problem. 44 // FIXME: We probably shouldn't ever get a non-zero BaseIdx here. 45 assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!"); 46 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) 47 throw TGError(Rec->getLoc(), 48 "Pseudo operand type '" + DI->getDef()->getName() + 49 "' does not match expansion operand type '" + 50 Insn.Operands[BaseIdx + i].Rec->getName() + "'"); 51 // Source operand maps to destination operand. The Data element 52 // will be filled in later, just set the Kind for now. Do it 53 // for each corresponding MachineInstr operand, not just the first. 54 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 55 OperandMap[BaseIdx + i + I].Kind = OpData::Operand; 56 OpsAdded += Insn.Operands[i].MINumOperands; 57 } else if (IntInit *II = dynamic_cast<IntInit*>(Dag->getArg(i))) { 58 OperandMap[BaseIdx + i].Kind = OpData::Imm; 59 OperandMap[BaseIdx + i].Data.Imm = II->getValue(); 60 ++OpsAdded; 61 } else if (DagInit *SubDag = dynamic_cast<DagInit*>(Dag->getArg(i))) { 62 // Just add the operands recursively. This is almost certainly 63 // a constant value for a complex operand (> 1 MI operand). 64 unsigned NewOps = 65 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); 66 OpsAdded += NewOps; 67 // Since we added more than one, we also need to adjust the base. 68 BaseIdx += NewOps - 1; 69 } else 70 llvm_unreachable("Unhandled pseudo-expansion argument type!"); 71 } 72 return OpsAdded; 73 } 74 75 void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) { 76 DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n"); 77 78 // Validate that the result pattern has the corrent number and types 79 // of arguments for the instruction it references. 80 DagInit *Dag = Rec->getValueAsDag("ResultInst"); 81 assert(Dag && "Missing result instruction in pseudo expansion!"); 82 DEBUG(dbgs() << " Result: " << *Dag << "\n"); 83 84 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator()); 85 if (!OpDef) 86 throw TGError(Rec->getLoc(), Rec->getName() + 87 " has unexpected operator type!"); 88 Record *Operator = OpDef->getDef(); 89 if (!Operator->isSubClassOf("Instruction")) 90 throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 91 "' is not an instruction!"); 92 93 CodeGenInstruction Insn(Operator); 94 95 if (Insn.isCodeGenOnly || Insn.isPseudo) 96 throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 97 "' cannot be another pseudo instruction!"); 98 99 if (Insn.Operands.size() != Dag->getNumArgs()) 100 throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 101 "' operand count mismatch"); 102 103 unsigned NumMIOperands = 0; 104 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) 105 NumMIOperands += Insn.Operands[i].MINumOperands; 106 IndexedMap<OpData> OperandMap; 107 OperandMap.grow(NumMIOperands); 108 109 addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0); 110 111 // If there are more operands that weren't in the DAG, they have to 112 // be operands that have default values, or we have an error. Currently, 113 // PredicateOperand and OptionalDefOperand both have default values. 114 115 116 // Validate that each result pattern argument has a matching (by name) 117 // argument in the source instruction, in either the (outs) or (ins) list. 118 // Also check that the type of the arguments match. 119 // 120 // Record the mapping of the source to result arguments for use by 121 // the lowering emitter. 122 CodeGenInstruction SourceInsn(Rec); 123 StringMap<unsigned> SourceOperands; 124 for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i) 125 SourceOperands[SourceInsn.Operands[i].Name] = i; 126 127 DEBUG(dbgs() << " Operand mapping:\n"); 128 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) { 129 // We've already handled constant values. Just map instruction operands 130 // here. 131 if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand) 132 continue; 133 StringMap<unsigned>::iterator SourceOp = 134 SourceOperands.find(Dag->getArgName(i)); 135 if (SourceOp == SourceOperands.end()) 136 throw TGError(Rec->getLoc(), 137 "Pseudo output operand '" + Dag->getArgName(i) + 138 "' has no matching source operand."); 139 // Map the source operand to the destination operand index for each 140 // MachineInstr operand. 141 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 142 OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand = 143 SourceOp->getValue(); 144 145 DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << i << "\n"); 146 } 147 148 Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap)); 149 } 150 151 void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) { 152 // Emit file header. 153 EmitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o); 154 155 o << "bool " << Target.getName() + "AsmPrinter" << "::\n" 156 << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n" 157 << " const MachineInstr *MI) {\n" 158 << " switch (MI->getOpcode()) {\n" 159 << " default: return false;\n"; 160 for (unsigned i = 0, e = Expansions.size(); i != e; ++i) { 161 PseudoExpansion &Expansion = Expansions[i]; 162 CodeGenInstruction &Source = Expansion.Source; 163 CodeGenInstruction &Dest = Expansion.Dest; 164 o << " case " << Source.Namespace << "::" 165 << Source.TheDef->getName() << ": {\n" 166 << " MCInst TmpInst;\n" 167 << " MCOperand MCOp;\n" 168 << " TmpInst.setOpcode(" << Dest.Namespace << "::" 169 << Dest.TheDef->getName() << ");\n"; 170 171 // Copy the operands from the source instruction. 172 // FIXME: Instruction operands with defaults values (predicates and cc_out 173 // in ARM, for example shouldn't need explicit values in the 174 // expansion DAG. 175 unsigned MIOpNo = 0; 176 for (unsigned OpNo = 0, E = Dest.Operands.size(); OpNo != E; 177 ++OpNo) { 178 o << " // Operand: " << Dest.Operands[OpNo].Name << "\n"; 179 for (unsigned i = 0, e = Dest.Operands[OpNo].MINumOperands; 180 i != e; ++i) { 181 switch (Expansion.OperandMap[MIOpNo + i].Kind) { 182 case OpData::Operand: 183 o << " lowerOperand(MI->getOperand(" 184 << Source.Operands[Expansion.OperandMap[MIOpNo].Data 185 .Operand].MIOperandNo + i 186 << "), MCOp);\n" 187 << " TmpInst.addOperand(MCOp);\n"; 188 break; 189 case OpData::Imm: 190 o << " TmpInst.addOperand(MCOperand::CreateImm(" 191 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n"; 192 break; 193 case OpData::Reg: { 194 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg; 195 o << " TmpInst.addOperand(MCOperand::CreateReg("; 196 // "zero_reg" is special. 197 if (Reg->getName() == "zero_reg") 198 o << "0"; 199 else 200 o << Reg->getValueAsString("Namespace") << "::" << Reg->getName(); 201 o << "));\n"; 202 break; 203 } 204 } 205 } 206 MIOpNo += Dest.Operands[OpNo].MINumOperands; 207 } 208 if (Dest.Operands.isVariadic) { 209 o << " // variable_ops\n"; 210 o << " for (unsigned i = " << MIOpNo 211 << ", e = MI->getNumOperands(); i != e; ++i)\n" 212 << " if (lowerOperand(MI->getOperand(i), MCOp))\n" 213 << " TmpInst.addOperand(MCOp);\n"; 214 } 215 o << " OutStreamer.EmitInstruction(TmpInst);\n" 216 << " break;\n" 217 << " }\n"; 218 } 219 o << " }\n return true;\n}\n\n"; 220 } 221 222 void PseudoLoweringEmitter::run(raw_ostream &o) { 223 Record *ExpansionClass = Records.getClass("PseudoInstExpansion"); 224 Record *InstructionClass = Records.getClass("PseudoInstExpansion"); 225 assert(ExpansionClass && "PseudoInstExpansion class definition missing!"); 226 assert(InstructionClass && "Instruction class definition missing!"); 227 228 std::vector<Record*> Insts; 229 for (std::map<std::string, Record*>::const_iterator I = 230 Records.getDefs().begin(), E = Records.getDefs().end(); I != E; ++I) { 231 if (I->second->isSubClassOf(ExpansionClass) && 232 I->second->isSubClassOf(InstructionClass)) 233 Insts.push_back(I->second); 234 } 235 236 // Process the pseudo expansion definitions, validating them as we do so. 237 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 238 evaluateExpansion(Insts[i]); 239 240 // Generate expansion code to lower the pseudo to an MCInst of the real 241 // instruction. 242 emitLoweringEmitter(o); 243 } 244 245
