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      1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
      2 target triple = "armv7-none-linux-gnueabi"
      3 
      4 define <2 x float> @_Z14convert_float2Dv2_h(<2 x i8> %in) nounwind readnone alwaysinline {
      5   %1 = uitofp <2 x i8> %in to <2 x float>
      6   ret <2 x float> %1
      7 }
      8 
      9 define <3 x float> @_Z14convert_float3Dv3_h(<3 x i8> %in) nounwind readnone alwaysinline {
     10   %1 = uitofp <3 x i8> %in to <3 x float>
     11   ret <3 x float> %1
     12 }
     13 
     14 define <4 x float> @_Z14convert_float4Dv4_h(<4 x i8> %in) nounwind readnone alwaysinline {
     15   %1 = uitofp <4 x i8> %in to <4 x float>
     16   ret <4 x float> %1
     17 }
     18 
     19 define <2 x float> @_Z14convert_float2Dv2_c(<2 x i8> %in) nounwind readnone alwaysinline {
     20   %1 = sitofp <2 x i8> %in to <2 x float>
     21   ret <2 x float> %1
     22 }
     23 
     24 define <3 x float> @_Z14convert_float3Dv3_c(<3 x i8> %in) nounwind readnone alwaysinline {
     25   %1 = sitofp <3 x i8> %in to <3 x float>
     26   ret <3 x float> %1
     27 }
     28 
     29 define <4 x float> @_Z14convert_float4Dv4_c(<4 x i8> %in) nounwind readnone alwaysinline {
     30   %1 = sitofp <4 x i8> %in to <4 x float>
     31   ret <4 x float> %1
     32 }
     33 
     34 define <2 x float> @_Z14convert_float2Dv2_t(<2 x i16> %in) nounwind readnone alwaysinline {
     35   %1 = uitofp <2 x i16> %in to <2 x float>
     36   ret <2 x float> %1
     37 }
     38 
     39 define <3 x float> @_Z14convert_float3Dv3_t(<3 x i16> %in) nounwind readnone alwaysinline {
     40   %1 = uitofp <3 x i16> %in to <3 x float>
     41   ret <3 x float> %1
     42 }
     43 
     44 define <4 x float> @_Z14convert_float4Dv4_t(<4 x i16> %in) nounwind readnone alwaysinline {
     45   %1 = uitofp <4 x i16> %in to <4 x float>
     46   ret <4 x float> %1
     47 }
     48 
     49 define <2 x float> @_Z14convert_float2Dv2_s(<2 x i16> %in) nounwind readnone alwaysinline {
     50   %1 = sitofp <2 x i16> %in to <2 x float>
     51   ret <2 x float> %1
     52 }
     53 
     54 define <3 x float> @_Z14convert_float3Dv3_s(<3 x i16> %in) nounwind readnone alwaysinline {
     55   %1 = sitofp <3 x i16> %in to <3 x float>
     56   ret <3 x float> %1
     57 }
     58 
     59 define <4 x float> @_Z14convert_float4Dv4_s(<4 x i16> %in) nounwind readnone alwaysinline {
     60   %1 = sitofp <4 x i16> %in to <4 x float>
     61   ret <4 x float> %1
     62 }
     63 
     64 define <2 x float> @_Z14convert_float2Dv2_j(<2 x i32> %in) nounwind readnone alwaysinline {
     65   %1 = uitofp <2 x i32> %in to <2 x float>
     66   ret <2 x float> %1
     67 }
     68 
     69 define <3 x float> @_Z14convert_float3Dv3_j(<3 x i32> %in) nounwind readnone alwaysinline {
     70   %1 = uitofp <3 x i32> %in to <3 x float>
     71   ret <3 x float> %1
     72 }
     73 
     74 define <4 x float> @_Z14convert_float4Dv4_j(<4 x i32> %in) nounwind readnone alwaysinline {
     75   %1 = uitofp <4 x i32> %in to <4 x float>
     76   ret <4 x float> %1
     77 }
     78 
     79 define <2 x float> @_Z14convert_float2Dv2_i(<2 x i32> %in) nounwind readnone alwaysinline {
     80   %1 = sitofp <2 x i32> %in to <2 x float>
     81   ret <2 x float> %1
     82 }
     83 
     84 define <3 x float> @_Z14convert_float3Dv3_i(<3 x i32> %in) nounwind readnone alwaysinline {
     85   %1 = sitofp <3 x i32> %in to <3 x float>
     86   ret <3 x float> %1
     87 }
     88 
     89 define <4 x float> @_Z14convert_float4Dv4_i(<4 x i32> %in) nounwind readnone alwaysinline {
     90   %1 = sitofp <4 x i32> %in to <4 x float>
     91   ret <4 x float> %1
     92 }
     93 
     94 define <2 x float> @_Z14convert_float2Dv2_f(<2 x float> %in) nounwind readnone alwaysinline {
     95   ret <2 x float> %in
     96 }
     97 
     98 define <3 x float> @_Z14convert_float3Dv3_f(<3 x float> %in) nounwind readnone alwaysinline {
     99   ret <3 x float> %in
    100 }
    101 
    102 define <4 x float> @_Z14convert_float4Dv4_f(<4 x float> %in) nounwind readnone alwaysinline {
    103   ret <4 x float> %in
    104 }
    105 
    106 ;---
    107 
    108 define <4 x i8> @_Z14convert_uchar4Dv4_f(<4 x float> %in) nounwind readnone alwaysinline {
    109   %1 = fptoui <4 x float> %in to <4 x i32>
    110   %2 = trunc <4 x i32> %1 to <4 x i16>
    111   %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    112   %4 = trunc <8 x i16> %3 to <8 x i8>
    113   %5 = shufflevector <8 x i8> %4, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    114   ret <4 x i8> %5
    115 }
    116 
    117 define <3 x i8> @_Z14convert_uchar3Dv3_f(<3 x float> %in) nounwind readnone alwaysinline {
    118   %in2 = shufflevector <3 x float> %in, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    119   %1 = fptoui <4 x float> %in2 to <4 x i32>
    120   %2 = trunc <4 x i32> %1 to <4 x i16>
    121   %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    122   %4 = trunc <8 x i16> %3 to <8 x i8>
    123   %5 = shufflevector <8 x i8> %4, <8 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
    124   ret <3 x i8> %5
    125 }
    126 
    127 define <2 x i8> @_Z14convert_uchar2Dv2_f(<2 x float> %in) nounwind readnone alwaysinline {
    128   %in2 = shufflevector <2 x float> %in, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    129   %1 = fptoui <4 x float> %in2 to <4 x i32>
    130   %2 = trunc <4 x i32> %1 to <4 x i16>
    131   %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    132   %4 = trunc <8 x i16> %3 to <8 x i8>
    133   %5 = shufflevector <8 x i8> %4, <8 x i8> undef, <2 x i32> <i32 0, i32 1>
    134   ret <2 x i8> %5
    135 }
    136 
    137 define <4 x i8> @_Z14convert_uchar4Dv4_h(<4 x i8> %in) nounwind readnone alwaysinline {
    138   ret <4 x i8> %in
    139 }
    140 
    141 define <3 x i8> @_Z14convert_uchar3Dv3_h(<3 x i8> %in) nounwind readnone alwaysinline {
    142   ret <3 x i8> %in
    143 }
    144 
    145 define <2 x i8> @_Z14convert_uchar2Dv2_h(<2 x i8> %in) nounwind readnone alwaysinline {
    146   ret <2 x i8> %in
    147 }
    148 
    149 define <4 x i8> @_Z14convert_uchar4Dv4_c(<4 x i8> %in) nounwind readnone alwaysinline {
    150   ret <4 x i8> %in
    151 }
    152 
    153 define <3 x i8> @_Z14convert_uchar3Dv3_c(<3 x i8> %in) nounwind readnone alwaysinline {
    154   ret <3 x i8> %in
    155 }
    156 
    157 define <2 x i8> @_Z14convert_uchar2Dv2_c(<2 x i8> %in) nounwind readnone alwaysinline {
    158   ret <2 x i8> %in
    159 }
    160 
    161 
    162 define <4 x i8> @_Z14convert_uchar4Dv4_t(<4 x i16> %in) nounwind readnone alwaysinline {
    163   %1 = shufflevector <4 x i16> %in, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    164   %2 = trunc <8 x i16> %1 to <8 x i8>
    165   %3 = shufflevector <8 x i8> %2, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    166   ret <4 x i8> %3
    167 }
    168 
    169 define <3 x i8> @_Z14convert_uchar3Dv3_t(<3 x i16> %in) nounwind readnone alwaysinline {
    170   %1 = shufflevector <3 x i16> %in, <3 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 5, i32 5>
    171   %2 = trunc <8 x i16> %1 to <8 x i8>
    172   %3 = shufflevector <8 x i8> %2, <8 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
    173   ret <3 x i8> %3
    174 }
    175 
    176 define <2 x i8> @_Z14convert_uchar2Dv2_t(<2 x i16> %in) nounwind readnone alwaysinline {
    177   %1 = shufflevector <2 x i16> %in, <2 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
    178   %2 = trunc <8 x i16> %1 to <8 x i8>
    179   %3 = shufflevector <8 x i8> %2, <8 x i8> undef, <2 x i32> <i32 0, i32 1>
    180   ret <2 x i8> %3
    181 }
    182 
    183 define <4 x i8> @_Z14convert_uchar4Dv4_s(<4 x i16> %in) nounwind readnone alwaysinline {
    184   %1 = shufflevector <4 x i16> %in, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    185   %2 = trunc <8 x i16> %1 to <8 x i8>
    186   %3 = shufflevector <8 x i8> %2, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    187   ret <4 x i8> %3
    188 }
    189 
    190 define <3 x i8> @_Z14convert_uchar3Dv3_s(<3 x i16> %in) nounwind readnone alwaysinline {
    191   %1 = shufflevector <3 x i16> %in, <3 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 5, i32 5>
    192   %2 = trunc <8 x i16> %1 to <8 x i8>
    193   %3 = shufflevector <8 x i8> %2, <8 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
    194   ret <3 x i8> %3
    195 }
    196 
    197 define <2 x i8> @_Z14convert_uchar2Dv2_s(<2 x i16> %in) nounwind readnone alwaysinline {
    198   %1 = shufflevector <2 x i16> %in, <2 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
    199   %2 = trunc <8 x i16> %1 to <8 x i8>
    200   %3 = shufflevector <8 x i8> %2, <8 x i8> undef, <2 x i32> <i32 0, i32 1>
    201   ret <2 x i8> %3
    202 }
    203 
    204 
    205 define <4 x i8> @_Z14convert_uchar4Dv4_j(<4 x i32> %in) nounwind readnone alwaysinline {
    206   %1 = trunc <4 x i32> %in to <4 x i16>
    207   %2 = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    208   %3 = trunc <8 x i16> %2 to <8 x i8>
    209   %4 = shufflevector <8 x i8> %3, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    210   ret <4 x i8> %4
    211 }
    212 
    213 define <3 x i8> @_Z14convert_uchar3Dv3_j(<3 x i32> %in) nounwind readnone alwaysinline {
    214   %1 = shufflevector <3 x i32> %in, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    215   %2 = trunc <4 x i32> %1 to <4 x i16>
    216   %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    217   %4 = trunc <8 x i16> %3 to <8 x i8>
    218   %5 = shufflevector <8 x i8> %4, <8 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
    219   ret <3 x i8> %5
    220 }
    221 
    222 define <2 x i8> @_Z14convert_uchar2Dv2_j(<2 x i32> %in) nounwind readnone alwaysinline {
    223   %1 = shufflevector <2 x i32> %in, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    224   %2 = trunc <4 x i32> %1 to <4 x i16>
    225   %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    226   %4 = trunc <8 x i16> %3 to <8 x i8>
    227   %5 = shufflevector <8 x i8> %4, <8 x i8> undef, <2 x i32> <i32 0, i32 1>
    228   ret <2 x i8> %5
    229 }
    230 
    231 define <4 x i8> @_Z14convert_uchar4Dv4_i(<4 x i32> %in) nounwind readnone alwaysinline {
    232   %1 = trunc <4 x i32> %in to <4 x i16>
    233   %2 = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    234   %3 = trunc <8 x i16> %2 to <8 x i8>
    235   %4 = shufflevector <8 x i8> %3, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    236   ret <4 x i8> %4
    237 }
    238 
    239 define <3 x i8> @_Z14convert_uchar3Dv3_i(<3 x i32> %in) nounwind readnone alwaysinline {
    240   %1 = shufflevector <3 x i32> %in, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    241   %2 = trunc <4 x i32> %1 to <4 x i16>
    242   %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    243   %4 = trunc <8 x i16> %3 to <8 x i8>
    244   %5 = shufflevector <8 x i8> %4, <8 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
    245   ret <3 x i8> %5
    246 }
    247 
    248 define <2 x i8> @_Z14convert_uchar2Dv2_i(<2 x i32> %in) nounwind readnone alwaysinline {
    249   %1 = shufflevector <2 x i32> %in, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    250   %2 = trunc <4 x i32> %1 to <4 x i16>
    251   %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    252   %4 = trunc <8 x i16> %3 to <8 x i8>
    253   %5 = shufflevector <8 x i8> %4, <8 x i8> undef, <2 x i32> <i32 0, i32 1>
    254   ret <2 x i8> %5
    255 }
    256 
    257