1 /* 2 * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards 3 * Copyright (c) by Jaroslav Kysela <perex (at) perex.cz> 4 * 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 * 21 * NOTE: comments are copy/paste from cwcemb80.lst 22 * provided by Tom Woller at Cirrus (my only 23 * documentation about the SP OS running inside 24 * the DSP) 25 */ 26 27 #ifndef __CS46XX_DSP_SCB_TYPES_H__ 28 #define __CS46XX_DSP_SCB_TYPES_H__ 29 30 #include <asm/byteorder.h> 31 32 #ifndef ___DSP_DUAL_16BIT_ALLOC 33 #if defined(__LITTLE_ENDIAN) 34 #define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 a; u16 b; 35 #elif defined(__BIG_ENDIAN) 36 #define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 b; u16 a; 37 #else 38 #error Not __LITTLE_ENDIAN and not __BIG_ENDIAN, then what ??? 39 #endif 40 #endif 41 42 /* This structs are used internally by the SP */ 43 44 struct dsp_basic_dma_req { 45 /* DMA Requestor Word 0 (DCW) fields: 46 47 31 [30-28]27 [26:24] 23 22 21 20 [19:18] [17:16] 15 14 13 12 11 10 9 8 7 6 [5:0] 48 _______________________________________________________________________________________ 49 |S| SBT |D| DBT |wb|wb| | | LS | SS |Opt|Do|SSG|DSG| | | | | | | Dword | 50 |H|_____ |H|_________|S_|D |__|__|______|_______|___|ne|__ |__ |__|__|_|_|_|_|_Count -1| 51 */ 52 u32 dcw; /* DMA Control Word */ 53 u32 dmw; /* DMA Mode Word */ 54 u32 saw; /* Source Address Word */ 55 u32 daw; /* Destination Address Word */ 56 }; 57 58 struct dsp_scatter_gather_ext { 59 u32 npaw; /* Next-Page Address Word */ 60 61 /* DMA Requestor Word 5 (NPCW) fields: 62 63 31-30 29 28 [27:16] [15:12] [11:3] [2:0] 64 _________________________________________________________________________________________ 65 |SV |LE|SE| Sample-end byte offset | | Page-map entry offset for next | | 66 |page|__|__| ___________________________|_________|__page, if !sample-end___________|____| 67 */ 68 u32 npcw; /* Next-Page Control Word */ 69 u32 lbaw; /* Loop-Begin Address Word */ 70 u32 nplbaw; /* Next-Page after Loop-Begin Address Word */ 71 u32 sgaw; /* Scatter/Gather Address Word */ 72 }; 73 74 struct dsp_volume_control { 75 ___DSP_DUAL_16BIT_ALLOC( 76 rightTarg, /* Target volume for left & right channels */ 77 leftTarg 78 ) 79 ___DSP_DUAL_16BIT_ALLOC( 80 rightVol, /* Current left & right channel volumes */ 81 leftVol 82 ) 83 }; 84 85 /* Generic stream control block (SCB) structure definition */ 86 struct dsp_generic_scb { 87 /* For streaming I/O, the DSP should never alter any words in the DMA 88 requestor or the scatter/gather extension. Only ad hoc DMA request 89 streams are free to alter the requestor (currently only occur in the 90 DOS-based MIDI controller and in debugger-inserted code). 91 92 If an SCB does not have any associated DMA requestor, these 9 ints 93 may be freed for use by other tasks, but the pointer to the SCB must 94 still be such that the insOrd:nextSCB appear at offset 9 from the 95 SCB pointer. 96 97 Basic (non scatter/gather) DMA requestor (4 ints) 98 */ 99 100 /* Initialized by the host, only modified by DMA 101 R/O for the DSP task */ 102 struct dsp_basic_dma_req basic_req; /* Optional */ 103 104 /* Scatter/gather DMA requestor extension (5 ints) 105 Initialized by the host, only modified by DMA 106 DSP task never needs to even read these. 107 */ 108 struct dsp_scatter_gather_ext sg_ext; /* Optional */ 109 110 /* Sublist pointer & next stream control block (SCB) link. 111 Initialized & modified by the host R/O for the DSP task 112 */ 113 ___DSP_DUAL_16BIT_ALLOC( 114 next_scb, /* REQUIRED */ 115 sub_list_ptr /* REQUIRED */ 116 ) 117 118 /* Pointer to this tasks parameter block & stream function pointer 119 Initialized by the host R/O for the DSP task */ 120 ___DSP_DUAL_16BIT_ALLOC( 121 entry_point, /* REQUIRED */ 122 this_spb /* REQUIRED */ 123 ) 124 125 /* rsConfig register for stream buffer (rsDMA reg. 126 is loaded from basicReq.daw for incoming streams, or 127 basicReq.saw, for outgoing streams) 128 129 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0] 130 ______________________________________________________________________________ 131 |DMA |D|maxDMAsize| streamNum|dir|p| | | | | | |ds |shr 1|rev Cy | mod | 132 |prio |_|__________|__________|___|_|__|__|__|__|_|_|___|_____|_______|_______| 133 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0] 134 135 136 Initialized by the host R/O for the DSP task 137 */ 138 u32 strm_rs_config; /* REQUIRED */ 139 // 140 /* On mixer input streams: indicates mixer input stream configuration 141 On Tees, this is copied from the stream being snooped 142 143 Stream sample pointer & MAC-unit mode for this stream 144 145 Initialized by the host Updated by the DSP task 146 */ 147 u32 strm_buf_ptr; /* REQUIRED */ 148 149 /* On mixer input streams: points to next mixer input and is updated by the 150 mixer subroutine in the "parent" DSP task 151 (least-significant 16 bits are preserved, unused) 152 153 On Tees, the pointer is copied from the stream being snooped on 154 initialization, and, subsequently, it is copied into the 155 stream being snooped. 156 157 On wavetable/3D voices: the strmBufPtr will use all 32 bits to allow for 158 fractional phase accumulation 159 160 Fractional increment per output sample in the input sample buffer 161 162 (Not used on mixer input streams & redefined on Tees) 163 On wavetable/3D voices: this 32-bit word specifies the integer.fractional 164 increment per output sample. 165 */ 166 u32 strmPhiIncr; 167 168 169 /* Standard stereo volume control 170 Initialized by the host (host updates target volumes) 171 172 Current volumes update by the DSP task 173 On mixer input streams: required & updated by the mixer subroutine in the 174 "parent" DSP task 175 176 On Tees, both current & target volumes are copied up on initialization, 177 and, subsequently, the target volume is copied up while the current 178 volume is copied down. 179 180 These two 32-bit words are redefined for wavetable & 3-D voices. 181 */ 182 struct dsp_volume_control vol_ctrl_t; /* Optional */ 183 }; 184 185 186 struct dsp_spos_control_block { 187 /* WARNING: Certain items in this structure are modified by the host 188 Any dword that can be modified by the host, must not be 189 modified by the SP as the host can only do atomic dword 190 writes, and to do otherwise, even a read modify write, 191 may lead to corrupted data on the SP. 192 193 This rule does not apply to one off boot time initialisation prior to starting the SP 194 */ 195 196 197 ___DSP_DUAL_16BIT_ALLOC( 198 /* First element on the Hyper forground task tree */ 199 hfg_tree_root_ptr, /* HOST */ 200 /* First 3 dwords are written by the host and read-only on the DSP */ 201 hfg_stack_base /* HOST */ 202 ) 203 204 ___DSP_DUAL_16BIT_ALLOC( 205 /* Point to this data structure to enable easy access */ 206 spos_cb_ptr, /* SP */ 207 prev_task_tree_ptr /* SP && HOST */ 208 ) 209 210 ___DSP_DUAL_16BIT_ALLOC( 211 /* Currently Unused */ 212 xxinterval_timer_period, 213 /* Enable extension of SPOS data structure */ 214 HFGSPB_ptr 215 ) 216 217 218 ___DSP_DUAL_16BIT_ALLOC( 219 xxnum_HFG_ticks_thisInterval, 220 /* Modified by the DSP */ 221 xxnum_tntervals 222 ) 223 224 225 /* Set by DSP upon encountering a trap (breakpoint) or a spurious 226 interrupt. The host must clear this dword after reading it 227 upon receiving spInt1. */ 228 ___DSP_DUAL_16BIT_ALLOC( 229 spurious_int_flag, /* (Host & SP) Nature of the spurious interrupt */ 230 trap_flag /* (Host & SP) Nature of detected Trap */ 231 ) 232 233 ___DSP_DUAL_16BIT_ALLOC( 234 unused2, 235 invalid_IP_flag /* (Host & SP ) Indicate detection of invalid instruction pointer */ 236 ) 237 238 ___DSP_DUAL_16BIT_ALLOC( 239 /* pointer to forground task tree header for use in next task search */ 240 fg_task_tree_hdr_ptr, /* HOST */ 241 /* Data structure for controlling synchronous link update */ 242 hfg_sync_update_ptr /* HOST */ 243 ) 244 245 ___DSP_DUAL_16BIT_ALLOC( 246 begin_foreground_FCNT, /* SP */ 247 /* Place holder for holding sleep timing */ 248 last_FCNT_before_sleep /* SP */ 249 ) 250 251 ___DSP_DUAL_16BIT_ALLOC( 252 unused7, /* SP */ 253 next_task_treePtr /* SP */ 254 ) 255 256 u32 unused5; 257 258 ___DSP_DUAL_16BIT_ALLOC( 259 active_flags, /* SP */ 260 /* State flags, used to assist control of execution of Hyper Forground */ 261 HFG_flags /* SP */ 262 ) 263 264 ___DSP_DUAL_16BIT_ALLOC( 265 unused9, 266 unused8 267 ) 268 269 /* Space for saving enough context so that we can set up enough 270 to save some more context. 271 */ 272 u32 rFE_save_for_invalid_IP; 273 u32 r32_save_for_spurious_int; 274 u32 r32_save_for_trap; 275 u32 r32_save_for_HFG; 276 }; 277 278 /* SPB for MIX_TO_OSTREAM algorithm family */ 279 struct dsp_mix2_ostream_spb 280 { 281 /* 16b.16b integer.frac approximation to the 282 number of 3 sample triplets to output each 283 frame. (approximation must be floor, to 284 insure that the fractional error is always 285 positive) 286 */ 287 u32 outTripletsPerFrame; 288 289 /* 16b.16b integer.frac accumulated number of 290 output triplets since the start of group 291 */ 292 u32 accumOutTriplets; 293 }; 294 295 /* SCB for Timing master algorithm */ 296 struct dsp_timing_master_scb { 297 /* First 12 dwords from generic_scb_t */ 298 struct dsp_basic_dma_req basic_req; /* Optional */ 299 struct dsp_scatter_gather_ext sg_ext; /* Optional */ 300 ___DSP_DUAL_16BIT_ALLOC( 301 next_scb, /* REQUIRED */ 302 sub_list_ptr /* REQUIRED */ 303 ) 304 305 ___DSP_DUAL_16BIT_ALLOC( 306 entry_point, /* REQUIRED */ 307 this_spb /* REQUIRED */ 308 ) 309 310 ___DSP_DUAL_16BIT_ALLOC( 311 /* Initial values are 0000:xxxx */ 312 reserved, 313 extra_sample_accum 314 ) 315 316 317 /* Initial values are xxxx:0000 318 hi: Current CODEC output FIFO pointer 319 (0 to 0x0f) 320 lo: Flag indicating that the CODEC 321 FIFO is sync'd (host clears to 322 resynchronize the FIFO pointer 323 upon start/restart) 324 */ 325 ___DSP_DUAL_16BIT_ALLOC( 326 codec_FIFO_syncd, 327 codec_FIFO_ptr 328 ) 329 330 /* Init. 8000:0005 for 44.1k 331 8000:0001 for 48k 332 hi: Fractional sample accumulator 0.16b 333 lo: Number of frames remaining to be 334 processed in the current group of 335 frames 336 */ 337 ___DSP_DUAL_16BIT_ALLOC( 338 frac_samp_accum_qm1, 339 TM_frms_left_in_group 340 ) 341 342 /* Init. 0001:0005 for 44.1k 343 0000:0001 for 48k 344 hi: Fractional sample correction factor 0.16b 345 to be added every frameGroupLength frames 346 to correct for truncation error in 347 nsamp_per_frm_q15 348 lo: Number of frames in the group 349 */ 350 ___DSP_DUAL_16BIT_ALLOC( 351 frac_samp_correction_qm1, 352 TM_frm_group_length 353 ) 354 355 /* Init. 44.1k*65536/8k = 0x00058333 for 44.1k 356 48k*65536/8k = 0x00060000 for 48k 357 16b.16b integer.frac approximation to the 358 number of samples to output each frame. 359 (approximation must be floor, to insure */ 360 u32 nsamp_per_frm_q15; 361 }; 362 363 /* SCB for CODEC output algorithm */ 364 struct dsp_codec_output_scb { 365 /* First 13 dwords from generic_scb_t */ 366 struct dsp_basic_dma_req basic_req; /* Optional */ 367 struct dsp_scatter_gather_ext sg_ext; /* Optional */ 368 ___DSP_DUAL_16BIT_ALLOC( 369 next_scb, /* REQUIRED */ 370 sub_list_ptr /* REQUIRED */ 371 ) 372 373 ___DSP_DUAL_16BIT_ALLOC( 374 entry_point, /* REQUIRED */ 375 this_spb /* REQUIRED */ 376 ) 377 378 u32 strm_rs_config; /* REQUIRED */ 379 380 u32 strm_buf_ptr; /* REQUIRED */ 381 382 /* NOTE: The CODEC output task reads samples from the first task on its 383 sublist at the stream buffer pointer (init. to lag DMA destination 384 address word). After the required number of samples is transferred, 385 the CODEC output task advances sub_list_ptr->strm_buf_ptr past the samples 386 consumed. 387 */ 388 389 /* Init. 0000:0010 for SDout 390 0060:0010 for SDout2 391 0080:0010 for SDout3 392 hi: Base IO address of FIFO to which 393 the left-channel samples are to 394 be written. 395 lo: Displacement for the base IO 396 address for left-channel to obtain 397 the base IO address for the FIFO 398 to which the right-channel samples 399 are to be written. 400 */ 401 ___DSP_DUAL_16BIT_ALLOC( 402 left_chan_base_IO_addr, 403 right_chan_IO_disp 404 ) 405 406 407 /* Init: 0x0080:0004 for non-AC-97 408 Init: 0x0080:0000 for AC-97 409 hi: Exponential volume change rate 410 for input stream 411 lo: Positive shift count to shift the 412 16-bit input sample to obtain the 413 32-bit output word 414 */ 415 ___DSP_DUAL_16BIT_ALLOC( 416 CO_scale_shift_count, 417 CO_exp_vol_change_rate 418 ) 419 420 /* Pointer to SCB at end of input chain */ 421 ___DSP_DUAL_16BIT_ALLOC( 422 reserved, 423 last_sub_ptr 424 ) 425 }; 426 427 /* SCB for CODEC input algorithm */ 428 struct dsp_codec_input_scb { 429 /* First 13 dwords from generic_scb_t */ 430 struct dsp_basic_dma_req basic_req; /* Optional */ 431 struct dsp_scatter_gather_ext sg_ext; /* Optional */ 432 ___DSP_DUAL_16BIT_ALLOC( 433 next_scb, /* REQUIRED */ 434 sub_list_ptr /* REQUIRED */ 435 ) 436 437 ___DSP_DUAL_16BIT_ALLOC( 438 entry_point, /* REQUIRED */ 439 this_spb /* REQUIRED */ 440 ) 441 442 u32 strm_rs_config; /* REQUIRED */ 443 u32 strm_buf_ptr; /* REQUIRED */ 444 445 /* NOTE: The CODEC input task reads samples from the hardware FIFO 446 sublist at the DMA source address word (sub_list_ptr->basic_req.saw). 447 After the required number of samples is transferred, the CODEC 448 output task advances sub_list_ptr->basic_req.saw past the samples 449 consumed. SPuD must initialize the sub_list_ptr->basic_req.saw 450 to point half-way around from the initial sub_list_ptr->strm_nuf_ptr 451 to allow for lag/lead. 452 */ 453 454 /* Init. 0000:0010 for SDout 455 0060:0010 for SDout2 456 0080:0010 for SDout3 457 hi: Base IO address of FIFO to which 458 the left-channel samples are to 459 be written. 460 lo: Displacement for the base IO 461 address for left-channel to obtain 462 the base IO address for the FIFO 463 to which the right-channel samples 464 are to be written. 465 */ 466 ___DSP_DUAL_16BIT_ALLOC( 467 rightChanINdisp, 468 left_chan_base_IN_addr 469 ) 470 /* Init. ?:fffc 471 lo: Negative shift count to shift the 472 32-bit input dword to obtain the 473 16-bit sample msb-aligned (count 474 is negative to shift left) 475 */ 476 ___DSP_DUAL_16BIT_ALLOC( 477 scaleShiftCount, 478 reserver1 479 ) 480 481 u32 reserved2; 482 }; 483 484 485 struct dsp_pcm_serial_input_scb { 486 /* First 13 dwords from generic_scb_t */ 487 struct dsp_basic_dma_req basic_req; /* Optional */ 488 struct dsp_scatter_gather_ext sg_ext; /* Optional */ 489 ___DSP_DUAL_16BIT_ALLOC( 490 next_scb, /* REQUIRED */ 491 sub_list_ptr /* REQUIRED */ 492 ) 493 494 ___DSP_DUAL_16BIT_ALLOC( 495 entry_point, /* REQUIRED */ 496 this_spb /* REQUIRED */ 497 ) 498 499 u32 strm_buf_ptr; /* REQUIRED */ 500 u32 strm_rs_config; /* REQUIRED */ 501 502 /* Init. Ptr to CODEC input SCB 503 hi: Pointer to the SCB containing the 504 input buffer to which CODEC input 505 samples are written 506 lo: Flag indicating the link to the CODEC 507 input task is to be initialized 508 */ 509 ___DSP_DUAL_16BIT_ALLOC( 510 init_codec_input_link, 511 codec_input_buf_scb 512 ) 513 514 /* Initialized by the host (host updates target volumes) */ 515 struct dsp_volume_control psi_vol_ctrl; 516 517 }; 518 519 struct dsp_src_task_scb { 520 ___DSP_DUAL_16BIT_ALLOC( 521 frames_left_in_gof, 522 gofs_left_in_sec 523 ) 524 525 ___DSP_DUAL_16BIT_ALLOC( 526 const2_thirds, 527 num_extra_tnput_samples 528 ) 529 530 ___DSP_DUAL_16BIT_ALLOC( 531 cor_per_gof, 532 correction_per_sec 533 ) 534 535 ___DSP_DUAL_16BIT_ALLOC( 536 output_buf_producer_ptr, 537 junk_DMA_MID 538 ) 539 540 ___DSP_DUAL_16BIT_ALLOC( 541 gof_length, 542 gofs_per_sec 543 ) 544 545 u32 input_buf_strm_config; 546 547 ___DSP_DUAL_16BIT_ALLOC( 548 reserved_for_SRC_use, 549 input_buf_consumer_ptr 550 ) 551 552 u32 accum_phi; 553 554 ___DSP_DUAL_16BIT_ALLOC( 555 exp_src_vol_change_rate, 556 input_buf_producer_ptr 557 ) 558 559 ___DSP_DUAL_16BIT_ALLOC( 560 src_next_scb, 561 src_sub_list_ptr 562 ) 563 564 ___DSP_DUAL_16BIT_ALLOC( 565 src_entry_point, 566 src_this_sbp 567 ) 568 569 u32 src_strm_rs_config; 570 u32 src_strm_buf_ptr; 571 572 u32 phiIncr6int_26frac; 573 574 struct dsp_volume_control src_vol_ctrl; 575 }; 576 577 struct dsp_decimate_by_pow2_scb { 578 /* decimationFactor = 2, 4, or 8 (larger factors waste too much memory 579 when compared to cascading decimators) 580 */ 581 ___DSP_DUAL_16BIT_ALLOC( 582 dec2_coef_base_ptr, 583 dec2_coef_increment 584 ) 585 586 /* coefIncrement = 128 / decimationFactor (for our ROM filter) 587 coefBasePtr = 0x8000 (for our ROM filter) 588 */ 589 ___DSP_DUAL_16BIT_ALLOC( 590 dec2_in_samples_per_out_triplet, 591 dec2_extra_in_samples 592 ) 593 /* extraInSamples: # of accumulated, unused input samples (init. to 0) 594 inSamplesPerOutTriplet = 3 * decimationFactor 595 */ 596 597 ___DSP_DUAL_16BIT_ALLOC( 598 dec2_const2_thirds, 599 dec2_half_num_taps_mp5 600 ) 601 /* halfNumTapsM5: (1/2 number of taps in decimation filter) minus 5 602 const2thirds: constant 2/3 in 16Q0 format (sign.15) 603 */ 604 605 ___DSP_DUAL_16BIT_ALLOC( 606 dec2_output_buf_producer_ptr, 607 dec2_junkdma_mid 608 ) 609 610 u32 dec2_reserved2; 611 612 u32 dec2_input_nuf_strm_config; 613 /* inputBufStrmConfig: rsConfig for the input buffer to the decimator 614 (buffer size = decimationFactor * 32 dwords) 615 */ 616 617 ___DSP_DUAL_16BIT_ALLOC( 618 dec2_phi_incr, 619 dec2_input_buf_consumer_ptr 620 ) 621 /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter) 622 phiIncr = decimationFactor * 4 623 */ 624 625 u32 dec2_reserved3; 626 627 ___DSP_DUAL_16BIT_ALLOC( 628 dec2_exp_vol_change_rate, 629 dec2_input_buf_producer_ptr 630 ) 631 /* inputBufProducerPtr: Input buffer write pointer 632 expVolChangeRate: Exponential volume change rate for possible 633 future mixer on input streams 634 */ 635 636 ___DSP_DUAL_16BIT_ALLOC( 637 dec2_next_scb, 638 dec2_sub_list_ptr 639 ) 640 641 ___DSP_DUAL_16BIT_ALLOC( 642 dec2_entry_point, 643 dec2_this_spb 644 ) 645 646 u32 dec2_strm_rs_config; 647 u32 dec2_strm_buf_ptr; 648 649 u32 dec2_reserved4; 650 651 struct dsp_volume_control dec2_vol_ctrl; /* Not used! */ 652 }; 653 654 struct dsp_vari_decimate_scb { 655 ___DSP_DUAL_16BIT_ALLOC( 656 vdec_frames_left_in_gof, 657 vdec_gofs_left_in_sec 658 ) 659 660 ___DSP_DUAL_16BIT_ALLOC( 661 vdec_const2_thirds, 662 vdec_extra_in_samples 663 ) 664 /* extraInSamples: # of accumulated, unused input samples (init. to 0) 665 const2thirds: constant 2/3 in 16Q0 format (sign.15) */ 666 667 ___DSP_DUAL_16BIT_ALLOC( 668 vdec_cor_per_gof, 669 vdec_correction_per_sec 670 ) 671 672 ___DSP_DUAL_16BIT_ALLOC( 673 vdec_output_buf_producer_ptr, 674 vdec_input_buf_consumer_ptr 675 ) 676 /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter) */ 677 ___DSP_DUAL_16BIT_ALLOC( 678 vdec_gof_length, 679 vdec_gofs_per_sec 680 ) 681 682 u32 vdec_input_buf_strm_config; 683 /* inputBufStrmConfig: rsConfig for the input buffer to the decimator 684 (buffer size = 64 dwords) */ 685 u32 vdec_coef_increment; 686 /* coefIncrement = - 128.0 / decimationFactor (as a 32Q15 number) */ 687 688 u32 vdec_accumphi; 689 /* accumPhi: accumulated fractional phase increment (6.26) */ 690 691 ___DSP_DUAL_16BIT_ALLOC( 692 vdec_exp_vol_change_rate, 693 vdec_input_buf_producer_ptr 694 ) 695 /* inputBufProducerPtr: Input buffer write pointer 696 expVolChangeRate: Exponential volume change rate for possible 697 future mixer on input streams */ 698 699 ___DSP_DUAL_16BIT_ALLOC( 700 vdec_next_scb, 701 vdec_sub_list_ptr 702 ) 703 704 ___DSP_DUAL_16BIT_ALLOC( 705 vdec_entry_point, 706 vdec_this_spb 707 ) 708 709 u32 vdec_strm_rs_config; 710 u32 vdec_strm_buf_ptr; 711 712 u32 vdec_phi_incr_6int_26frac; 713 714 struct dsp_volume_control vdec_vol_ctrl; 715 }; 716 717 718 /* SCB for MIX_TO_OSTREAM algorithm family */ 719 struct dsp_mix2_ostream_scb { 720 /* First 13 dwords from generic_scb_t */ 721 struct dsp_basic_dma_req basic_req; /* Optional */ 722 struct dsp_scatter_gather_ext sg_ext; /* Optional */ 723 ___DSP_DUAL_16BIT_ALLOC( 724 next_scb, /* REQUIRED */ 725 sub_list_ptr /* REQUIRED */ 726 ) 727 728 ___DSP_DUAL_16BIT_ALLOC( 729 entry_point, /* REQUIRED */ 730 this_spb /* REQUIRED */ 731 ) 732 733 u32 strm_rs_config; /* REQUIRED */ 734 u32 strm_buf_ptr; /* REQUIRED */ 735 736 737 /* hi: Number of mixed-down input triplets 738 computed since start of group 739 lo: Number of frames remaining to be 740 processed in the current group of 741 frames 742 */ 743 ___DSP_DUAL_16BIT_ALLOC( 744 frames_left_in_group, 745 accum_input_triplets 746 ) 747 748 /* hi: Exponential volume change rate 749 for mixer on input streams 750 lo: Number of frames in the group 751 */ 752 ___DSP_DUAL_16BIT_ALLOC( 753 frame_group_length, 754 exp_vol_change_rate 755 ) 756 757 ___DSP_DUAL_16BIT_ALLOC( 758 const_FFFF, 759 const_zero 760 ) 761 }; 762 763 764 /* SCB for S16_MIX algorithm */ 765 struct dsp_mix_only_scb { 766 /* First 13 dwords from generic_scb_t */ 767 struct dsp_basic_dma_req basic_req; /* Optional */ 768 struct dsp_scatter_gather_ext sg_ext; /* Optional */ 769 ___DSP_DUAL_16BIT_ALLOC( 770 next_scb, /* REQUIRED */ 771 sub_list_ptr /* REQUIRED */ 772 ) 773 774 ___DSP_DUAL_16BIT_ALLOC( 775 entry_point, /* REQUIRED */ 776 this_spb /* REQUIRED */ 777 ) 778 779 u32 strm_rs_config; /* REQUIRED */ 780 u32 strm_buf_ptr; /* REQUIRED */ 781 782 u32 reserved; 783 struct dsp_volume_control vol_ctrl; 784 }; 785 786 /* SCB for the async. CODEC input algorithm */ 787 struct dsp_async_codec_input_scb { 788 u32 io_free2; 789 790 u32 io_current_total; 791 u32 io_previous_total; 792 793 u16 io_count; 794 u16 io_count_limit; 795 796 u16 o_fifo_base_addr; 797 u16 ost_mo_format; 798 /* 1 = stereo; 0 = mono 799 xxx for ASER 1 (not allowed); 118 for ASER2 */ 800 801 u32 ostrm_rs_config; 802 u32 ostrm_buf_ptr; 803 804 ___DSP_DUAL_16BIT_ALLOC( 805 io_sclks_per_lr_clk, 806 io_io_enable 807 ) 808 809 u32 io_free4; 810 811 ___DSP_DUAL_16BIT_ALLOC( 812 io_next_scb, 813 io_sub_list_ptr 814 ) 815 816 ___DSP_DUAL_16BIT_ALLOC( 817 io_entry_point, 818 io_this_spb 819 ) 820 821 u32 istrm_rs_config; 822 u32 istrm_buf_ptr; 823 824 /* Init. 0000:8042: for ASER1 825 0000:8044: for ASER2 */ 826 ___DSP_DUAL_16BIT_ALLOC( 827 io_stat_reg_addr, 828 iofifo_pointer 829 ) 830 831 /* Init 1 stero:100 ASER1 832 Init 0 mono:110 ASER2 833 */ 834 ___DSP_DUAL_16BIT_ALLOC( 835 ififo_base_addr, 836 ist_mo_format 837 ) 838 839 u32 i_free; 840 }; 841 842 843 /* SCB for the SP/DIF CODEC input and output */ 844 struct dsp_spdifiscb { 845 ___DSP_DUAL_16BIT_ALLOC( 846 status_ptr, 847 status_start_ptr 848 ) 849 850 u32 current_total; 851 u32 previous_total; 852 853 ___DSP_DUAL_16BIT_ALLOC( 854 count, 855 count_limit 856 ) 857 858 u32 status_data; 859 860 ___DSP_DUAL_16BIT_ALLOC( 861 status, 862 free4 863 ) 864 865 u32 free3; 866 867 ___DSP_DUAL_16BIT_ALLOC( 868 free2, 869 bit_count 870 ) 871 872 u32 temp_status; 873 874 ___DSP_DUAL_16BIT_ALLOC( 875 next_SCB, 876 sub_list_ptr 877 ) 878 879 ___DSP_DUAL_16BIT_ALLOC( 880 entry_point, 881 this_spb 882 ) 883 884 u32 strm_rs_config; 885 u32 strm_buf_ptr; 886 887 ___DSP_DUAL_16BIT_ALLOC( 888 stat_reg_addr, 889 fifo_pointer 890 ) 891 892 ___DSP_DUAL_16BIT_ALLOC( 893 fifo_base_addr, 894 st_mo_format 895 ) 896 897 u32 free1; 898 }; 899 900 901 /* SCB for the SP/DIF CODEC input and output */ 902 struct dsp_spdifoscb { 903 904 u32 free2; 905 906 u32 free3[4]; 907 908 /* Need to be here for compatibility with AsynchFGTxCode */ 909 u32 strm_rs_config; 910 911 u32 strm_buf_ptr; 912 913 ___DSP_DUAL_16BIT_ALLOC( 914 status, 915 free5 916 ) 917 918 u32 free4; 919 920 ___DSP_DUAL_16BIT_ALLOC( 921 next_scb, 922 sub_list_ptr 923 ) 924 925 ___DSP_DUAL_16BIT_ALLOC( 926 entry_point, 927 this_spb 928 ) 929 930 u32 free6[2]; 931 932 ___DSP_DUAL_16BIT_ALLOC( 933 stat_reg_addr, 934 fifo_pointer 935 ) 936 937 ___DSP_DUAL_16BIT_ALLOC( 938 fifo_base_addr, 939 st_mo_format 940 ) 941 942 u32 free1; 943 }; 944 945 946 struct dsp_asynch_fg_rx_scb { 947 ___DSP_DUAL_16BIT_ALLOC( 948 bot_buf_mask, 949 buf_Mask 950 ) 951 952 ___DSP_DUAL_16BIT_ALLOC( 953 max, 954 min 955 ) 956 957 ___DSP_DUAL_16BIT_ALLOC( 958 old_producer_pointer, 959 hfg_scb_ptr 960 ) 961 962 ___DSP_DUAL_16BIT_ALLOC( 963 delta, 964 adjust_count 965 ) 966 967 u32 unused2[5]; 968 969 ___DSP_DUAL_16BIT_ALLOC( 970 sibling_ptr, 971 child_ptr 972 ) 973 974 ___DSP_DUAL_16BIT_ALLOC( 975 code_ptr, 976 this_ptr 977 ) 978 979 u32 strm_rs_config; 980 981 u32 strm_buf_ptr; 982 983 u32 unused_phi_incr; 984 985 ___DSP_DUAL_16BIT_ALLOC( 986 right_targ, 987 left_targ 988 ) 989 990 ___DSP_DUAL_16BIT_ALLOC( 991 right_vol, 992 left_vol 993 ) 994 }; 995 996 997 struct dsp_asynch_fg_tx_scb { 998 ___DSP_DUAL_16BIT_ALLOC( 999 not_buf_mask, 1000 buf_mask 1001 ) 1002 1003 ___DSP_DUAL_16BIT_ALLOC( 1004 max, 1005 min 1006 ) 1007 1008 ___DSP_DUAL_16BIT_ALLOC( 1009 unused1, 1010 hfg_scb_ptr 1011 ) 1012 1013 ___DSP_DUAL_16BIT_ALLOC( 1014 delta, 1015 adjust_count 1016 ) 1017 1018 u32 accum_phi; 1019 1020 ___DSP_DUAL_16BIT_ALLOC( 1021 unused2, 1022 const_one_third 1023 ) 1024 1025 u32 unused3[3]; 1026 1027 ___DSP_DUAL_16BIT_ALLOC( 1028 sibling_ptr, 1029 child_ptr 1030 ) 1031 1032 ___DSP_DUAL_16BIT_ALLOC( 1033 codePtr, 1034 this_ptr 1035 ) 1036 1037 u32 strm_rs_config; 1038 1039 u32 strm_buf_ptr; 1040 1041 u32 phi_incr; 1042 1043 ___DSP_DUAL_16BIT_ALLOC( 1044 unused_right_targ, 1045 unused_left_targ 1046 ) 1047 1048 ___DSP_DUAL_16BIT_ALLOC( 1049 unused_right_vol, 1050 unused_left_vol 1051 ) 1052 }; 1053 1054 1055 struct dsp_output_snoop_scb { 1056 /* First 13 dwords from generic_scb_t */ 1057 struct dsp_basic_dma_req basic_req; /* Optional */ 1058 struct dsp_scatter_gather_ext sg_ext; /* Optional */ 1059 ___DSP_DUAL_16BIT_ALLOC( 1060 next_scb, /* REQUIRED */ 1061 sub_list_ptr /* REQUIRED */ 1062 ) 1063 1064 ___DSP_DUAL_16BIT_ALLOC( 1065 entry_point, /* REQUIRED */ 1066 this_spb /* REQUIRED */ 1067 ) 1068 1069 u32 strm_rs_config; /* REQUIRED */ 1070 u32 strm_buf_ptr; /* REQUIRED */ 1071 1072 ___DSP_DUAL_16BIT_ALLOC( 1073 init_snoop_input_link, 1074 snoop_child_input_scb 1075 ) 1076 1077 u32 snoop_input_buf_ptr; 1078 1079 ___DSP_DUAL_16BIT_ALLOC( 1080 reserved, 1081 input_scb 1082 ) 1083 }; 1084 1085 struct dsp_spio_write_scb { 1086 ___DSP_DUAL_16BIT_ALLOC( 1087 address1, 1088 address2 1089 ) 1090 1091 u32 data1; 1092 1093 u32 data2; 1094 1095 ___DSP_DUAL_16BIT_ALLOC( 1096 address3, 1097 address4 1098 ) 1099 1100 u32 data3; 1101 1102 u32 data4; 1103 1104 ___DSP_DUAL_16BIT_ALLOC( 1105 unused1, 1106 data_ptr 1107 ) 1108 1109 u32 unused2[2]; 1110 1111 ___DSP_DUAL_16BIT_ALLOC( 1112 sibling_ptr, 1113 child_ptr 1114 ) 1115 1116 ___DSP_DUAL_16BIT_ALLOC( 1117 entry_point, 1118 this_ptr 1119 ) 1120 1121 u32 unused3[5]; 1122 }; 1123 1124 struct dsp_magic_snoop_task { 1125 u32 i0; 1126 u32 i1; 1127 1128 u32 strm_buf_ptr1; 1129 1130 u16 i2; 1131 u16 snoop_scb; 1132 1133 u32 i3; 1134 u32 i4; 1135 u32 i5; 1136 u32 i6; 1137 1138 u32 i7; 1139 1140 ___DSP_DUAL_16BIT_ALLOC( 1141 next_scb, 1142 sub_list_ptr 1143 ) 1144 1145 ___DSP_DUAL_16BIT_ALLOC( 1146 entry_point, 1147 this_ptr 1148 ) 1149 1150 u32 strm_buf_config; 1151 u32 strm_buf_ptr2; 1152 1153 u32 i8; 1154 1155 struct dsp_volume_control vdec_vol_ctrl; 1156 }; 1157 1158 1159 struct dsp_filter_scb { 1160 ___DSP_DUAL_16BIT_ALLOC( 1161 a0_right, /* 0x00 */ 1162 a0_left 1163 ) 1164 ___DSP_DUAL_16BIT_ALLOC( 1165 a1_right, /* 0x01 */ 1166 a1_left 1167 ) 1168 ___DSP_DUAL_16BIT_ALLOC( 1169 a2_right, /* 0x02 */ 1170 a2_left 1171 ) 1172 ___DSP_DUAL_16BIT_ALLOC( 1173 output_buf_ptr, /* 0x03 */ 1174 init 1175 ) 1176 1177 ___DSP_DUAL_16BIT_ALLOC( 1178 filter_unused3, /* 0x04 */ 1179 filter_unused2 1180 ) 1181 1182 u32 prev_sample_output1; /* 0x05 */ 1183 u32 prev_sample_output2; /* 0x06 */ 1184 u32 prev_sample_input1; /* 0x07 */ 1185 u32 prev_sample_input2; /* 0x08 */ 1186 1187 ___DSP_DUAL_16BIT_ALLOC( 1188 next_scb_ptr, /* 0x09 */ 1189 sub_list_ptr 1190 ) 1191 1192 ___DSP_DUAL_16BIT_ALLOC( 1193 entry_point, /* 0x0A */ 1194 spb_ptr 1195 ) 1196 1197 u32 strm_rs_config; /* 0x0B */ 1198 u32 strm_buf_ptr; /* 0x0C */ 1199 1200 ___DSP_DUAL_16BIT_ALLOC( 1201 b0_right, /* 0x0D */ 1202 b0_left 1203 ) 1204 ___DSP_DUAL_16BIT_ALLOC( 1205 b1_right, /* 0x0E */ 1206 b1_left 1207 ) 1208 ___DSP_DUAL_16BIT_ALLOC( 1209 b2_right, /* 0x0F */ 1210 b2_left 1211 ) 1212 }; 1213 #endif /* __DSP_SCB_TYPES_H__ */ 1214
